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powerpc: manroland: remove uc100, uc101, mucmc52, hmi1001 support
[people/ms/u-boot.git] / drivers / net / mpc5xxx_fec.c
1 /*
2 * (C) Copyright 2003-2010
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * This file is based on mpc4200fec.c,
6 * (C) Copyright Motorola, Inc., 2000
7 */
8
9 #include <common.h>
10 #include <mpc5xxx.h>
11 #include <mpc5xxx_sdma.h>
12 #include <malloc.h>
13 #include <net.h>
14 #include <netdev.h>
15 #include <miiphy.h>
16 #include "mpc5xxx_fec.h"
17
18 DECLARE_GLOBAL_DATA_PTR;
19
20 /* #define DEBUG 0x28 */
21
22 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
23 #error "CONFIG_MII has to be defined!"
24 #endif
25
26 #if (DEBUG & 0x60)
27 static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec);
28 static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec);
29 #endif /* DEBUG */
30
31 typedef struct {
32 uint8 data[1500]; /* actual data */
33 int length; /* actual length */
34 int used; /* buffer in use or not */
35 uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
36 } NBUF;
37
38 int fec5xxx_miiphy_read(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 *retVal);
39 int fec5xxx_miiphy_write(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
40
41 static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis);
42
43 /********************************************************************/
44 #if (DEBUG & 0x2)
45 static void mpc5xxx_fec_phydump (char *devname)
46 {
47 uint16 phyStatus, i;
48 uint8 phyAddr = CONFIG_PHY_ADDR;
49 uint8 reg_mask[] = {
50 #if CONFIG_PHY_TYPE == 0x79c874 /* AMD Am79C874 */
51 /* regs to print: 0...7, 16...19, 21, 23, 24 */
52 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
53 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0,
54 #else
55 /* regs to print: 0...8, 16...20 */
56 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
57 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
58 #endif
59 };
60
61 for (i = 0; i < 32; i++) {
62 if (reg_mask[i]) {
63 miiphy_read(devname, phyAddr, i, &phyStatus);
64 printf("Mii reg %d: 0x%04x\n", i, phyStatus);
65 }
66 }
67 }
68 #endif
69
70 /********************************************************************/
71 static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec)
72 {
73 int ix;
74 char *data;
75 static int once = 0;
76
77 for (ix = 0; ix < FEC_RBD_NUM; ix++) {
78 if (!once) {
79 data = (char *)malloc(FEC_MAX_PKT_SIZE);
80 if (data == NULL) {
81 printf ("RBD INIT FAILED\n");
82 return -1;
83 }
84 fec->rbdBase[ix].dataPointer = (uint32)data;
85 }
86 fec->rbdBase[ix].status = FEC_RBD_EMPTY;
87 fec->rbdBase[ix].dataLength = 0;
88 }
89 once ++;
90
91 /*
92 * have the last RBD to close the ring
93 */
94 fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP;
95 fec->rbdIndex = 0;
96
97 return 0;
98 }
99
100 /********************************************************************/
101 static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec)
102 {
103 int ix;
104
105 for (ix = 0; ix < FEC_TBD_NUM; ix++) {
106 fec->tbdBase[ix].status = 0;
107 }
108
109 /*
110 * Have the last TBD to close the ring
111 */
112 fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP;
113
114 /*
115 * Initialize some indices
116 */
117 fec->tbdIndex = 0;
118 fec->usedTbdIndex = 0;
119 fec->cleanTbdNum = FEC_TBD_NUM;
120 }
121
122 /********************************************************************/
123 static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, volatile FEC_RBD * pRbd)
124 {
125 /*
126 * Reset buffer descriptor as empty
127 */
128 if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
129 pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
130 else
131 pRbd->status = FEC_RBD_EMPTY;
132
133 pRbd->dataLength = 0;
134
135 /*
136 * Now, we have an empty RxBD, restart the SmartDMA receive task
137 */
138 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
139
140 /*
141 * Increment BD count
142 */
143 fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
144 }
145
146 /********************************************************************/
147 static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec)
148 {
149 volatile FEC_TBD *pUsedTbd;
150
151 #if (DEBUG & 0x1)
152 printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
153 fec->cleanTbdNum, fec->usedTbdIndex);
154 #endif
155
156 /*
157 * process all the consumed TBDs
158 */
159 while (fec->cleanTbdNum < FEC_TBD_NUM) {
160 pUsedTbd = &fec->tbdBase[fec->usedTbdIndex];
161 if (pUsedTbd->status & FEC_TBD_READY) {
162 #if (DEBUG & 0x20)
163 printf("Cannot clean TBD %d, in use\n", fec->cleanTbdNum);
164 #endif
165 return;
166 }
167
168 /*
169 * clean this buffer descriptor
170 */
171 if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
172 pUsedTbd->status = FEC_TBD_WRAP;
173 else
174 pUsedTbd->status = 0;
175
176 /*
177 * update some indeces for a correct handling of the TBD ring
178 */
179 fec->cleanTbdNum++;
180 fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
181 }
182 }
183
184 /********************************************************************/
185 static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac)
186 {
187 uint8 currByte; /* byte for which to compute the CRC */
188 int byte; /* loop - counter */
189 int bit; /* loop - counter */
190 uint32 crc = 0xffffffff; /* initial value */
191
192 /*
193 * The algorithm used is the following:
194 * we loop on each of the six bytes of the provided address,
195 * and we compute the CRC by left-shifting the previous
196 * value by one position, so that each bit in the current
197 * byte of the address may contribute the calculation. If
198 * the latter and the MSB in the CRC are different, then
199 * the CRC value so computed is also ex-ored with the
200 * "polynomium generator". The current byte of the address
201 * is also shifted right by one bit at each iteration.
202 * This is because the CRC generatore in hardware is implemented
203 * as a shift-register with as many ex-ores as the radixes
204 * in the polynomium. This suggests that we represent the
205 * polynomiumm itself as a 32-bit constant.
206 */
207 for (byte = 0; byte < 6; byte++) {
208 currByte = mac[byte];
209 for (bit = 0; bit < 8; bit++) {
210 if ((currByte & 0x01) ^ (crc & 0x01)) {
211 crc >>= 1;
212 crc = crc ^ 0xedb88320;
213 } else {
214 crc >>= 1;
215 }
216 currByte >>= 1;
217 }
218 }
219
220 crc = crc >> 26;
221
222 /*
223 * Set individual hash table register
224 */
225 if (crc >= 32) {
226 fec->eth->iaddr1 = (1 << (crc - 32));
227 fec->eth->iaddr2 = 0;
228 } else {
229 fec->eth->iaddr1 = 0;
230 fec->eth->iaddr2 = (1 << crc);
231 }
232
233 /*
234 * Set physical address
235 */
236 fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
237 fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
238 }
239
240 /********************************************************************/
241 static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
242 {
243 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
244 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
245
246 #if (DEBUG & 0x1)
247 printf ("mpc5xxx_fec_init... Begin\n");
248 #endif
249
250 mpc5xxx_fec_init_phy(dev, bis);
251
252 /*
253 * Call board-specific PHY fixups (if any)
254 */
255 #ifdef CONFIG_RESET_PHY_R
256 reset_phy();
257 #endif
258
259 /*
260 * Initialize RxBD/TxBD rings
261 */
262 mpc5xxx_fec_rbd_init(fec);
263 mpc5xxx_fec_tbd_init(fec);
264
265 /*
266 * Clear FEC-Lite interrupt event register(IEVENT)
267 */
268 fec->eth->ievent = 0xffffffff;
269
270 /*
271 * Set interrupt mask register
272 */
273 fec->eth->imask = 0x00000000;
274
275 /*
276 * Set FEC-Lite receive control register(R_CNTRL):
277 */
278 if (fec->xcv_type == SEVENWIRE) {
279 /*
280 * Frame length=1518; 7-wire mode
281 */
282 fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */
283 } else {
284 /*
285 * Frame length=1518; MII mode;
286 */
287 fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */
288 }
289
290 fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */
291
292 /*
293 * Set Opcode/Pause Duration Register
294 */
295 fec->eth->op_pause = 0x00010020; /*FIXME 0xffff0020; */
296
297 /*
298 * Set Rx FIFO alarm and granularity value
299 */
300 fec->eth->rfifo_cntrl = 0x0c000000
301 | (fec->eth->rfifo_cntrl & ~0x0f000000);
302 fec->eth->rfifo_alarm = 0x0000030c;
303 #if (DEBUG & 0x22)
304 if (fec->eth->rfifo_status & 0x00700000 ) {
305 printf("mpc5xxx_fec_init() RFIFO error\n");
306 }
307 #endif
308
309 /*
310 * Set Tx FIFO granularity value
311 */
312 fec->eth->tfifo_cntrl = 0x0c000000
313 | (fec->eth->tfifo_cntrl & ~0x0f000000);
314 #if (DEBUG & 0x2)
315 printf("tfifo_status: 0x%08x\n", fec->eth->tfifo_status);
316 printf("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm);
317 #endif
318
319 /*
320 * Set transmit fifo watermark register(X_WMRK), default = 64
321 */
322 fec->eth->tfifo_alarm = 0x00000080;
323 fec->eth->x_wmrk = 0x2;
324
325 /*
326 * Set individual address filter for unicast address
327 * and set physical address registers.
328 */
329 mpc5xxx_fec_set_hwaddr(fec, (char *)dev->enetaddr);
330
331 /*
332 * Set multicast address filter
333 */
334 fec->eth->gaddr1 = 0x00000000;
335 fec->eth->gaddr2 = 0x00000000;
336
337 /*
338 * Turn ON cheater FSM: ????
339 */
340 fec->eth->xmit_fsm = 0x03000000;
341
342 /*
343 * Turn off COMM bus prefetch in the MPC5200 BestComm. It doesn't
344 * work w/ the current receive task.
345 */
346 sdma->PtdCntrl |= 0x00000001;
347
348 /*
349 * Set priority of different initiators
350 */
351 sdma->IPR0 = 7; /* always */
352 sdma->IPR3 = 6; /* Eth RX */
353 sdma->IPR4 = 5; /* Eth Tx */
354
355 /*
356 * Clear SmartDMA task interrupt pending bits
357 */
358 SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO);
359
360 /*
361 * Initialize SmartDMA parameters stored in SRAM
362 */
363 *(volatile int *)FEC_TBD_BASE = (int)fec->tbdBase;
364 *(volatile int *)FEC_RBD_BASE = (int)fec->rbdBase;
365 *(volatile int *)FEC_TBD_NEXT = (int)fec->tbdBase;
366 *(volatile int *)FEC_RBD_NEXT = (int)fec->rbdBase;
367
368 /*
369 * Enable FEC-Lite controller
370 */
371 fec->eth->ecntrl |= 0x00000006;
372
373 #if (DEBUG & 0x2)
374 if (fec->xcv_type != SEVENWIRE)
375 mpc5xxx_fec_phydump (dev->name);
376 #endif
377
378 /*
379 * Enable SmartDMA receive task
380 */
381 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
382
383 #if (DEBUG & 0x1)
384 printf("mpc5xxx_fec_init... Done \n");
385 #endif
386
387 return 1;
388 }
389
390 /********************************************************************/
391 static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
392 {
393 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
394 const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
395 static int initialized = 0;
396
397 if(initialized)
398 return 0;
399 initialized = 1;
400
401 #if (DEBUG & 0x1)
402 printf ("mpc5xxx_fec_init_phy... Begin\n");
403 #endif
404
405 /*
406 * Initialize GPIO pins
407 */
408 if (fec->xcv_type == SEVENWIRE) {
409 /* 10MBit with 7-wire operation */
410 #if defined(CONFIG_TOTAL5200)
411 /* 7-wire and USB2 on Ethernet */
412 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00030000;
413 #else /* !CONFIG_TOTAL5200 */
414 /* 7-wire only */
415 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000;
416 #endif /* CONFIG_TOTAL5200 */
417 } else {
418 /* 100MBit with MD operation */
419 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000;
420 }
421
422 /*
423 * Clear FEC-Lite interrupt event register(IEVENT)
424 */
425 fec->eth->ievent = 0xffffffff;
426
427 /*
428 * Set interrupt mask register
429 */
430 fec->eth->imask = 0x00000000;
431
432 /*
433 * In original Promess-provided code PHY initialization is disabled with the
434 * following comment: "Phy initialization is DISABLED for now. There was a
435 * problem with running 100 Mbps on PRO board". Thus we temporarily disable
436 * PHY initialization for the Motion-PRO board, until a proper fix is found.
437 */
438
439 if (fec->xcv_type != SEVENWIRE) {
440 /*
441 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
442 * and do not drop the Preamble.
443 * No MII for 7-wire mode
444 */
445 fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1);
446 }
447
448 if (fec->xcv_type != SEVENWIRE) {
449 /*
450 * Initialize PHY(LXT971A):
451 *
452 * Generally, on power up, the LXT971A reads its configuration
453 * pins to check for forced operation, If not cofigured for
454 * forced operation, it uses auto-negotiation/parallel detection
455 * to automatically determine line operating conditions.
456 * If the PHY device on the other side of the link supports
457 * auto-negotiation, the LXT971A auto-negotiates with it
458 * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not
459 * support auto-negotiation, the LXT971A automatically detects
460 * the presence of either link pulses(10Mbps PHY) or Idle
461 * symbols(100Mbps) and sets its operating conditions accordingly.
462 *
463 * When auto-negotiation is controlled by software, the following
464 * steps are recommended.
465 *
466 * Note:
467 * The physical address is dependent on hardware configuration.
468 *
469 */
470 int timeout = 1;
471 uint16 phyStatus;
472
473 /*
474 * Reset PHY, then delay 300ns
475 */
476 miiphy_write(dev->name, phyAddr, 0x0, 0x8000);
477 udelay(1000);
478
479 if (fec->xcv_type == MII10) {
480 /*
481 * Force 10Base-T, FDX operation
482 */
483 #if (DEBUG & 0x2)
484 printf("Forcing 10 Mbps ethernet link... ");
485 #endif
486 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
487 /*
488 miiphy_write(dev->name, fec, phyAddr, 0x0, 0x0100);
489 */
490 miiphy_write(dev->name, phyAddr, 0x0, 0x0180);
491
492 timeout = 20;
493 do { /* wait for link status to go down */
494 udelay(10000);
495 if ((timeout--) == 0) {
496 #if (DEBUG & 0x2)
497 printf("hmmm, should not have waited...");
498 #endif
499 break;
500 }
501 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
502 #if (DEBUG & 0x2)
503 printf("=");
504 #endif
505 } while ((phyStatus & 0x0004)); /* !link up */
506
507 timeout = 1000;
508 do { /* wait for link status to come back up */
509 udelay(10000);
510 if ((timeout--) == 0) {
511 printf("failed. Link is down.\n");
512 break;
513 }
514 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
515 #if (DEBUG & 0x2)
516 printf("+");
517 #endif
518 } while (!(phyStatus & 0x0004)); /* !link up */
519
520 #if (DEBUG & 0x2)
521 printf ("done.\n");
522 #endif
523 } else { /* MII100 */
524 /*
525 * Set the auto-negotiation advertisement register bits
526 */
527 miiphy_write(dev->name, phyAddr, 0x4, 0x01e1);
528
529 /*
530 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
531 */
532 miiphy_write(dev->name, phyAddr, 0x0, 0x1200);
533
534 /*
535 * Wait for AN completion
536 */
537 timeout = 5000;
538 do {
539 udelay(1000);
540
541 if ((timeout--) == 0) {
542 #if (DEBUG & 0x2)
543 printf("PHY auto neg 0 failed...\n");
544 #endif
545 return -1;
546 }
547
548 if (miiphy_read(dev->name, phyAddr, 0x1, &phyStatus) != 0) {
549 #if (DEBUG & 0x2)
550 printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
551 #endif
552 return -1;
553 }
554 } while (!(phyStatus & 0x0004));
555
556 #if (DEBUG & 0x2)
557 printf("PHY auto neg complete! \n");
558 #endif
559 }
560
561 }
562
563 #if (DEBUG & 0x2)
564 if (fec->xcv_type != SEVENWIRE)
565 mpc5xxx_fec_phydump (dev->name);
566 #endif
567
568
569 #if (DEBUG & 0x1)
570 printf("mpc5xxx_fec_init_phy... Done \n");
571 #endif
572
573 return 1;
574 }
575
576 /********************************************************************/
577 static void mpc5xxx_fec_halt(struct eth_device *dev)
578 {
579 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
580 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
581 int counter = 0xffff;
582
583 #if (DEBUG & 0x2)
584 if (fec->xcv_type != SEVENWIRE)
585 mpc5xxx_fec_phydump (dev->name);
586 #endif
587
588 /*
589 * mask FEC chip interrupts
590 */
591 fec->eth->imask = 0;
592
593 /*
594 * issue graceful stop command to the FEC transmitter if necessary
595 */
596 fec->eth->x_cntrl |= 0x00000001;
597
598 /*
599 * wait for graceful stop to register
600 */
601 while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;
602
603 /*
604 * Disable SmartDMA tasks
605 */
606 SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
607 SDMA_TASK_DISABLE (FEC_RECV_TASK_NO);
608
609 /*
610 * Turn on COMM bus prefetch in the MPC5200 BestComm after we're
611 * done. It doesn't work w/ the current receive task.
612 */
613 sdma->PtdCntrl &= ~0x00000001;
614
615 /*
616 * Disable the Ethernet Controller
617 */
618 fec->eth->ecntrl &= 0xfffffffd;
619
620 /*
621 * Clear FIFO status registers
622 */
623 fec->eth->rfifo_status &= 0x00700000;
624 fec->eth->tfifo_status &= 0x00700000;
625
626 fec->eth->reset_cntrl = 0x01000000;
627
628 /*
629 * Issue a reset command to the FEC chip
630 */
631 fec->eth->ecntrl |= 0x1;
632
633 /*
634 * wait at least 16 clock cycles
635 */
636 udelay(10);
637
638 /* don't leave the MII speed set to zero */
639 if (fec->xcv_type != SEVENWIRE) {
640 /*
641 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
642 * and do not drop the Preamble.
643 * No MII for 7-wire mode
644 */
645 fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1);
646 }
647
648 #if (DEBUG & 0x3)
649 printf("Ethernet task stopped\n");
650 #endif
651 }
652
653 #if (DEBUG & 0x60)
654 /********************************************************************/
655
656 static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec)
657 {
658 uint16 phyAddr = CONFIG_PHY_ADDR;
659 uint16 phyStatus;
660
661 if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
662 || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
663
664 miiphy_read(devname, phyAddr, 0x1, &phyStatus);
665 printf("\nphyStatus: 0x%04x\n", phyStatus);
666 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
667 printf("ievent: 0x%08x\n", fec->eth->ievent);
668 printf("x_status: 0x%08x\n", fec->eth->x_status);
669 printf("tfifo: status 0x%08x\n", fec->eth->tfifo_status);
670
671 printf(" control 0x%08x\n", fec->eth->tfifo_cntrl);
672 printf(" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr);
673 printf(" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr);
674 printf(" alarm 0x%08x\n", fec->eth->tfifo_alarm);
675 printf(" readptr 0x%08x\n", fec->eth->tfifo_rdptr);
676 printf(" writptr 0x%08x\n", fec->eth->tfifo_wrptr);
677 }
678 }
679
680 static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec)
681 {
682 uint16 phyAddr = CONFIG_PHY_ADDR;
683 uint16 phyStatus;
684
685 if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
686 || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
687
688 miiphy_read(devname, phyAddr, 0x1, &phyStatus);
689 printf("\nphyStatus: 0x%04x\n", phyStatus);
690 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
691 printf("ievent: 0x%08x\n", fec->eth->ievent);
692 printf("x_status: 0x%08x\n", fec->eth->x_status);
693 printf("rfifo: status 0x%08x\n", fec->eth->rfifo_status);
694
695 printf(" control 0x%08x\n", fec->eth->rfifo_cntrl);
696 printf(" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr);
697 printf(" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr);
698 printf(" alarm 0x%08x\n", fec->eth->rfifo_alarm);
699 printf(" readptr 0x%08x\n", fec->eth->rfifo_rdptr);
700 printf(" writptr 0x%08x\n", fec->eth->rfifo_wrptr);
701 }
702 }
703 #endif /* DEBUG */
704
705 /********************************************************************/
706
707 static int mpc5xxx_fec_send(struct eth_device *dev, void *eth_data,
708 int data_length)
709 {
710 /*
711 * This routine transmits one frame. This routine only accepts
712 * 6-byte Ethernet addresses.
713 */
714 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
715 volatile FEC_TBD *pTbd;
716
717 #if (DEBUG & 0x20)
718 printf("tbd status: 0x%04x\n", fec->tbdBase[0].status);
719 tfifo_print(dev->name, fec);
720 #endif
721
722 /*
723 * Clear Tx BD ring at first
724 */
725 mpc5xxx_fec_tbd_scrub(fec);
726
727 /*
728 * Check for valid length of data.
729 */
730 if ((data_length > 1500) || (data_length <= 0)) {
731 return -1;
732 }
733
734 /*
735 * Check the number of vacant TxBDs.
736 */
737 if (fec->cleanTbdNum < 1) {
738 #if (DEBUG & 0x20)
739 printf("No available TxBDs ...\n");
740 #endif
741 return -1;
742 }
743
744 /*
745 * Get the first TxBD to send the mac header
746 */
747 pTbd = &fec->tbdBase[fec->tbdIndex];
748 pTbd->dataLength = data_length;
749 pTbd->dataPointer = (uint32)eth_data;
750 pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
751 fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
752
753 #if (DEBUG & 0x100)
754 printf("SDMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex);
755 #endif
756
757 /*
758 * Kick the MII i/f
759 */
760 if (fec->xcv_type != SEVENWIRE) {
761 uint16 phyStatus;
762 miiphy_read(dev->name, 0, 0x1, &phyStatus);
763 }
764
765 /*
766 * Enable SmartDMA transmit task
767 */
768
769 #if (DEBUG & 0x20)
770 tfifo_print(dev->name, fec);
771 #endif
772 SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
773 #if (DEBUG & 0x20)
774 tfifo_print(dev->name, fec);
775 #endif
776 #if (DEBUG & 0x8)
777 printf( "+" );
778 #endif
779
780 fec->cleanTbdNum -= 1;
781
782 #if (DEBUG & 0x129) && (DEBUG & 0x80000000)
783 printf ("smartDMA ethernet Tx task enabled\n");
784 #endif
785 /*
786 * wait until frame is sent .
787 */
788 while (pTbd->status & FEC_TBD_READY) {
789 udelay(10);
790 #if (DEBUG & 0x8)
791 printf ("TDB status = %04x\n", pTbd->status);
792 #endif
793 }
794
795 return 0;
796 }
797
798
799 /********************************************************************/
800 static int mpc5xxx_fec_recv(struct eth_device *dev)
801 {
802 /*
803 * This command pulls one frame from the card
804 */
805 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
806 volatile FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
807 unsigned long ievent;
808 int frame_length, len = 0;
809 NBUF *frame;
810 uchar buff[FEC_MAX_PKT_SIZE];
811
812 #if (DEBUG & 0x1)
813 printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex);
814 #endif
815 #if (DEBUG & 0x8)
816 printf( "-" );
817 #endif
818
819 /*
820 * Check if any critical events have happened
821 */
822 ievent = fec->eth->ievent;
823 fec->eth->ievent = ievent;
824 if (ievent & 0x20060000) {
825 /* BABT, Rx/Tx FIFO errors */
826 mpc5xxx_fec_halt(dev);
827 mpc5xxx_fec_init(dev, NULL);
828 return 0;
829 }
830 if (ievent & 0x80000000) {
831 /* Heartbeat error */
832 fec->eth->x_cntrl |= 0x00000001;
833 }
834 if (ievent & 0x10000000) {
835 /* Graceful stop complete */
836 if (fec->eth->x_cntrl & 0x00000001) {
837 mpc5xxx_fec_halt(dev);
838 fec->eth->x_cntrl &= ~0x00000001;
839 mpc5xxx_fec_init(dev, NULL);
840 }
841 }
842
843 if (!(pRbd->status & FEC_RBD_EMPTY)) {
844 if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) &&
845 ((pRbd->dataLength - 4) > 14)) {
846
847 /*
848 * Get buffer address and size
849 */
850 frame = (NBUF *)pRbd->dataPointer;
851 frame_length = pRbd->dataLength - 4;
852
853 #if (DEBUG & 0x20)
854 {
855 int i;
856 printf("recv data hdr:");
857 for (i = 0; i < 14; i++)
858 printf("%x ", *(frame->head + i));
859 printf("\n");
860 }
861 #endif
862 /*
863 * Fill the buffer and pass it to upper layers
864 */
865 memcpy(buff, frame->head, 14);
866 memcpy(buff + 14, frame->data, frame_length);
867 NetReceive(buff, frame_length);
868 len = frame_length;
869 }
870 /*
871 * Reset buffer descriptor as empty
872 */
873 mpc5xxx_fec_rbd_clean(fec, pRbd);
874 }
875 SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
876 return len;
877 }
878
879
880 /********************************************************************/
881 int mpc5xxx_fec_initialize(bd_t * bis)
882 {
883 mpc5xxx_fec_priv *fec;
884 struct eth_device *dev;
885 char *tmp, *end;
886 char env_enetaddr[6];
887 int i;
888
889 fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec));
890 dev = (struct eth_device *)malloc(sizeof(*dev));
891 memset(dev, 0, sizeof *dev);
892
893 fec->eth = (ethernet_regs *)MPC5XXX_FEC;
894 fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
895 fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
896 #if defined(CONFIG_MPC5xxx_FEC_MII100)
897 fec->xcv_type = MII100;
898 #elif defined(CONFIG_MPC5xxx_FEC_MII10)
899 fec->xcv_type = MII10;
900 #elif defined(CONFIG_MPC5xxx_FEC_SEVENWIRE)
901 fec->xcv_type = SEVENWIRE;
902 #else
903 #error fec->xcv_type not initialized.
904 #endif
905 if (fec->xcv_type != SEVENWIRE) {
906 /*
907 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
908 * and do not drop the Preamble.
909 * No MII for 7-wire mode
910 */
911 fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1);
912 }
913
914 dev->priv = (void *)fec;
915 dev->iobase = MPC5XXX_FEC;
916 dev->init = mpc5xxx_fec_init;
917 dev->halt = mpc5xxx_fec_halt;
918 dev->send = mpc5xxx_fec_send;
919 dev->recv = mpc5xxx_fec_recv;
920
921 sprintf(dev->name, "FEC");
922 eth_register(dev);
923
924 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
925 miiphy_register (dev->name,
926 fec5xxx_miiphy_read, fec5xxx_miiphy_write);
927 #endif
928
929 /*
930 * Try to set the mac address now. The fec mac address is
931 * a garbage after reset. When not using fec for booting
932 * the Linux fec driver will try to work with this garbage.
933 */
934 tmp = getenv("ethaddr");
935 if (tmp) {
936 for (i=0; i<6; i++) {
937 env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
938 if (tmp)
939 tmp = (*end) ? end+1 : end;
940 }
941 mpc5xxx_fec_set_hwaddr(fec, env_enetaddr);
942 }
943
944 return 1;
945 }
946
947 /* MII-interface related functions */
948 /********************************************************************/
949 int fec5xxx_miiphy_read(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal)
950 {
951 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
952 uint32 reg; /* convenient holder for the PHY register */
953 uint32 phy; /* convenient holder for the PHY */
954 int timeout = 0xffff;
955
956 /*
957 * reading from any PHY's register is done by properly
958 * programming the FEC's MII data register.
959 */
960 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
961 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
962
963 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
964
965 /*
966 * wait for the related interrupt
967 */
968 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
969
970 if (timeout == 0) {
971 #if (DEBUG & 0x2)
972 printf ("Read MDIO failed...\n");
973 #endif
974 return -1;
975 }
976
977 /*
978 * clear mii interrupt bit
979 */
980 eth->ievent = 0x00800000;
981
982 /*
983 * it's now safe to read the PHY's register
984 */
985 *retVal = (uint16) eth->mii_data;
986
987 return 0;
988 }
989
990 /********************************************************************/
991 int fec5xxx_miiphy_write(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 data)
992 {
993 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
994 uint32 reg; /* convenient holder for the PHY register */
995 uint32 phy; /* convenient holder for the PHY */
996 int timeout = 0xffff;
997
998 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
999 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
1000
1001 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
1002 FEC_MII_DATA_TA | phy | reg | data);
1003
1004 /*
1005 * wait for the MII interrupt
1006 */
1007 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
1008
1009 if (timeout == 0) {
1010 #if (DEBUG & 0x2)
1011 printf ("Write MDIO failed...\n");
1012 #endif
1013 return -1;
1014 }
1015
1016 /*
1017 * clear MII interrupt bit
1018 */
1019 eth->ievent = 0x00800000;
1020
1021 return 0;
1022 }
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