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Merge branch 'master' of git://git.denx.de/u-boot-sh
[people/ms/u-boot.git] / drivers / net / mpc5xxx_fec.c
1 /*
2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * This file is based on mpc4200fec.c,
6 * (C) Copyright Motorola, Inc., 2000
7 */
8
9 #include <common.h>
10 #include <mpc5xxx.h>
11 #include <mpc5xxx_sdma.h>
12 #include <malloc.h>
13 #include <net.h>
14 #include <netdev.h>
15 #include <miiphy.h>
16 #include "mpc5xxx_fec.h"
17
18 DECLARE_GLOBAL_DATA_PTR;
19
20 /* #define DEBUG 0x28 */
21
22 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
23 #error "CONFIG_MII has to be defined!"
24 #endif
25
26 #if (DEBUG & 0x60)
27 static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec);
28 static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec);
29 #endif /* DEBUG */
30
31 #if (DEBUG & 0x40)
32 static uint32 local_crc32(char *string, unsigned int crc_value, int len);
33 #endif
34
35 typedef struct {
36 uint8 data[1500]; /* actual data */
37 int length; /* actual length */
38 int used; /* buffer in use or not */
39 uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
40 } NBUF;
41
42 int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal);
43 int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
44
45 /********************************************************************/
46 #if (DEBUG & 0x2)
47 static void mpc5xxx_fec_phydump (char *devname)
48 {
49 uint16 phyStatus, i;
50 uint8 phyAddr = CONFIG_PHY_ADDR;
51 uint8 reg_mask[] = {
52 #if CONFIG_PHY_TYPE == 0x79c874 /* AMD Am79C874 */
53 /* regs to print: 0...7, 16...19, 21, 23, 24 */
54 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
55 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0,
56 #else
57 /* regs to print: 0...8, 16...20 */
58 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
59 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
60 #endif
61 };
62
63 for (i = 0; i < 32; i++) {
64 if (reg_mask[i]) {
65 miiphy_read(devname, phyAddr, i, &phyStatus);
66 printf("Mii reg %d: 0x%04x\n", i, phyStatus);
67 }
68 }
69 }
70 #endif
71
72 /********************************************************************/
73 static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec)
74 {
75 int ix;
76 char *data;
77 static int once = 0;
78
79 for (ix = 0; ix < FEC_RBD_NUM; ix++) {
80 if (!once) {
81 data = (char *)malloc(FEC_MAX_PKT_SIZE);
82 if (data == NULL) {
83 printf ("RBD INIT FAILED\n");
84 return -1;
85 }
86 fec->rbdBase[ix].dataPointer = (uint32)data;
87 }
88 fec->rbdBase[ix].status = FEC_RBD_EMPTY;
89 fec->rbdBase[ix].dataLength = 0;
90 }
91 once ++;
92
93 /*
94 * have the last RBD to close the ring
95 */
96 fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP;
97 fec->rbdIndex = 0;
98
99 return 0;
100 }
101
102 /********************************************************************/
103 static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec)
104 {
105 int ix;
106
107 for (ix = 0; ix < FEC_TBD_NUM; ix++) {
108 fec->tbdBase[ix].status = 0;
109 }
110
111 /*
112 * Have the last TBD to close the ring
113 */
114 fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP;
115
116 /*
117 * Initialize some indices
118 */
119 fec->tbdIndex = 0;
120 fec->usedTbdIndex = 0;
121 fec->cleanTbdNum = FEC_TBD_NUM;
122 }
123
124 /********************************************************************/
125 static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, volatile FEC_RBD * pRbd)
126 {
127 /*
128 * Reset buffer descriptor as empty
129 */
130 if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
131 pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
132 else
133 pRbd->status = FEC_RBD_EMPTY;
134
135 pRbd->dataLength = 0;
136
137 /*
138 * Now, we have an empty RxBD, restart the SmartDMA receive task
139 */
140 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
141
142 /*
143 * Increment BD count
144 */
145 fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
146 }
147
148 /********************************************************************/
149 static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec)
150 {
151 volatile FEC_TBD *pUsedTbd;
152
153 #if (DEBUG & 0x1)
154 printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
155 fec->cleanTbdNum, fec->usedTbdIndex);
156 #endif
157
158 /*
159 * process all the consumed TBDs
160 */
161 while (fec->cleanTbdNum < FEC_TBD_NUM) {
162 pUsedTbd = &fec->tbdBase[fec->usedTbdIndex];
163 if (pUsedTbd->status & FEC_TBD_READY) {
164 #if (DEBUG & 0x20)
165 printf("Cannot clean TBD %d, in use\n", fec->cleanTbdNum);
166 #endif
167 return;
168 }
169
170 /*
171 * clean this buffer descriptor
172 */
173 if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
174 pUsedTbd->status = FEC_TBD_WRAP;
175 else
176 pUsedTbd->status = 0;
177
178 /*
179 * update some indeces for a correct handling of the TBD ring
180 */
181 fec->cleanTbdNum++;
182 fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
183 }
184 }
185
186 /********************************************************************/
187 static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac)
188 {
189 uint8 currByte; /* byte for which to compute the CRC */
190 int byte; /* loop - counter */
191 int bit; /* loop - counter */
192 uint32 crc = 0xffffffff; /* initial value */
193
194 /*
195 * The algorithm used is the following:
196 * we loop on each of the six bytes of the provided address,
197 * and we compute the CRC by left-shifting the previous
198 * value by one position, so that each bit in the current
199 * byte of the address may contribute the calculation. If
200 * the latter and the MSB in the CRC are different, then
201 * the CRC value so computed is also ex-ored with the
202 * "polynomium generator". The current byte of the address
203 * is also shifted right by one bit at each iteration.
204 * This is because the CRC generatore in hardware is implemented
205 * as a shift-register with as many ex-ores as the radixes
206 * in the polynomium. This suggests that we represent the
207 * polynomiumm itself as a 32-bit constant.
208 */
209 for (byte = 0; byte < 6; byte++) {
210 currByte = mac[byte];
211 for (bit = 0; bit < 8; bit++) {
212 if ((currByte & 0x01) ^ (crc & 0x01)) {
213 crc >>= 1;
214 crc = crc ^ 0xedb88320;
215 } else {
216 crc >>= 1;
217 }
218 currByte >>= 1;
219 }
220 }
221
222 crc = crc >> 26;
223
224 /*
225 * Set individual hash table register
226 */
227 if (crc >= 32) {
228 fec->eth->iaddr1 = (1 << (crc - 32));
229 fec->eth->iaddr2 = 0;
230 } else {
231 fec->eth->iaddr1 = 0;
232 fec->eth->iaddr2 = (1 << crc);
233 }
234
235 /*
236 * Set physical address
237 */
238 fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
239 fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
240 }
241
242 /********************************************************************/
243 static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
244 {
245 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
246 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
247
248 #if (DEBUG & 0x1)
249 printf ("mpc5xxx_fec_init... Begin\n");
250 #endif
251
252 /*
253 * Initialize RxBD/TxBD rings
254 */
255 mpc5xxx_fec_rbd_init(fec);
256 mpc5xxx_fec_tbd_init(fec);
257
258 /*
259 * Clear FEC-Lite interrupt event register(IEVENT)
260 */
261 fec->eth->ievent = 0xffffffff;
262
263 /*
264 * Set interrupt mask register
265 */
266 fec->eth->imask = 0x00000000;
267
268 /*
269 * Set FEC-Lite receive control register(R_CNTRL):
270 */
271 if (fec->xcv_type == SEVENWIRE) {
272 /*
273 * Frame length=1518; 7-wire mode
274 */
275 fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */
276 } else {
277 /*
278 * Frame length=1518; MII mode;
279 */
280 fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */
281 }
282
283 fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */
284
285 /*
286 * Set Opcode/Pause Duration Register
287 */
288 fec->eth->op_pause = 0x00010020; /*FIXME 0xffff0020; */
289
290 /*
291 * Set Rx FIFO alarm and granularity value
292 */
293 fec->eth->rfifo_cntrl = 0x0c000000
294 | (fec->eth->rfifo_cntrl & ~0x0f000000);
295 fec->eth->rfifo_alarm = 0x0000030c;
296 #if (DEBUG & 0x22)
297 if (fec->eth->rfifo_status & 0x00700000 ) {
298 printf("mpc5xxx_fec_init() RFIFO error\n");
299 }
300 #endif
301
302 /*
303 * Set Tx FIFO granularity value
304 */
305 fec->eth->tfifo_cntrl = 0x0c000000
306 | (fec->eth->tfifo_cntrl & ~0x0f000000);
307 #if (DEBUG & 0x2)
308 printf("tfifo_status: 0x%08x\n", fec->eth->tfifo_status);
309 printf("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm);
310 #endif
311
312 /*
313 * Set transmit fifo watermark register(X_WMRK), default = 64
314 */
315 fec->eth->tfifo_alarm = 0x00000080;
316 fec->eth->x_wmrk = 0x2;
317
318 /*
319 * Set individual address filter for unicast address
320 * and set physical address registers.
321 */
322 mpc5xxx_fec_set_hwaddr(fec, (char *)dev->enetaddr);
323
324 /*
325 * Set multicast address filter
326 */
327 fec->eth->gaddr1 = 0x00000000;
328 fec->eth->gaddr2 = 0x00000000;
329
330 /*
331 * Turn ON cheater FSM: ????
332 */
333 fec->eth->xmit_fsm = 0x03000000;
334
335 #if defined(CONFIG_MPC5200)
336 /*
337 * Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't
338 * work w/ the current receive task.
339 */
340 sdma->PtdCntrl |= 0x00000001;
341 #endif
342
343 /*
344 * Set priority of different initiators
345 */
346 sdma->IPR0 = 7; /* always */
347 sdma->IPR3 = 6; /* Eth RX */
348 sdma->IPR4 = 5; /* Eth Tx */
349
350 /*
351 * Clear SmartDMA task interrupt pending bits
352 */
353 SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO);
354
355 /*
356 * Initialize SmartDMA parameters stored in SRAM
357 */
358 *(volatile int *)FEC_TBD_BASE = (int)fec->tbdBase;
359 *(volatile int *)FEC_RBD_BASE = (int)fec->rbdBase;
360 *(volatile int *)FEC_TBD_NEXT = (int)fec->tbdBase;
361 *(volatile int *)FEC_RBD_NEXT = (int)fec->rbdBase;
362
363 /*
364 * Enable FEC-Lite controller
365 */
366 fec->eth->ecntrl |= 0x00000006;
367
368 #if (DEBUG & 0x2)
369 if (fec->xcv_type != SEVENWIRE)
370 mpc5xxx_fec_phydump (dev->name);
371 #endif
372
373 /*
374 * Enable SmartDMA receive task
375 */
376 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
377
378 #if (DEBUG & 0x1)
379 printf("mpc5xxx_fec_init... Done \n");
380 #endif
381
382 return 1;
383 }
384
385 /********************************************************************/
386 static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
387 {
388 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
389 const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
390
391 #if (DEBUG & 0x1)
392 printf ("mpc5xxx_fec_init_phy... Begin\n");
393 #endif
394
395 /*
396 * Initialize GPIO pins
397 */
398 if (fec->xcv_type == SEVENWIRE) {
399 /* 10MBit with 7-wire operation */
400 #if defined(CONFIG_TOTAL5200)
401 /* 7-wire and USB2 on Ethernet */
402 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00030000;
403 #else /* !CONFIG_TOTAL5200 */
404 /* 7-wire only */
405 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000;
406 #endif /* CONFIG_TOTAL5200 */
407 } else {
408 /* 100MBit with MD operation */
409 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000;
410 }
411
412 /*
413 * Clear FEC-Lite interrupt event register(IEVENT)
414 */
415 fec->eth->ievent = 0xffffffff;
416
417 /*
418 * Set interrupt mask register
419 */
420 fec->eth->imask = 0x00000000;
421
422 /*
423 * In original Promess-provided code PHY initialization is disabled with the
424 * following comment: "Phy initialization is DISABLED for now. There was a
425 * problem with running 100 Mbps on PRO board". Thus we temporarily disable
426 * PHY initialization for the Motion-PRO board, until a proper fix is found.
427 */
428
429 if (fec->xcv_type != SEVENWIRE) {
430 /*
431 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
432 * and do not drop the Preamble.
433 */
434 fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
435 }
436
437 if (fec->xcv_type != SEVENWIRE) {
438 /*
439 * Initialize PHY(LXT971A):
440 *
441 * Generally, on power up, the LXT971A reads its configuration
442 * pins to check for forced operation, If not cofigured for
443 * forced operation, it uses auto-negotiation/parallel detection
444 * to automatically determine line operating conditions.
445 * If the PHY device on the other side of the link supports
446 * auto-negotiation, the LXT971A auto-negotiates with it
447 * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not
448 * support auto-negotiation, the LXT971A automatically detects
449 * the presence of either link pulses(10Mbps PHY) or Idle
450 * symbols(100Mbps) and sets its operating conditions accordingly.
451 *
452 * When auto-negotiation is controlled by software, the following
453 * steps are recommended.
454 *
455 * Note:
456 * The physical address is dependent on hardware configuration.
457 *
458 */
459 int timeout = 1;
460 uint16 phyStatus;
461
462 /*
463 * Reset PHY, then delay 300ns
464 */
465 miiphy_write(dev->name, phyAddr, 0x0, 0x8000);
466 udelay(1000);
467
468 #if defined(CONFIG_UC101) || defined(CONFIG_MUCMC52)
469 /* Set the LED configuration Register for the UC101
470 and MUCMC52 Board */
471 miiphy_write(dev->name, phyAddr, 0x14, 0x4122);
472 #endif
473 if (fec->xcv_type == MII10) {
474 /*
475 * Force 10Base-T, FDX operation
476 */
477 #if (DEBUG & 0x2)
478 printf("Forcing 10 Mbps ethernet link... ");
479 #endif
480 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
481 /*
482 miiphy_write(dev->name, fec, phyAddr, 0x0, 0x0100);
483 */
484 miiphy_write(dev->name, phyAddr, 0x0, 0x0180);
485
486 timeout = 20;
487 do { /* wait for link status to go down */
488 udelay(10000);
489 if ((timeout--) == 0) {
490 #if (DEBUG & 0x2)
491 printf("hmmm, should not have waited...");
492 #endif
493 break;
494 }
495 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
496 #if (DEBUG & 0x2)
497 printf("=");
498 #endif
499 } while ((phyStatus & 0x0004)); /* !link up */
500
501 timeout = 1000;
502 do { /* wait for link status to come back up */
503 udelay(10000);
504 if ((timeout--) == 0) {
505 printf("failed. Link is down.\n");
506 break;
507 }
508 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
509 #if (DEBUG & 0x2)
510 printf("+");
511 #endif
512 } while (!(phyStatus & 0x0004)); /* !link up */
513
514 #if (DEBUG & 0x2)
515 printf ("done.\n");
516 #endif
517 } else { /* MII100 */
518 /*
519 * Set the auto-negotiation advertisement register bits
520 */
521 miiphy_write(dev->name, phyAddr, 0x4, 0x01e1);
522
523 /*
524 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
525 */
526 miiphy_write(dev->name, phyAddr, 0x0, 0x1200);
527
528 /*
529 * Wait for AN completion
530 */
531 timeout = 5000;
532 do {
533 udelay(1000);
534
535 if ((timeout--) == 0) {
536 #if (DEBUG & 0x2)
537 printf("PHY auto neg 0 failed...\n");
538 #endif
539 return -1;
540 }
541
542 if (miiphy_read(dev->name, phyAddr, 0x1, &phyStatus) != 0) {
543 #if (DEBUG & 0x2)
544 printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
545 #endif
546 return -1;
547 }
548 } while (!(phyStatus & 0x0004));
549
550 #if (DEBUG & 0x2)
551 printf("PHY auto neg complete! \n");
552 #endif
553 }
554
555 }
556
557 #if (DEBUG & 0x2)
558 if (fec->xcv_type != SEVENWIRE)
559 mpc5xxx_fec_phydump (dev->name);
560 #endif
561
562
563 #if (DEBUG & 0x1)
564 printf("mpc5xxx_fec_init_phy... Done \n");
565 #endif
566
567 return 1;
568 }
569
570 /********************************************************************/
571 static void mpc5xxx_fec_halt(struct eth_device *dev)
572 {
573 #if defined(CONFIG_MPC5200)
574 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
575 #endif
576 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
577 int counter = 0xffff;
578
579 #if (DEBUG & 0x2)
580 if (fec->xcv_type != SEVENWIRE)
581 mpc5xxx_fec_phydump (dev->name);
582 #endif
583
584 /*
585 * mask FEC chip interrupts
586 */
587 fec->eth->imask = 0;
588
589 /*
590 * issue graceful stop command to the FEC transmitter if necessary
591 */
592 fec->eth->x_cntrl |= 0x00000001;
593
594 /*
595 * wait for graceful stop to register
596 */
597 while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;
598
599 /*
600 * Disable SmartDMA tasks
601 */
602 SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
603 SDMA_TASK_DISABLE (FEC_RECV_TASK_NO);
604
605 #if defined(CONFIG_MPC5200)
606 /*
607 * Turn on COMM bus prefetch in the MGT5200 BestComm after we're
608 * done. It doesn't work w/ the current receive task.
609 */
610 sdma->PtdCntrl &= ~0x00000001;
611 #endif
612
613 /*
614 * Disable the Ethernet Controller
615 */
616 fec->eth->ecntrl &= 0xfffffffd;
617
618 /*
619 * Clear FIFO status registers
620 */
621 fec->eth->rfifo_status &= 0x00700000;
622 fec->eth->tfifo_status &= 0x00700000;
623
624 fec->eth->reset_cntrl = 0x01000000;
625
626 /*
627 * Issue a reset command to the FEC chip
628 */
629 fec->eth->ecntrl |= 0x1;
630
631 /*
632 * wait at least 16 clock cycles
633 */
634 udelay(10);
635
636 /* don't leave the MII speed set to zero */
637 if (fec->xcv_type != SEVENWIRE) {
638 /*
639 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
640 * and do not drop the Preamble.
641 */
642 fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
643 }
644
645 #if (DEBUG & 0x3)
646 printf("Ethernet task stopped\n");
647 #endif
648 }
649
650 #if (DEBUG & 0x60)
651 /********************************************************************/
652
653 static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec)
654 {
655 uint16 phyAddr = CONFIG_PHY_ADDR;
656 uint16 phyStatus;
657
658 if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
659 || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
660
661 miiphy_read(devname, phyAddr, 0x1, &phyStatus);
662 printf("\nphyStatus: 0x%04x\n", phyStatus);
663 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
664 printf("ievent: 0x%08x\n", fec->eth->ievent);
665 printf("x_status: 0x%08x\n", fec->eth->x_status);
666 printf("tfifo: status 0x%08x\n", fec->eth->tfifo_status);
667
668 printf(" control 0x%08x\n", fec->eth->tfifo_cntrl);
669 printf(" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr);
670 printf(" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr);
671 printf(" alarm 0x%08x\n", fec->eth->tfifo_alarm);
672 printf(" readptr 0x%08x\n", fec->eth->tfifo_rdptr);
673 printf(" writptr 0x%08x\n", fec->eth->tfifo_wrptr);
674 }
675 }
676
677 static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec)
678 {
679 uint16 phyAddr = CONFIG_PHY_ADDR;
680 uint16 phyStatus;
681
682 if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
683 || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
684
685 miiphy_read(devname, phyAddr, 0x1, &phyStatus);
686 printf("\nphyStatus: 0x%04x\n", phyStatus);
687 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
688 printf("ievent: 0x%08x\n", fec->eth->ievent);
689 printf("x_status: 0x%08x\n", fec->eth->x_status);
690 printf("rfifo: status 0x%08x\n", fec->eth->rfifo_status);
691
692 printf(" control 0x%08x\n", fec->eth->rfifo_cntrl);
693 printf(" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr);
694 printf(" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr);
695 printf(" alarm 0x%08x\n", fec->eth->rfifo_alarm);
696 printf(" readptr 0x%08x\n", fec->eth->rfifo_rdptr);
697 printf(" writptr 0x%08x\n", fec->eth->rfifo_wrptr);
698 }
699 }
700 #endif /* DEBUG */
701
702 /********************************************************************/
703
704 static int mpc5xxx_fec_send(struct eth_device *dev, volatile void *eth_data,
705 int data_length)
706 {
707 /*
708 * This routine transmits one frame. This routine only accepts
709 * 6-byte Ethernet addresses.
710 */
711 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
712 volatile FEC_TBD *pTbd;
713
714 #if (DEBUG & 0x20)
715 printf("tbd status: 0x%04x\n", fec->tbdBase[0].status);
716 tfifo_print(dev->name, fec);
717 #endif
718
719 /*
720 * Clear Tx BD ring at first
721 */
722 mpc5xxx_fec_tbd_scrub(fec);
723
724 /*
725 * Check for valid length of data.
726 */
727 if ((data_length > 1500) || (data_length <= 0)) {
728 return -1;
729 }
730
731 /*
732 * Check the number of vacant TxBDs.
733 */
734 if (fec->cleanTbdNum < 1) {
735 #if (DEBUG & 0x20)
736 printf("No available TxBDs ...\n");
737 #endif
738 return -1;
739 }
740
741 /*
742 * Get the first TxBD to send the mac header
743 */
744 pTbd = &fec->tbdBase[fec->tbdIndex];
745 pTbd->dataLength = data_length;
746 pTbd->dataPointer = (uint32)eth_data;
747 pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
748 fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
749
750 #if (DEBUG & 0x100)
751 printf("SDMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex);
752 #endif
753
754 /*
755 * Kick the MII i/f
756 */
757 if (fec->xcv_type != SEVENWIRE) {
758 uint16 phyStatus;
759 miiphy_read(dev->name, 0, 0x1, &phyStatus);
760 }
761
762 /*
763 * Enable SmartDMA transmit task
764 */
765
766 #if (DEBUG & 0x20)
767 tfifo_print(dev->name, fec);
768 #endif
769 SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
770 #if (DEBUG & 0x20)
771 tfifo_print(dev->name, fec);
772 #endif
773 #if (DEBUG & 0x8)
774 printf( "+" );
775 #endif
776
777 fec->cleanTbdNum -= 1;
778
779 #if (DEBUG & 0x129) && (DEBUG & 0x80000000)
780 printf ("smartDMA ethernet Tx task enabled\n");
781 #endif
782 /*
783 * wait until frame is sent .
784 */
785 while (pTbd->status & FEC_TBD_READY) {
786 udelay(10);
787 #if (DEBUG & 0x8)
788 printf ("TDB status = %04x\n", pTbd->status);
789 #endif
790 }
791
792 return 0;
793 }
794
795
796 /********************************************************************/
797 static int mpc5xxx_fec_recv(struct eth_device *dev)
798 {
799 /*
800 * This command pulls one frame from the card
801 */
802 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
803 volatile FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
804 unsigned long ievent;
805 int frame_length, len = 0;
806 NBUF *frame;
807 uchar buff[FEC_MAX_PKT_SIZE];
808
809 #if (DEBUG & 0x1)
810 printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex);
811 #endif
812 #if (DEBUG & 0x8)
813 printf( "-" );
814 #endif
815
816 /*
817 * Check if any critical events have happened
818 */
819 ievent = fec->eth->ievent;
820 fec->eth->ievent = ievent;
821 if (ievent & 0x20060000) {
822 /* BABT, Rx/Tx FIFO errors */
823 mpc5xxx_fec_halt(dev);
824 mpc5xxx_fec_init(dev, NULL);
825 return 0;
826 }
827 if (ievent & 0x80000000) {
828 /* Heartbeat error */
829 fec->eth->x_cntrl |= 0x00000001;
830 }
831 if (ievent & 0x10000000) {
832 /* Graceful stop complete */
833 if (fec->eth->x_cntrl & 0x00000001) {
834 mpc5xxx_fec_halt(dev);
835 fec->eth->x_cntrl &= ~0x00000001;
836 mpc5xxx_fec_init(dev, NULL);
837 }
838 }
839
840 if (!(pRbd->status & FEC_RBD_EMPTY)) {
841 if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) &&
842 ((pRbd->dataLength - 4) > 14)) {
843
844 /*
845 * Get buffer address and size
846 */
847 frame = (NBUF *)pRbd->dataPointer;
848 frame_length = pRbd->dataLength - 4;
849
850 #if (DEBUG & 0x20)
851 {
852 int i;
853 printf("recv data hdr:");
854 for (i = 0; i < 14; i++)
855 printf("%x ", *(frame->head + i));
856 printf("\n");
857 }
858 #endif
859 /*
860 * Fill the buffer and pass it to upper layers
861 */
862 memcpy(buff, frame->head, 14);
863 memcpy(buff + 14, frame->data, frame_length);
864 NetReceive(buff, frame_length);
865 len = frame_length;
866 }
867 /*
868 * Reset buffer descriptor as empty
869 */
870 mpc5xxx_fec_rbd_clean(fec, pRbd);
871 }
872 SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
873 return len;
874 }
875
876
877 /********************************************************************/
878 int mpc5xxx_fec_initialize(bd_t * bis)
879 {
880 mpc5xxx_fec_priv *fec;
881 struct eth_device *dev;
882 char *tmp, *end;
883 char env_enetaddr[6];
884 int i;
885
886 fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec));
887 dev = (struct eth_device *)malloc(sizeof(*dev));
888 memset(dev, 0, sizeof *dev);
889
890 fec->eth = (ethernet_regs *)MPC5XXX_FEC;
891 fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
892 fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
893 #if defined(CONFIG_MPC5xxx_FEC_MII100)
894 fec->xcv_type = MII100;
895 #elif defined(CONFIG_MPC5xxx_FEC_MII10)
896 fec->xcv_type = MII10;
897 #elif defined(CONFIG_MPC5xxx_FEC_SEVENWIRE)
898 fec->xcv_type = SEVENWIRE;
899 #else
900 #error fec->xcv_type not initialized.
901 #endif
902 if (fec->xcv_type != SEVENWIRE) {
903 /*
904 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
905 * and do not drop the Preamble.
906 */
907 fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
908 }
909
910 dev->priv = (void *)fec;
911 dev->iobase = MPC5XXX_FEC;
912 dev->init = mpc5xxx_fec_init;
913 dev->halt = mpc5xxx_fec_halt;
914 dev->send = mpc5xxx_fec_send;
915 dev->recv = mpc5xxx_fec_recv;
916
917 sprintf(dev->name, "FEC ETHERNET");
918 eth_register(dev);
919
920 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
921 miiphy_register (dev->name,
922 fec5xxx_miiphy_read, fec5xxx_miiphy_write);
923 #endif
924
925 /*
926 * Try to set the mac address now. The fec mac address is
927 * a garbage after reset. When not using fec for booting
928 * the Linux fec driver will try to work with this garbage.
929 */
930 tmp = getenv("ethaddr");
931 if (tmp) {
932 for (i=0; i<6; i++) {
933 env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
934 if (tmp)
935 tmp = (*end) ? end+1 : end;
936 }
937 mpc5xxx_fec_set_hwaddr(fec, env_enetaddr);
938 }
939
940 mpc5xxx_fec_init_phy(dev, bis);
941
942 return 1;
943 }
944
945 /* MII-interface related functions */
946 /********************************************************************/
947 int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal)
948 {
949 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
950 uint32 reg; /* convenient holder for the PHY register */
951 uint32 phy; /* convenient holder for the PHY */
952 int timeout = 0xffff;
953
954 /*
955 * reading from any PHY's register is done by properly
956 * programming the FEC's MII data register.
957 */
958 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
959 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
960
961 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
962
963 /*
964 * wait for the related interrupt
965 */
966 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
967
968 if (timeout == 0) {
969 #if (DEBUG & 0x2)
970 printf ("Read MDIO failed...\n");
971 #endif
972 return -1;
973 }
974
975 /*
976 * clear mii interrupt bit
977 */
978 eth->ievent = 0x00800000;
979
980 /*
981 * it's now safe to read the PHY's register
982 */
983 *retVal = (uint16) eth->mii_data;
984
985 return 0;
986 }
987
988 /********************************************************************/
989 int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data)
990 {
991 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
992 uint32 reg; /* convenient holder for the PHY register */
993 uint32 phy; /* convenient holder for the PHY */
994 int timeout = 0xffff;
995
996 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
997 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
998
999 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
1000 FEC_MII_DATA_TA | phy | reg | data);
1001
1002 /*
1003 * wait for the MII interrupt
1004 */
1005 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
1006
1007 if (timeout == 0) {
1008 #if (DEBUG & 0x2)
1009 printf ("Write MDIO failed...\n");
1010 #endif
1011 return -1;
1012 }
1013
1014 /*
1015 * clear MII interrupt bit
1016 */
1017 eth->ievent = 0x00800000;
1018
1019 return 0;
1020 }
1021
1022 #if (DEBUG & 0x40)
1023 static uint32 local_crc32(char *string, unsigned int crc_value, int len)
1024 {
1025 int i;
1026 char c;
1027 unsigned int crc, count;
1028
1029 /*
1030 * crc32 algorithm
1031 */
1032 /*
1033 * crc = 0xffffffff; * The initialized value should be 0xffffffff
1034 */
1035 crc = crc_value;
1036
1037 for (i = len; --i >= 0;) {
1038 c = *string++;
1039 for (count = 0; count < 8; count++) {
1040 if ((c & 0x01) ^ (crc & 0x01)) {
1041 crc >>= 1;
1042 crc = crc ^ 0xedb88320;
1043 } else {
1044 crc >>= 1;
1045 }
1046 c >>= 1;
1047 }
1048 }
1049
1050 /*
1051 * In big endian system, do byte swaping for crc value
1052 */
1053 /**/ return crc;
1054 }
1055 #endif /* DEBUG */
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