drivers/net/mtk_eth.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 2018 MediaTek Inc.
   4  *
   5  * Author: Weijie Gao <weijie.gao@mediatek.com>
   6  * Author: Mark Lee <mark-mc.lee@mediatek.com>
   7  */
   8
   9 #ifndef _MTK_ETH_H_
  10 #define _MTK_ETH_H_
  11
  12 /* Frame Engine Register Bases */
  13 #define PDMA_BASE                       0x0800
  14 #define GDMA1_BASE                      0x0500
  15 #define GDMA2_BASE                      0x1500
  16 #define GMAC_BASE                       0x10000
  17
  18 /* Ethernet subsystem registers */
  19
  20 #define ETHSYS_SYSCFG0_REG              0x14
  21 #define SYSCFG0_GE_MODE_S(n)            (12 + ((n) * 2))
  22 #define SYSCFG0_GE_MODE_M               0x3
  23
  24 #define ETHSYS_CLKCFG0_REG              0x2c
  25 #define ETHSYS_TRGMII_CLK_SEL362_5      BIT(11)
  26
  27 /* SYSCFG0_GE_MODE: GE Modes */
  28 #define GE_MODE_RGMII                   0
  29 #define GE_MODE_MII                     1
  30 #define GE_MODE_MII_PHY                 2
  31 #define GE_MODE_RMII                    3
  32
  33 /* Frame Engine Registers */
  34
  35 /* PDMA */
  36 #define TX_BASE_PTR_REG(n)              (0x000 + (n) * 0x10)
  37 #define TX_MAX_CNT_REG(n)               (0x004 + (n) * 0x10)
  38 #define TX_CTX_IDX_REG(n)               (0x008 + (n) * 0x10)
  39 #define TX_DTX_IDX_REG(n)               (0x00c + (n) * 0x10)
  40
  41 #define RX_BASE_PTR_REG(n)              (0x100 + (n) * 0x10)
  42 #define RX_MAX_CNT_REG(n)               (0x104 + (n) * 0x10)
  43 #define RX_CRX_IDX_REG(n)               (0x108 + (n) * 0x10)
  44 #define RX_DRX_IDX_REG(n)               (0x10c + (n) * 0x10)
  45
  46 #define PDMA_GLO_CFG_REG                0x204
  47 #define TX_WB_DDONE                     BIT(6)
  48 #define RX_DMA_BUSY                     BIT(3)
  49 #define RX_DMA_EN                       BIT(2)
  50 #define TX_DMA_BUSY                     BIT(1)
  51 #define TX_DMA_EN                       BIT(0)
  52
  53 #define PDMA_RST_IDX_REG                0x208
  54 #define RST_DRX_IDX0                    BIT(16)
  55 #define RST_DTX_IDX0                    BIT(0)
  56
  57 /* GDMA */
  58 #define GDMA_IG_CTRL_REG                0x000
  59 #define GDM_ICS_EN                      BIT(22)
  60 #define GDM_TCS_EN                      BIT(21)
  61 #define GDM_UCS_EN                      BIT(20)
  62 #define STRP_CRC                        BIT(16)
  63 #define MYMAC_DP_S                      12
  64 #define MYMAC_DP_M                      0xf000
  65 #define BC_DP_S                         8
  66 #define BC_DP_M                         0xf00
  67 #define MC_DP_S                         4
  68 #define MC_DP_M                         0xf0
  69 #define UN_DP_S                         0
  70 #define UN_DP_M                         0x0f
  71
  72 #define GDMA_MAC_LSB_REG                0x008
  73
  74 #define GDMA_MAC_MSB_REG                0x00c
  75
  76 /* MYMAC_DP/BC_DP/MC_DP/UN_DP: Destination ports */
  77 #define DP_PDMA                         0
  78 #define DP_GDMA1                        1
  79 #define DP_GDMA2                        2
  80 #define DP_PPE                          4
  81 #define DP_QDMA                         5
  82 #define DP_DISCARD                      7
  83
  84 /* GMAC Registers */
  85
  86 #define GMAC_PIAC_REG                   0x0004
  87 #define PHY_ACS_ST                      BIT(31)
  88 #define MDIO_REG_ADDR_S                 25
  89 #define MDIO_REG_ADDR_M                 0x3e000000
  90 #define MDIO_PHY_ADDR_S                 20
  91 #define MDIO_PHY_ADDR_M                 0x1f00000
  92 #define MDIO_CMD_S                      18
  93 #define MDIO_CMD_M                      0xc0000
  94 #define MDIO_ST_S                       16
  95 #define MDIO_ST_M                       0x30000
  96 #define MDIO_RW_DATA_S                  0
  97 #define MDIO_RW_DATA_M                  0xffff
  98
  99 /* MDIO_CMD: MDIO commands */
 100 #define MDIO_CMD_ADDR                   0
 101 #define MDIO_CMD_WRITE                  1
 102 #define MDIO_CMD_READ                   2
 103 #define MDIO_CMD_READ_C45               3
 104
 105 /* MDIO_ST: MDIO start field */
 106 #define MDIO_ST_C45                     0
 107 #define MDIO_ST_C22                     1
 108
 109 #define GMAC_PORT_MCR(p)                (0x0100 + (p) * 0x100)
 110 #define MAC_RX_PKT_LEN_S                24
 111 #define MAC_RX_PKT_LEN_M                0x3000000
 112 #define IPG_CFG_S                       18
 113 #define IPG_CFG_M                       0xc0000
 114 #define MAC_MODE                        BIT(16)
 115 #define FORCE_MODE                      BIT(15)
 116 #define MAC_TX_EN                       BIT(14)
 117 #define MAC_RX_EN                       BIT(13)
 118 #define BKOFF_EN                        BIT(9)
 119 #define BACKPR_EN                       BIT(8)
 120 #define FORCE_RX_FC                     BIT(5)
 121 #define FORCE_TX_FC                     BIT(4)
 122 #define FORCE_SPD_S                     2
 123 #define FORCE_SPD_M                     0x0c
 124 #define FORCE_DPX                       BIT(1)
 125 #define FORCE_LINK                      BIT(0)
 126
 127 /* MAC_RX_PKT_LEN: Max RX packet length */
 128 #define MAC_RX_PKT_LEN_1518             0
 129 #define MAC_RX_PKT_LEN_1536             1
 130 #define MAC_RX_PKT_LEN_1552             2
 131 #define MAC_RX_PKT_LEN_JUMBO            3
 132
 133 /* FORCE_SPD: Forced link speed */
 134 #define SPEED_10M                       0
 135 #define SPEED_100M                      1
 136 #define SPEED_1000M                     2
 137
 138 #define GMAC_TRGMII_RCK_CTRL            0x300
 139 #define RX_RST                          BIT(31)
 140 #define RXC_DQSISEL                     BIT(30)
 141
 142 #define GMAC_TRGMII_TD_ODT(n)           (0x354 + (n) * 8)
 143 #define TD_DM_DRVN_S                    4
 144 #define TD_DM_DRVN_M                    0xf0
 145 #define TD_DM_DRVP_S                    0
 146 #define TD_DM_DRVP_M                    0x0f
 147
 148 /* MT7530 Registers */
 149
 150 #define PCR_REG(p)                      (0x2004 + (p) * 0x100)
 151 #define PORT_MATRIX_S                   16
 152 #define PORT_MATRIX_M                   0xff0000
 153
 154 #define PVC_REG(p)                      (0x2010 + (p) * 0x100)
 155 #define STAG_VPID_S                     16
 156 #define STAG_VPID_M                     0xffff0000
 157 #define VLAN_ATTR_S                     6
 158 #define VLAN_ATTR_M                     0xc0
 159
 160 /* VLAN_ATTR: VLAN attributes */
 161 #define VLAN_ATTR_USER                  0
 162 #define VLAN_ATTR_STACK                 1
 163 #define VLAN_ATTR_TRANSLATION           2
 164 #define VLAN_ATTR_TRANSPARENT           3
 165
 166 #define PCMR_REG(p)                     (0x3000 + (p) * 0x100)
 167 /* XXX: all fields are defined under GMAC_PORT_MCR */
 168
 169 #define SYS_CTRL_REG                    0x7000
 170 #define SW_PHY_RST                      BIT(2)
 171 #define SW_SYS_RST                      BIT(1)
 172 #define SW_REG_RST                      BIT(0)
 173
 174 #define NUM_TRGMII_CTRL                 5
 175
 176 #define HWTRAP_REG                      0x7800
 177 #define MHWTRAP_REG                     0x7804
 178 #define CHG_TRAP                        BIT(16)
 179 #define LOOPDET_DIS                     BIT(14)
 180 #define P5_INTF_SEL_S                   13
 181 #define P5_INTF_SEL_M                   0x2000
 182 #define SMI_ADDR_S                      11
 183 #define SMI_ADDR_M                      0x1800
 184 #define XTAL_FSEL_S                     9
 185 #define XTAL_FSEL_M                     0x600
 186 #define P6_INTF_DIS                     BIT(8)
 187 #define P5_INTF_MODE_S                  7
 188 #define P5_INTF_MODE_M                  0x80
 189 #define P5_INTF_DIS                     BIT(6)
 190 #define C_MDIO_BPS                      BIT(5)
 191 #define CHIP_MODE_S                     0
 192 #define CHIP_MODE_M                     0x0f
 193
 194 /* P5_INTF_SEL: Interface type of Port5 */
 195 #define P5_INTF_SEL_GPHY                0
 196 #define P5_INTF_SEL_GMAC5               1
 197
 198 /* P5_INTF_MODE: Interface mode of Port5 */
 199 #define P5_INTF_MODE_GMII_MII           0
 200 #define P5_INTF_MODE_RGMII              1
 201
 202 #define MT7530_P6ECR                    0x7830
 203 #define P6_INTF_MODE_M                  0x3
 204 #define P6_INTF_MODE_S                  0
 205
 206 /* P6_INTF_MODE: Interface mode of Port6 */
 207 #define P6_INTF_MODE_RGMII              0
 208 #define P6_INTF_MODE_TRGMII             1
 209
 210 #define MT7530_TRGMII_RD(n)             (0x7a10 + (n) * 8)
 211 #define RD_TAP_S                        0
 212 #define RD_TAP_M                        0x7f
 213
 214 #define MT7530_TRGMII_TD_ODT(n)         (0x7a54 + (n) * 8)
 215 /* XXX: all fields are defined under GMAC_TRGMII_TD_ODT */
 216
 217 /* MT7530 GPHY MDIO Indirect Access Registers */
 218
 219 #define MII_MMD_ACC_CTL_REG             0x0d
 220 #define MMD_CMD_S                       14
 221 #define MMD_CMD_M                       0xc000
 222 #define MMD_DEVAD_S                     0
 223 #define MMD_DEVAD_M                     0x1f
 224
 225 /* MMD_CMD: MMD commands */
 226 #define MMD_ADDR                        0
 227 #define MMD_DATA                        1
 228 #define MMD_DATA_RW_POST_INC            2
 229 #define MMD_DATA_W_POST_INC             3
 230
 231 #define MII_MMD_ADDR_DATA_REG           0x0e
 232
 233 /* MT7530 GPHY MDIO MMD Registers */
 234
 235 #define CORE_PLL_GROUP2                 0x401
 236 #define RG_SYSPLL_EN_NORMAL             BIT(15)
 237 #define RG_SYSPLL_VODEN                 BIT(14)
 238 #define RG_SYSPLL_POSDIV_S              5
 239 #define RG_SYSPLL_POSDIV_M              0x60
 240
 241 #define CORE_PLL_GROUP4                 0x403
 242 #define RG_SYSPLL_DDSFBK_EN             BIT(12)
 243 #define RG_SYSPLL_BIAS_EN               BIT(11)
 244 #define RG_SYSPLL_BIAS_LPF_EN           BIT(10)
 245
 246 #define CORE_PLL_GROUP5                 0x404
 247 #define RG_LCDDS_PCW_NCPO1_S            0
 248 #define RG_LCDDS_PCW_NCPO1_M            0xffff
 249
 250 #define CORE_PLL_GROUP6                 0x405
 251 #define RG_LCDDS_PCW_NCPO0_S            0
 252 #define RG_LCDDS_PCW_NCPO0_M            0xffff
 253
 254 #define CORE_PLL_GROUP7                 0x406
 255 #define RG_LCDDS_PWDB                   BIT(15)
 256 #define RG_LCDDS_ISO_EN                 BIT(13)
 257 #define RG_LCCDS_C_S                    4
 258 #define RG_LCCDS_C_M                    0x70
 259 #define RG_LCDDS_PCW_NCPO_CHG           BIT(3)
 260
 261 #define CORE_PLL_GROUP10                0x409
 262 #define RG_LCDDS_SSC_DELTA_S            0
 263 #define RG_LCDDS_SSC_DELTA_M            0xfff
 264
 265 #define CORE_PLL_GROUP11                0x40a
 266 #define RG_LCDDS_SSC_DELTA1_S           0
 267 #define RG_LCDDS_SSC_DELTA1_M           0xfff
 268
 269 #define CORE_GSWPLL_GRP1                0x40d
 270 #define RG_GSWPLL_POSDIV_200M_S         12
 271 #define RG_GSWPLL_POSDIV_200M_M         0x3000
 272 #define RG_GSWPLL_EN_PRE                BIT(11)
 273 #define RG_GSWPLL_FBKDIV_200M_S         0
 274 #define RG_GSWPLL_FBKDIV_200M_M         0xff
 275
 276 #define CORE_GSWPLL_GRP2                0x40e
 277 #define RG_GSWPLL_POSDIV_500M_S         8
 278 #define RG_GSWPLL_POSDIV_500M_M         0x300
 279 #define RG_GSWPLL_FBKDIV_500M_S         0
 280 #define RG_GSWPLL_FBKDIV_500M_M         0xff
 281
 282 #define CORE_TRGMII_GSW_CLK_CG          0x410
 283 #define REG_GSWCK_EN                    BIT(0)
 284 #define REG_TRGMIICK_EN                 BIT(1)
 285
 286 #endif /* _MTK_ETH_H_ */