drivers/net/mvgbe.c

   1 /*
   2  * (C) Copyright 2009
   3  * Marvell Semiconductor <www.marvell.com>
   4  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   5  *
   6  * (C) Copyright 2003
   7  * Ingo Assmus <ingo.assmus@keymile.com>
   8  *
   9  * based on - Driver for MV64360X ethernet ports
  10  * Copyright (C) 2002 rabeeh@galileo.co.il
  11  *
  12  * SPDX-License-Identifier:     GPL-2.0+
  13  */
  14
  15 #include <common.h>
  16 #include <net.h>
  17 #include <malloc.h>
  18 #include <miiphy.h>
  19 #include <asm/io.h>
  20 #include <asm/errno.h>
  21 #include <asm/types.h>
  22 #include <asm/system.h>
  23 #include <asm/byteorder.h>
  24 #include <asm/arch/cpu.h>
  25
  26 #if defined(CONFIG_KIRKWOOD)
  27 #include <asm/arch/kirkwood.h>
  28 #elif defined(CONFIG_ORION5X)
  29 #include <asm/arch/orion5x.h>
  30 #elif defined(CONFIG_DOVE)
  31 #include <asm/arch/dove.h>
  32 #endif
  33
  34 #include "mvgbe.h"
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 #define MV_PHY_ADR_REQUEST 0xee
  39 #define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
  40
  41 #if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  42 /*
  43  * smi_reg_read - miiphy_read callback function.
  44  *
  45  * Returns 16bit phy register value, or 0xffff on error
  46  */
  47 static int smi_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
  48 {
  49         struct eth_device *dev = eth_get_dev_by_name(devname);
  50         struct mvgbe_device *dmvgbe = to_mvgbe(dev);
  51         struct mvgbe_registers *regs = dmvgbe->regs;
  52         u32 smi_reg;
  53         u32 timeout;
  54
  55         /* Phyadr read request */
  56         if (phy_adr == MV_PHY_ADR_REQUEST &&
  57                         reg_ofs == MV_PHY_ADR_REQUEST) {
  58                 /* */
  59                 *data = (u16) (MVGBE_REG_RD(regs->phyadr) & PHYADR_MASK);
  60                 return 0;
  61         }
  62         /* check parameters */
  63         if (phy_adr > PHYADR_MASK) {
  64                 printf("Err..(%s) Invalid PHY address %d\n",
  65                         __FUNCTION__, phy_adr);
  66                 return -EFAULT;
  67         }
  68         if (reg_ofs > PHYREG_MASK) {
  69                 printf("Err..(%s) Invalid register offset %d\n",
  70                         __FUNCTION__, reg_ofs);
  71                 return -EFAULT;
  72         }
  73
  74         timeout = MVGBE_PHY_SMI_TIMEOUT;
  75         /* wait till the SMI is not busy */
  76         do {
  77                 /* read smi register */
  78                 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
  79                 if (timeout-- == 0) {
  80                         printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
  81                         return -EFAULT;
  82                 }
  83         } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK);
  84
  85         /* fill the phy address and regiser offset and read opcode */
  86         smi_reg = (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
  87                 | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS)
  88                 | MVGBE_PHY_SMI_OPCODE_READ;
  89
  90         /* write the smi register */
  91         MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
  92
  93         /*wait till read value is ready */
  94         timeout = MVGBE_PHY_SMI_TIMEOUT;
  95
  96         do {
  97                 /* read smi register */
  98                 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
  99                 if (timeout-- == 0) {
 100                         printf("Err..(%s) SMI read ready timeout\n",
 101                                 __FUNCTION__);
 102                         return -EFAULT;
 103                 }
 104         } while (!(smi_reg & MVGBE_PHY_SMI_READ_VALID_MASK));
 105
 106         /* Wait for the data to update in the SMI register */
 107         for (timeout = 0; timeout < MVGBE_PHY_SMI_TIMEOUT; timeout++)
 108                 ;
 109
 110         *data = (u16) (MVGBE_REG_RD(MVGBE_SMI_REG) & MVGBE_PHY_SMI_DATA_MASK);
 111
 112         debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr,
 113                 reg_ofs, *data);
 114
 115         return 0;
 116 }
 117
 118 /*
 119  * smi_reg_write - imiiphy_write callback function.
 120  *
 121  * Returns 0 if write succeed, -EINVAL on bad parameters
 122  * -ETIME on timeout
 123  */
 124 static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
 125 {
 126         struct eth_device *dev = eth_get_dev_by_name(devname);
 127         struct mvgbe_device *dmvgbe = to_mvgbe(dev);
 128         struct mvgbe_registers *regs = dmvgbe->regs;
 129         u32 smi_reg;
 130         u32 timeout;
 131
 132         /* Phyadr write request*/
 133         if (phy_adr == MV_PHY_ADR_REQUEST &&
 134                         reg_ofs == MV_PHY_ADR_REQUEST) {
 135                 MVGBE_REG_WR(regs->phyadr, data);
 136                 return 0;
 137         }
 138
 139         /* check parameters */
 140         if (phy_adr > PHYADR_MASK) {
 141                 printf("Err..(%s) Invalid phy address\n", __FUNCTION__);
 142                 return -EINVAL;
 143         }
 144         if (reg_ofs > PHYREG_MASK) {
 145                 printf("Err..(%s) Invalid register offset\n", __FUNCTION__);
 146                 return -EINVAL;
 147         }
 148
 149         /* wait till the SMI is not busy */
 150         timeout = MVGBE_PHY_SMI_TIMEOUT;
 151         do {
 152                 /* read smi register */
 153                 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
 154                 if (timeout-- == 0) {
 155                         printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
 156                         return -ETIME;
 157                 }
 158         } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK);
 159
 160         /* fill the phy addr and reg offset and write opcode and data */
 161         smi_reg = (data << MVGBE_PHY_SMI_DATA_OFFS);
 162         smi_reg |= (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
 163                 | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS);
 164         smi_reg &= ~MVGBE_PHY_SMI_OPCODE_READ;
 165
 166         /* write the smi register */
 167         MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
 168
 169         return 0;
 170 }
 171 #endif
 172
 173 #if defined(CONFIG_PHYLIB)
 174 int mvgbe_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr,
 175                    int reg_addr)
 176 {
 177         u16 data;
 178         int ret;
 179         ret = smi_reg_read(bus->name, phy_addr, reg_addr, &data);
 180         if (ret)
 181                 return ret;
 182         return data;
 183 }
 184
 185 int mvgbe_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr,
 186                     int reg_addr, u16 data)
 187 {
 188         return smi_reg_write(bus->name, phy_addr, reg_addr, data);
 189 }
 190 #endif
 191
 192 /* Stop and checks all queues */
 193 static void stop_queue(u32 * qreg)
 194 {
 195         u32 reg_data;
 196
 197         reg_data = readl(qreg);
 198
 199         if (reg_data & 0xFF) {
 200                 /* Issue stop command for active channels only */
 201                 writel((reg_data << 8), qreg);
 202
 203                 /* Wait for all queue activity to terminate. */
 204                 do {
 205                         /*
 206                          * Check port cause register that all queues
 207                          * are stopped
 208                          */
 209                         reg_data = readl(qreg);
 210                 }
 211                 while (reg_data & 0xFF);
 212         }
 213 }
 214
 215 /*
 216  * set_access_control - Config address decode parameters for Ethernet unit
 217  *
 218  * This function configures the address decode parameters for the Gigabit
 219  * Ethernet Controller according the given parameters struct.
 220  *
 221  * @regs        Register struct pointer.
 222  * @param       Address decode parameter struct.
 223  */
 224 static void set_access_control(struct mvgbe_registers *regs,
 225                                 struct mvgbe_winparam *param)
 226 {
 227         u32 access_prot_reg;
 228
 229         /* Set access control register */
 230         access_prot_reg = MVGBE_REG_RD(regs->epap);
 231         /* clear window permission */
 232         access_prot_reg &= (~(3 << (param->win * 2)));
 233         access_prot_reg |= (param->access_ctrl << (param->win * 2));
 234         MVGBE_REG_WR(regs->epap, access_prot_reg);
 235
 236         /* Set window Size reg (SR) */
 237         MVGBE_REG_WR(regs->barsz[param->win].size,
 238                         (((param->size / 0x10000) - 1) << 16));
 239
 240         /* Set window Base address reg (BA) */
 241         MVGBE_REG_WR(regs->barsz[param->win].bar,
 242                         (param->target | param->attrib | param->base_addr));
 243         /* High address remap reg (HARR) */
 244         if (param->win < 4)
 245                 MVGBE_REG_WR(regs->ha_remap[param->win], param->high_addr);
 246
 247         /* Base address enable reg (BARER) */
 248         if (param->enable == 1)
 249                 MVGBE_REG_BITS_RESET(regs->bare, (1 << param->win));
 250         else
 251                 MVGBE_REG_BITS_SET(regs->bare, (1 << param->win));
 252 }
 253
 254 static void set_dram_access(struct mvgbe_registers *regs)
 255 {
 256         struct mvgbe_winparam win_param;
 257         int i;
 258
 259         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 260                 /* Set access parameters for DRAM bank i */
 261                 win_param.win = i;      /* Use Ethernet window i */
 262                 /* Window target - DDR */
 263                 win_param.target = MVGBE_TARGET_DRAM;
 264                 /* Enable full access */
 265                 win_param.access_ctrl = EWIN_ACCESS_FULL;
 266                 win_param.high_addr = 0;
 267                 /* Get bank base and size */
 268                 win_param.base_addr = gd->bd->bi_dram[i].start;
 269                 win_param.size = gd->bd->bi_dram[i].size;
 270                 if (win_param.size == 0)
 271                         win_param.enable = 0;
 272                 else
 273                         win_param.enable = 1;   /* Enable the access */
 274
 275                 /* Enable DRAM bank */
 276                 switch (i) {
 277                 case 0:
 278                         win_param.attrib = EBAR_DRAM_CS0;
 279                         break;
 280                 case 1:
 281                         win_param.attrib = EBAR_DRAM_CS1;
 282                         break;
 283                 case 2:
 284                         win_param.attrib = EBAR_DRAM_CS2;
 285                         break;
 286                 case 3:
 287                         win_param.attrib = EBAR_DRAM_CS3;
 288                         break;
 289                 default:
 290                         /* invalid bank, disable access */
 291                         win_param.enable = 0;
 292                         win_param.attrib = 0;
 293                         break;
 294                 }
 295                 /* Set the access control for address window(EPAPR) RD/WR */
 296                 set_access_control(regs, &win_param);
 297         }
 298 }
 299
 300 /*
 301  * port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
 302  *
 303  * Go through all the DA filter tables (Unicast, Special Multicast & Other
 304  * Multicast) and set each entry to 0.
 305  */
 306 static void port_init_mac_tables(struct mvgbe_registers *regs)
 307 {
 308         int table_index;
 309
 310         /* Clear DA filter unicast table (Ex_dFUT) */
 311         for (table_index = 0; table_index < 4; ++table_index)
 312                 MVGBE_REG_WR(regs->dfut[table_index], 0);
 313
 314         for (table_index = 0; table_index < 64; ++table_index) {
 315                 /* Clear DA filter special multicast table (Ex_dFSMT) */
 316                 MVGBE_REG_WR(regs->dfsmt[table_index], 0);
 317                 /* Clear DA filter other multicast table (Ex_dFOMT) */
 318                 MVGBE_REG_WR(regs->dfomt[table_index], 0);
 319         }
 320 }
 321
 322 /*
 323  * port_uc_addr - This function Set the port unicast address table
 324  *
 325  * This function locates the proper entry in the Unicast table for the
 326  * specified MAC nibble and sets its properties according to function
 327  * parameters.
 328  * This function add/removes MAC addresses from the port unicast address
 329  * table.
 330  *
 331  * @uc_nibble   Unicast MAC Address last nibble.
 332  * @option      0 = Add, 1 = remove address.
 333  *
 334  * RETURN: 1 if output succeeded. 0 if option parameter is invalid.
 335  */
 336 static int port_uc_addr(struct mvgbe_registers *regs, u8 uc_nibble,
 337                         int option)
 338 {
 339         u32 unicast_reg;
 340         u32 tbl_offset;
 341         u32 reg_offset;
 342
 343         /* Locate the Unicast table entry */
 344         uc_nibble = (0xf & uc_nibble);
 345         /* Register offset from unicast table base */
 346         tbl_offset = (uc_nibble / 4);
 347         /* Entry offset within the above register */
 348         reg_offset = uc_nibble % 4;
 349
 350         switch (option) {
 351         case REJECT_MAC_ADDR:
 352                 /*
 353                  * Clear accepts frame bit at specified unicast
 354                  * DA table entry
 355                  */
 356                 unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
 357                 unicast_reg &= (0xFF << (8 * reg_offset));
 358                 MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
 359                 break;
 360         case ACCEPT_MAC_ADDR:
 361                 /* Set accepts frame bit at unicast DA filter table entry */
 362                 unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
 363                 unicast_reg &= (0xFF << (8 * reg_offset));
 364                 unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset));
 365                 MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
 366                 break;
 367         default:
 368                 return 0;
 369         }
 370         return 1;
 371 }
 372
 373 /*
 374  * port_uc_addr_set - This function Set the port Unicast address.
 375  */
 376 static void port_uc_addr_set(struct mvgbe_registers *regs, u8 * p_addr)
 377 {
 378         u32 mac_h;
 379         u32 mac_l;
 380
 381         mac_l = (p_addr[4] << 8) | (p_addr[5]);
 382         mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
 383                 (p_addr[3] << 0);
 384
 385         MVGBE_REG_WR(regs->macal, mac_l);
 386         MVGBE_REG_WR(regs->macah, mac_h);
 387
 388         /* Accept frames of this address */
 389         port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR);
 390 }
 391
 392 /*
 393  * mvgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
 394  */
 395 static void mvgbe_init_rx_desc_ring(struct mvgbe_device *dmvgbe)
 396 {
 397         struct mvgbe_rxdesc *p_rx_desc;
 398         int i;
 399
 400         /* initialize the Rx descriptors ring */
 401         p_rx_desc = dmvgbe->p_rxdesc;
 402         for (i = 0; i < RINGSZ; i++) {
 403                 p_rx_desc->cmd_sts =
 404                         MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
 405                 p_rx_desc->buf_size = PKTSIZE_ALIGN;
 406                 p_rx_desc->byte_cnt = 0;
 407                 p_rx_desc->buf_ptr = dmvgbe->p_rxbuf + i * PKTSIZE_ALIGN;
 408                 if (i == (RINGSZ - 1))
 409                         p_rx_desc->nxtdesc_p = dmvgbe->p_rxdesc;
 410                 else {
 411                         p_rx_desc->nxtdesc_p = (struct mvgbe_rxdesc *)
 412                                 ((u32) p_rx_desc + MV_RXQ_DESC_ALIGNED_SIZE);
 413                         p_rx_desc = p_rx_desc->nxtdesc_p;
 414                 }
 415         }
 416         dmvgbe->p_rxdesc_curr = dmvgbe->p_rxdesc;
 417 }
 418
 419 static int mvgbe_init(struct eth_device *dev)
 420 {
 421         struct mvgbe_device *dmvgbe = to_mvgbe(dev);
 422         struct mvgbe_registers *regs = dmvgbe->regs;
 423 #if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
 424          && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
 425         int i;
 426 #endif
 427         /* setup RX rings */
 428         mvgbe_init_rx_desc_ring(dmvgbe);
 429
 430         /* Clear the ethernet port interrupts */
 431         MVGBE_REG_WR(regs->ic, 0);
 432         MVGBE_REG_WR(regs->ice, 0);
 433         /* Unmask RX buffer and TX end interrupt */
 434         MVGBE_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
 435         /* Unmask phy and link status changes interrupts */
 436         MVGBE_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
 437
 438         set_dram_access(regs);
 439         port_init_mac_tables(regs);
 440         port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
 441
 442         /* Assign port configuration and command. */
 443         MVGBE_REG_WR(regs->pxc, PRT_CFG_VAL);
 444         MVGBE_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
 445         MVGBE_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
 446
 447         /* Assign port SDMA configuration */
 448         MVGBE_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
 449         MVGBE_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
 450         MVGBE_REG_WR(regs->tqx[0].tqxtbc,
 451                 (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
 452         /* Turn off the port/RXUQ bandwidth limitation */
 453         MVGBE_REG_WR(regs->pmtu, 0);
 454
 455         /* Set maximum receive buffer to 9700 bytes */
 456         MVGBE_REG_WR(regs->psc0, MVGBE_MAX_RX_PACKET_9700BYTE
 457                         | (MVGBE_REG_RD(regs->psc0) & MRU_MASK));
 458
 459         /* Enable port initially */
 460         MVGBE_REG_BITS_SET(regs->psc0, MVGBE_SERIAL_PORT_EN);
 461
 462         /*
 463          * Set ethernet MTU for leaky bucket mechanism to 0 - this will
 464          * disable the leaky bucket mechanism .
 465          */
 466         MVGBE_REG_WR(regs->pmtu, 0);
 467
 468         /* Assignment of Rx CRDB of given RXUQ */
 469         MVGBE_REG_WR(regs->rxcdp[RXUQ], (u32) dmvgbe->p_rxdesc_curr);
 470         /* ensure previous write is done before enabling Rx DMA */
 471         isb();
 472         /* Enable port Rx. */
 473         MVGBE_REG_WR(regs->rqc, (1 << RXUQ));
 474
 475 #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \
 476         !defined(CONFIG_PHYLIB) && \
 477         defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
 478         /* Wait up to 5s for the link status */
 479         for (i = 0; i < 5; i++) {
 480                 u16 phyadr;
 481
 482                 miiphy_read(dev->name, MV_PHY_ADR_REQUEST,
 483                                 MV_PHY_ADR_REQUEST, &phyadr);
 484                 /* Return if we get link up */
 485                 if (miiphy_link(dev->name, phyadr))
 486                         return 0;
 487                 udelay(1000000);
 488         }
 489
 490         printf("No link on %s\n", dev->name);
 491         return -1;
 492 #endif
 493         return 0;
 494 }
 495
 496 static int mvgbe_halt(struct eth_device *dev)
 497 {
 498         struct mvgbe_device *dmvgbe = to_mvgbe(dev);
 499         struct mvgbe_registers *regs = dmvgbe->regs;
 500
 501         /* Disable all gigE address decoder */
 502         MVGBE_REG_WR(regs->bare, 0x3f);
 503
 504         stop_queue(&regs->tqc);
 505         stop_queue(&regs->rqc);
 506
 507         /* Disable port */
 508         MVGBE_REG_BITS_RESET(regs->psc0, MVGBE_SERIAL_PORT_EN);
 509         /* Set port is not reset */
 510         MVGBE_REG_BITS_RESET(regs->psc1, 1 << 4);
 511 #ifdef CONFIG_SYS_MII_MODE
 512         /* Set MMI interface up */
 513         MVGBE_REG_BITS_RESET(regs->psc1, 1 << 3);
 514 #endif
 515         /* Disable & mask ethernet port interrupts */
 516         MVGBE_REG_WR(regs->ic, 0);
 517         MVGBE_REG_WR(regs->ice, 0);
 518         MVGBE_REG_WR(regs->pim, 0);
 519         MVGBE_REG_WR(regs->peim, 0);
 520
 521         return 0;
 522 }
 523
 524 static int mvgbe_write_hwaddr(struct eth_device *dev)
 525 {
 526         struct mvgbe_device *dmvgbe = to_mvgbe(dev);
 527         struct mvgbe_registers *regs = dmvgbe->regs;
 528
 529         /* Programs net device MAC address after initialization */
 530         port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
 531         return 0;
 532 }
 533
 534 static int mvgbe_send(struct eth_device *dev, void *dataptr, int datasize)
 535 {
 536         struct mvgbe_device *dmvgbe = to_mvgbe(dev);
 537         struct mvgbe_registers *regs = dmvgbe->regs;
 538         struct mvgbe_txdesc *p_txdesc = dmvgbe->p_txdesc;
 539         void *p = (void *)dataptr;
 540         u32 cmd_sts;
 541         u32 txuq0_reg_addr;
 542
 543         /* Copy buffer if it's misaligned */
 544         if ((u32) dataptr & 0x07) {
 545                 if (datasize > PKTSIZE_ALIGN) {
 546                         printf("Non-aligned data too large (%d)\n",
 547                                         datasize);
 548                         return -1;
 549                 }
 550
 551                 memcpy(dmvgbe->p_aligned_txbuf, p, datasize);
 552                 p = dmvgbe->p_aligned_txbuf;
 553         }
 554
 555         p_txdesc->cmd_sts = MVGBE_ZERO_PADDING | MVGBE_GEN_CRC;
 556         p_txdesc->cmd_sts |= MVGBE_TX_FIRST_DESC | MVGBE_TX_LAST_DESC;
 557         p_txdesc->cmd_sts |= MVGBE_BUFFER_OWNED_BY_DMA;
 558         p_txdesc->cmd_sts |= MVGBE_TX_EN_INTERRUPT;
 559         p_txdesc->buf_ptr = (u8 *) p;
 560         p_txdesc->byte_cnt = datasize;
 561
 562         /* Set this tc desc as zeroth TXUQ */
 563         txuq0_reg_addr = (u32)&regs->tcqdp[TXUQ];
 564         writel((u32) p_txdesc, txuq0_reg_addr);
 565
 566         /* ensure tx desc writes above are performed before we start Tx DMA */
 567         isb();
 568
 569         /* Apply send command using zeroth TXUQ */
 570         MVGBE_REG_WR(regs->tqc, (1 << TXUQ));
 571
 572         /*
 573          * wait for packet xmit completion
 574          */
 575         cmd_sts = readl(&p_txdesc->cmd_sts);
 576         while (cmd_sts & MVGBE_BUFFER_OWNED_BY_DMA) {
 577                 /* return fail if error is detected */
 578                 if ((cmd_sts & (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME)) ==
 579                                 (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME) &&
 580                                 cmd_sts & (MVGBE_UR_ERROR | MVGBE_RL_ERROR)) {
 581                         printf("Err..(%s) in xmit packet\n", __FUNCTION__);
 582                         return -1;
 583                 }
 584                 cmd_sts = readl(&p_txdesc->cmd_sts);
 585         };
 586         return 0;
 587 }
 588
 589 static int mvgbe_recv(struct eth_device *dev)
 590 {
 591         struct mvgbe_device *dmvgbe = to_mvgbe(dev);
 592         struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr;
 593         u32 cmd_sts;
 594         u32 timeout = 0;
 595         u32 rxdesc_curr_addr;
 596
 597         /* wait untill rx packet available or timeout */
 598         do {
 599                 if (timeout < MVGBE_PHY_SMI_TIMEOUT)
 600                         timeout++;
 601                 else {
 602                         debug("%s time out...\n", __FUNCTION__);
 603                         return -1;
 604                 }
 605         } while (readl(&p_rxdesc_curr->cmd_sts) & MVGBE_BUFFER_OWNED_BY_DMA);
 606
 607         if (p_rxdesc_curr->byte_cnt != 0) {
 608                 debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
 609                         __FUNCTION__, (u32) p_rxdesc_curr->byte_cnt,
 610                         (u32) p_rxdesc_curr->buf_ptr,
 611                         (u32) p_rxdesc_curr->cmd_sts);
 612         }
 613
 614         /*
 615          * In case received a packet without first/last bits on
 616          * OR the error summary bit is on,
 617          * the packets needs to be dropeed.
 618          */
 619         cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
 620
 621         if ((cmd_sts &
 622                 (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC))
 623                 != (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) {
 624
 625                 printf("Err..(%s) Dropping packet spread on"
 626                         " multiple descriptors\n", __FUNCTION__);
 627
 628         } else if (cmd_sts & MVGBE_ERROR_SUMMARY) {
 629
 630                 printf("Err..(%s) Dropping packet with errors\n",
 631                         __FUNCTION__);
 632
 633         } else {
 634                 /* !!! call higher layer processing */
 635                 debug("%s: Sending Received packet to"
 636                         " upper layer (NetReceive)\n", __FUNCTION__);
 637
 638                 /* let the upper layer handle the packet */
 639                 NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET),
 640                         (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
 641         }
 642         /*
 643          * free these descriptors and point next in the ring
 644          */
 645         p_rxdesc_curr->cmd_sts =
 646                 MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
 647         p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
 648         p_rxdesc_curr->byte_cnt = 0;
 649
 650         rxdesc_curr_addr = (u32)&dmvgbe->p_rxdesc_curr;
 651         writel((unsigned)p_rxdesc_curr->nxtdesc_p, rxdesc_curr_addr);
 652
 653         return 0;
 654 }
 655
 656 #if defined(CONFIG_PHYLIB)
 657 int mvgbe_phylib_init(struct eth_device *dev, int phyid)
 658 {
 659         struct mii_dev *bus;
 660         struct phy_device *phydev;
 661         int ret;
 662
 663         bus = mdio_alloc();
 664         if (!bus) {
 665                 printf("mdio_alloc failed\n");
 666                 return -ENOMEM;
 667         }
 668         bus->read = mvgbe_phy_read;
 669         bus->write = mvgbe_phy_write;
 670         sprintf(bus->name, dev->name);
 671
 672         ret = mdio_register(bus);
 673         if (ret) {
 674                 printf("mdio_register failed\n");
 675                 free(bus);
 676                 return -ENOMEM;
 677         }
 678
 679         /* Set phy address of the port */
 680         mvgbe_phy_write(bus, MV_PHY_ADR_REQUEST, 0, MV_PHY_ADR_REQUEST, phyid);
 681
 682         phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RGMII);
 683         if (!phydev) {
 684                 printf("phy_connect failed\n");
 685                 return -ENODEV;
 686         }
 687
 688         phy_config(phydev);
 689         phy_startup(phydev);
 690
 691         return 0;
 692 }
 693 #endif
 694
 695 int mvgbe_initialize(bd_t *bis)
 696 {
 697         struct mvgbe_device *dmvgbe;
 698         struct eth_device *dev;
 699         int devnum;
 700         u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS;
 701
 702         for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) {
 703                 /*skip if port is configured not to use */
 704                 if (used_ports[devnum] == 0)
 705                         continue;
 706
 707                 dmvgbe = malloc(sizeof(struct mvgbe_device));
 708
 709                 if (!dmvgbe)
 710                         goto error1;
 711
 712                 memset(dmvgbe, 0, sizeof(struct mvgbe_device));
 713
 714                 dmvgbe->p_rxdesc =
 715                         (struct mvgbe_rxdesc *)memalign(PKTALIGN,
 716                         MV_RXQ_DESC_ALIGNED_SIZE*RINGSZ + 1);
 717
 718                 if (!dmvgbe->p_rxdesc)
 719                         goto error2;
 720
 721                 dmvgbe->p_rxbuf = (u8 *) memalign(PKTALIGN,
 722                         RINGSZ*PKTSIZE_ALIGN + 1);
 723
 724                 if (!dmvgbe->p_rxbuf)
 725                         goto error3;
 726
 727                 dmvgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
 728
 729                 if (!dmvgbe->p_aligned_txbuf)
 730                         goto error4;
 731
 732                 dmvgbe->p_txdesc = (struct mvgbe_txdesc *) memalign(
 733                         PKTALIGN, sizeof(struct mvgbe_txdesc) + 1);
 734
 735                 if (!dmvgbe->p_txdesc) {
 736                         free(dmvgbe->p_aligned_txbuf);
 737 error4:
 738                         free(dmvgbe->p_rxbuf);
 739 error3:
 740                         free(dmvgbe->p_rxdesc);
 741 error2:
 742                         free(dmvgbe);
 743 error1:
 744                         printf("Err.. %s Failed to allocate memory\n",
 745                                 __FUNCTION__);
 746                         return -1;
 747                 }
 748
 749                 dev = &dmvgbe->dev;
 750
 751                 /* must be less than sizeof(dev->name) */
 752                 sprintf(dev->name, "egiga%d", devnum);
 753
 754                 switch (devnum) {
 755                 case 0:
 756                         dmvgbe->regs = (void *)MVGBE0_BASE;
 757                         break;
 758 #if defined(MVGBE1_BASE)
 759                 case 1:
 760                         dmvgbe->regs = (void *)MVGBE1_BASE;
 761                         break;
 762 #endif
 763                 default:        /* this should never happen */
 764                         printf("Err..(%s) Invalid device number %d\n",
 765                                 __FUNCTION__, devnum);
 766                         return -1;
 767                 }
 768
 769                 dev->init = (void *)mvgbe_init;
 770                 dev->halt = (void *)mvgbe_halt;
 771                 dev->send = (void *)mvgbe_send;
 772                 dev->recv = (void *)mvgbe_recv;
 773                 dev->write_hwaddr = (void *)mvgbe_write_hwaddr;
 774
 775                 eth_register(dev);
 776
 777 #if defined(CONFIG_PHYLIB)
 778                 mvgbe_phylib_init(dev, PHY_BASE_ADR + devnum);
 779 #elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 780                 miiphy_register(dev->name, smi_reg_read, smi_reg_write);
 781                 /* Set phy address of the port */
 782                 miiphy_write(dev->name, MV_PHY_ADR_REQUEST,
 783                                 MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
 784 #endif
 785         }
 786         return 0;
 787 }