drivers/net/mvgbe.c

   1 /*
   2  * (C) Copyright 2009
   3  * Marvell Semiconductor <www.marvell.com>
   4  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   5  *
   6  * (C) Copyright 2003
   7  * Ingo Assmus <ingo.assmus@keymile.com>
   8  *
   9  * based on - Driver for MV64360X ethernet ports
  10  * Copyright (C) 2002 rabeeh@galileo.co.il
  11  *
  12  * See file CREDITS for list of people who contributed to this
  13  * project.
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License as
  17  * published by the Free Software Foundation; either version 2 of
  18  * the License, or (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  28  * MA 02110-1301 USA
  29  */
  30
  31 #include <common.h>
  32 #include <net.h>
  33 #include <malloc.h>
  34 #include <miiphy.h>
  35 #include <asm/io.h>
  36 #include <asm/errno.h>
  37 #include <asm/types.h>
  38 #include <asm/system.h>
  39 #include <asm/byteorder.h>
  40 #include <asm/arch/cpu.h>
  41
  42 #if defined(CONFIG_KIRKWOOD)
  43 #include <asm/arch/kirkwood.h>
  44 #elif defined(CONFIG_ORION5X)
  45 #include <asm/arch/orion5x.h>
  46 #endif
  47
  48 #include "mvgbe.h"
  49
  50 DECLARE_GLOBAL_DATA_PTR;
  51
  52 #define MV_PHY_ADR_REQUEST 0xee
  53 #define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
  54
  55 #if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  56 /*
  57  * smi_reg_read - miiphy_read callback function.
  58  *
  59  * Returns 16bit phy register value, or 0xffff on error
  60  */
  61 static int smi_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
  62 {
  63         struct eth_device *dev = eth_get_dev_by_name(devname);
  64         struct mvgbe_device *dmvgbe = to_mvgbe(dev);
  65         struct mvgbe_registers *regs = dmvgbe->regs;
  66         u32 smi_reg;
  67         u32 timeout;
  68
  69         /* Phyadr read request */
  70         if (phy_adr == MV_PHY_ADR_REQUEST &&
  71                         reg_ofs == MV_PHY_ADR_REQUEST) {
  72                 /* */
  73                 *data = (u16) (MVGBE_REG_RD(regs->phyadr) & PHYADR_MASK);
  74                 return 0;
  75         }
  76         /* check parameters */
  77         if (phy_adr > PHYADR_MASK) {
  78                 printf("Err..(%s) Invalid PHY address %d\n",
  79                         __FUNCTION__, phy_adr);
  80                 return -EFAULT;
  81         }
  82         if (reg_ofs > PHYREG_MASK) {
  83                 printf("Err..(%s) Invalid register offset %d\n",
  84                         __FUNCTION__, reg_ofs);
  85                 return -EFAULT;
  86         }
  87
  88         timeout = MVGBE_PHY_SMI_TIMEOUT;
  89         /* wait till the SMI is not busy */
  90         do {
  91                 /* read smi register */
  92                 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
  93                 if (timeout-- == 0) {
  94                         printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
  95                         return -EFAULT;
  96                 }
  97         } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK);
  98
  99         /* fill the phy address and regiser offset and read opcode */
 100         smi_reg = (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
 101                 | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS)
 102                 | MVGBE_PHY_SMI_OPCODE_READ;
 103
 104         /* write the smi register */
 105         MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
 106
 107         /*wait till read value is ready */
 108         timeout = MVGBE_PHY_SMI_TIMEOUT;
 109
 110         do {
 111                 /* read smi register */
 112                 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
 113                 if (timeout-- == 0) {
 114                         printf("Err..(%s) SMI read ready timeout\n",
 115                                 __FUNCTION__);
 116                         return -EFAULT;
 117                 }
 118         } while (!(smi_reg & MVGBE_PHY_SMI_READ_VALID_MASK));
 119
 120         /* Wait for the data to update in the SMI register */
 121         for (timeout = 0; timeout < MVGBE_PHY_SMI_TIMEOUT; timeout++)
 122                 ;
 123
 124         *data = (u16) (MVGBE_REG_RD(MVGBE_SMI_REG) & MVGBE_PHY_SMI_DATA_MASK);
 125
 126         debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr,
 127                 reg_ofs, *data);
 128
 129         return 0;
 130 }
 131
 132 /*
 133  * smi_reg_write - imiiphy_write callback function.
 134  *
 135  * Returns 0 if write succeed, -EINVAL on bad parameters
 136  * -ETIME on timeout
 137  */
 138 static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
 139 {
 140         struct eth_device *dev = eth_get_dev_by_name(devname);
 141         struct mvgbe_device *dmvgbe = to_mvgbe(dev);
 142         struct mvgbe_registers *regs = dmvgbe->regs;
 143         u32 smi_reg;
 144         u32 timeout;
 145
 146         /* Phyadr write request*/
 147         if (phy_adr == MV_PHY_ADR_REQUEST &&
 148                         reg_ofs == MV_PHY_ADR_REQUEST) {
 149                 MVGBE_REG_WR(regs->phyadr, data);
 150                 return 0;
 151         }
 152
 153         /* check parameters */
 154         if (phy_adr > PHYADR_MASK) {
 155                 printf("Err..(%s) Invalid phy address\n", __FUNCTION__);
 156                 return -EINVAL;
 157         }
 158         if (reg_ofs > PHYREG_MASK) {
 159                 printf("Err..(%s) Invalid register offset\n", __FUNCTION__);
 160                 return -EINVAL;
 161         }
 162
 163         /* wait till the SMI is not busy */
 164         timeout = MVGBE_PHY_SMI_TIMEOUT;
 165         do {
 166                 /* read smi register */
 167                 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
 168                 if (timeout-- == 0) {
 169                         printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
 170                         return -ETIME;
 171                 }
 172         } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK);
 173
 174         /* fill the phy addr and reg offset and write opcode and data */
 175         smi_reg = (data << MVGBE_PHY_SMI_DATA_OFFS);
 176         smi_reg |= (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
 177                 | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS);
 178         smi_reg &= ~MVGBE_PHY_SMI_OPCODE_READ;
 179
 180         /* write the smi register */
 181         MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
 182
 183         return 0;
 184 }
 185 #endif
 186
 187 #if defined(CONFIG_PHYLIB)
 188 int mvgbe_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr,
 189                    int reg_addr)
 190 {
 191         u16 data;
 192         int ret;
 193         ret = smi_reg_read(bus->name, phy_addr, reg_addr, &data);
 194         if (ret)
 195                 return ret;
 196         return data;
 197 }
 198
 199 int mvgbe_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr,
 200                     int reg_addr, u16 data)
 201 {
 202         return smi_reg_write(bus->name, phy_addr, reg_addr, data);
 203 }
 204 #endif
 205
 206 /* Stop and checks all queues */
 207 static void stop_queue(u32 * qreg)
 208 {
 209         u32 reg_data;
 210
 211         reg_data = readl(qreg);
 212
 213         if (reg_data & 0xFF) {
 214                 /* Issue stop command for active channels only */
 215                 writel((reg_data << 8), qreg);
 216
 217                 /* Wait for all queue activity to terminate. */
 218                 do {
 219                         /*
 220                          * Check port cause register that all queues
 221                          * are stopped
 222                          */
 223                         reg_data = readl(qreg);
 224                 }
 225                 while (reg_data & 0xFF);
 226         }
 227 }
 228
 229 /*
 230  * set_access_control - Config address decode parameters for Ethernet unit
 231  *
 232  * This function configures the address decode parameters for the Gigabit
 233  * Ethernet Controller according the given parameters struct.
 234  *
 235  * @regs        Register struct pointer.
 236  * @param       Address decode parameter struct.
 237  */
 238 static void set_access_control(struct mvgbe_registers *regs,
 239                                 struct mvgbe_winparam *param)
 240 {
 241         u32 access_prot_reg;
 242
 243         /* Set access control register */
 244         access_prot_reg = MVGBE_REG_RD(regs->epap);
 245         /* clear window permission */
 246         access_prot_reg &= (~(3 << (param->win * 2)));
 247         access_prot_reg |= (param->access_ctrl << (param->win * 2));
 248         MVGBE_REG_WR(regs->epap, access_prot_reg);
 249
 250         /* Set window Size reg (SR) */
 251         MVGBE_REG_WR(regs->barsz[param->win].size,
 252                         (((param->size / 0x10000) - 1) << 16));
 253
 254         /* Set window Base address reg (BA) */
 255         MVGBE_REG_WR(regs->barsz[param->win].bar,
 256                         (param->target | param->attrib | param->base_addr));
 257         /* High address remap reg (HARR) */
 258         if (param->win < 4)
 259                 MVGBE_REG_WR(regs->ha_remap[param->win], param->high_addr);
 260
 261         /* Base address enable reg (BARER) */
 262         if (param->enable == 1)
 263                 MVGBE_REG_BITS_RESET(regs->bare, (1 << param->win));
 264         else
 265                 MVGBE_REG_BITS_SET(regs->bare, (1 << param->win));
 266 }
 267
 268 static void set_dram_access(struct mvgbe_registers *regs)
 269 {
 270         struct mvgbe_winparam win_param;
 271         int i;
 272
 273         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 274                 /* Set access parameters for DRAM bank i */
 275                 win_param.win = i;      /* Use Ethernet window i */
 276                 /* Window target - DDR */
 277                 win_param.target = MVGBE_TARGET_DRAM;
 278                 /* Enable full access */
 279                 win_param.access_ctrl = EWIN_ACCESS_FULL;
 280                 win_param.high_addr = 0;
 281                 /* Get bank base and size */
 282                 win_param.base_addr = gd->bd->bi_dram[i].start;
 283                 win_param.size = gd->bd->bi_dram[i].size;
 284                 if (win_param.size == 0)
 285                         win_param.enable = 0;
 286                 else
 287                         win_param.enable = 1;   /* Enable the access */
 288
 289                 /* Enable DRAM bank */
 290                 switch (i) {
 291                 case 0:
 292                         win_param.attrib = EBAR_DRAM_CS0;
 293                         break;
 294                 case 1:
 295                         win_param.attrib = EBAR_DRAM_CS1;
 296                         break;
 297                 case 2:
 298                         win_param.attrib = EBAR_DRAM_CS2;
 299                         break;
 300                 case 3:
 301                         win_param.attrib = EBAR_DRAM_CS3;
 302                         break;
 303                 default:
 304                         /* invalid bank, disable access */
 305                         win_param.enable = 0;
 306                         win_param.attrib = 0;
 307                         break;
 308                 }
 309                 /* Set the access control for address window(EPAPR) RD/WR */
 310                 set_access_control(regs, &win_param);
 311         }
 312 }
 313
 314 /*
 315  * port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
 316  *
 317  * Go through all the DA filter tables (Unicast, Special Multicast & Other
 318  * Multicast) and set each entry to 0.
 319  */
 320 static void port_init_mac_tables(struct mvgbe_registers *regs)
 321 {
 322         int table_index;
 323
 324         /* Clear DA filter unicast table (Ex_dFUT) */
 325         for (table_index = 0; table_index < 4; ++table_index)
 326                 MVGBE_REG_WR(regs->dfut[table_index], 0);
 327
 328         for (table_index = 0; table_index < 64; ++table_index) {
 329                 /* Clear DA filter special multicast table (Ex_dFSMT) */
 330                 MVGBE_REG_WR(regs->dfsmt[table_index], 0);
 331                 /* Clear DA filter other multicast table (Ex_dFOMT) */
 332                 MVGBE_REG_WR(regs->dfomt[table_index], 0);
 333         }
 334 }
 335
 336 /*
 337  * port_uc_addr - This function Set the port unicast address table
 338  *
 339  * This function locates the proper entry in the Unicast table for the
 340  * specified MAC nibble and sets its properties according to function
 341  * parameters.
 342  * This function add/removes MAC addresses from the port unicast address
 343  * table.
 344  *
 345  * @uc_nibble   Unicast MAC Address last nibble.
 346  * @option      0 = Add, 1 = remove address.
 347  *
 348  * RETURN: 1 if output succeeded. 0 if option parameter is invalid.
 349  */
 350 static int port_uc_addr(struct mvgbe_registers *regs, u8 uc_nibble,
 351                         int option)
 352 {
 353         u32 unicast_reg;
 354         u32 tbl_offset;
 355         u32 reg_offset;
 356
 357         /* Locate the Unicast table entry */
 358         uc_nibble = (0xf & uc_nibble);
 359         /* Register offset from unicast table base */
 360         tbl_offset = (uc_nibble / 4);
 361         /* Entry offset within the above register */
 362         reg_offset = uc_nibble % 4;
 363
 364         switch (option) {
 365         case REJECT_MAC_ADDR:
 366                 /*
 367                  * Clear accepts frame bit at specified unicast
 368                  * DA table entry
 369                  */
 370                 unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
 371                 unicast_reg &= (0xFF << (8 * reg_offset));
 372                 MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
 373                 break;
 374         case ACCEPT_MAC_ADDR:
 375                 /* Set accepts frame bit at unicast DA filter table entry */
 376                 unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
 377                 unicast_reg &= (0xFF << (8 * reg_offset));
 378                 unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset));
 379                 MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
 380                 break;
 381         default:
 382                 return 0;
 383         }
 384         return 1;
 385 }
 386
 387 /*
 388  * port_uc_addr_set - This function Set the port Unicast address.
 389  */
 390 static void port_uc_addr_set(struct mvgbe_registers *regs, u8 * p_addr)
 391 {
 392         u32 mac_h;
 393         u32 mac_l;
 394
 395         mac_l = (p_addr[4] << 8) | (p_addr[5]);
 396         mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
 397                 (p_addr[3] << 0);
 398
 399         MVGBE_REG_WR(regs->macal, mac_l);
 400         MVGBE_REG_WR(regs->macah, mac_h);
 401
 402         /* Accept frames of this address */
 403         port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR);
 404 }
 405
 406 /*
 407  * mvgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
 408  */
 409 static void mvgbe_init_rx_desc_ring(struct mvgbe_device *dmvgbe)
 410 {
 411         struct mvgbe_rxdesc *p_rx_desc;
 412         int i;
 413
 414         /* initialize the Rx descriptors ring */
 415         p_rx_desc = dmvgbe->p_rxdesc;
 416         for (i = 0; i < RINGSZ; i++) {
 417                 p_rx_desc->cmd_sts =
 418                         MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
 419                 p_rx_desc->buf_size = PKTSIZE_ALIGN;
 420                 p_rx_desc->byte_cnt = 0;
 421                 p_rx_desc->buf_ptr = dmvgbe->p_rxbuf + i * PKTSIZE_ALIGN;
 422                 if (i == (RINGSZ - 1))
 423                         p_rx_desc->nxtdesc_p = dmvgbe->p_rxdesc;
 424                 else {
 425                         p_rx_desc->nxtdesc_p = (struct mvgbe_rxdesc *)
 426                                 ((u32) p_rx_desc + MV_RXQ_DESC_ALIGNED_SIZE);
 427                         p_rx_desc = p_rx_desc->nxtdesc_p;
 428                 }
 429         }
 430         dmvgbe->p_rxdesc_curr = dmvgbe->p_rxdesc;
 431 }
 432
 433 static int mvgbe_init(struct eth_device *dev)
 434 {
 435         struct mvgbe_device *dmvgbe = to_mvgbe(dev);
 436         struct mvgbe_registers *regs = dmvgbe->regs;
 437 #if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
 438          && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
 439         int i;
 440 #endif
 441         /* setup RX rings */
 442         mvgbe_init_rx_desc_ring(dmvgbe);
 443
 444         /* Clear the ethernet port interrupts */
 445         MVGBE_REG_WR(regs->ic, 0);
 446         MVGBE_REG_WR(regs->ice, 0);
 447         /* Unmask RX buffer and TX end interrupt */
 448         MVGBE_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
 449         /* Unmask phy and link status changes interrupts */
 450         MVGBE_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
 451
 452         set_dram_access(regs);
 453         port_init_mac_tables(regs);
 454         port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
 455
 456         /* Assign port configuration and command. */
 457         MVGBE_REG_WR(regs->pxc, PRT_CFG_VAL);
 458         MVGBE_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
 459         MVGBE_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
 460
 461         /* Assign port SDMA configuration */
 462         MVGBE_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
 463         MVGBE_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
 464         MVGBE_REG_WR(regs->tqx[0].tqxtbc,
 465                 (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
 466         /* Turn off the port/RXUQ bandwidth limitation */
 467         MVGBE_REG_WR(regs->pmtu, 0);
 468
 469         /* Set maximum receive buffer to 9700 bytes */
 470         MVGBE_REG_WR(regs->psc0, MVGBE_MAX_RX_PACKET_9700BYTE
 471                         | (MVGBE_REG_RD(regs->psc0) & MRU_MASK));
 472
 473         /* Enable port initially */
 474         MVGBE_REG_BITS_SET(regs->psc0, MVGBE_SERIAL_PORT_EN);
 475
 476         /*
 477          * Set ethernet MTU for leaky bucket mechanism to 0 - this will
 478          * disable the leaky bucket mechanism .
 479          */
 480         MVGBE_REG_WR(regs->pmtu, 0);
 481
 482         /* Assignment of Rx CRDB of given RXUQ */
 483         MVGBE_REG_WR(regs->rxcdp[RXUQ], (u32) dmvgbe->p_rxdesc_curr);
 484         /* ensure previous write is done before enabling Rx DMA */
 485         isb();
 486         /* Enable port Rx. */
 487         MVGBE_REG_WR(regs->rqc, (1 << RXUQ));
 488
 489 #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \
 490         !defined(CONFIG_PHYLIB) && \
 491         defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
 492         /* Wait up to 5s for the link status */
 493         for (i = 0; i < 5; i++) {
 494                 u16 phyadr;
 495
 496                 miiphy_read(dev->name, MV_PHY_ADR_REQUEST,
 497                                 MV_PHY_ADR_REQUEST, &phyadr);
 498                 /* Return if we get link up */
 499                 if (miiphy_link(dev->name, phyadr))
 500                         return 0;
 501                 udelay(1000000);
 502         }
 503
 504         printf("No link on %s\n", dev->name);
 505         return -1;
 506 #endif
 507         return 0;
 508 }
 509
 510 static int mvgbe_halt(struct eth_device *dev)
 511 {
 512         struct mvgbe_device *dmvgbe = to_mvgbe(dev);
 513         struct mvgbe_registers *regs = dmvgbe->regs;
 514
 515         /* Disable all gigE address decoder */
 516         MVGBE_REG_WR(regs->bare, 0x3f);
 517
 518         stop_queue(&regs->tqc);
 519         stop_queue(&regs->rqc);
 520
 521         /* Disable port */
 522         MVGBE_REG_BITS_RESET(regs->psc0, MVGBE_SERIAL_PORT_EN);
 523         /* Set port is not reset */
 524         MVGBE_REG_BITS_RESET(regs->psc1, 1 << 4);
 525 #ifdef CONFIG_SYS_MII_MODE
 526         /* Set MMI interface up */
 527         MVGBE_REG_BITS_RESET(regs->psc1, 1 << 3);
 528 #endif
 529         /* Disable & mask ethernet port interrupts */
 530         MVGBE_REG_WR(regs->ic, 0);
 531         MVGBE_REG_WR(regs->ice, 0);
 532         MVGBE_REG_WR(regs->pim, 0);
 533         MVGBE_REG_WR(regs->peim, 0);
 534
 535         return 0;
 536 }
 537
 538 static int mvgbe_write_hwaddr(struct eth_device *dev)
 539 {
 540         struct mvgbe_device *dmvgbe = to_mvgbe(dev);
 541         struct mvgbe_registers *regs = dmvgbe->regs;
 542
 543         /* Programs net device MAC address after initialization */
 544         port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
 545         return 0;
 546 }
 547
 548 static int mvgbe_send(struct eth_device *dev, void *dataptr, int datasize)
 549 {
 550         struct mvgbe_device *dmvgbe = to_mvgbe(dev);
 551         struct mvgbe_registers *regs = dmvgbe->regs;
 552         struct mvgbe_txdesc *p_txdesc = dmvgbe->p_txdesc;
 553         void *p = (void *)dataptr;
 554         u32 cmd_sts;
 555         u32 txuq0_reg_addr;
 556
 557         /* Copy buffer if it's misaligned */
 558         if ((u32) dataptr & 0x07) {
 559                 if (datasize > PKTSIZE_ALIGN) {
 560                         printf("Non-aligned data too large (%d)\n",
 561                                         datasize);
 562                         return -1;
 563                 }
 564
 565                 memcpy(dmvgbe->p_aligned_txbuf, p, datasize);
 566                 p = dmvgbe->p_aligned_txbuf;
 567         }
 568
 569         p_txdesc->cmd_sts = MVGBE_ZERO_PADDING | MVGBE_GEN_CRC;
 570         p_txdesc->cmd_sts |= MVGBE_TX_FIRST_DESC | MVGBE_TX_LAST_DESC;
 571         p_txdesc->cmd_sts |= MVGBE_BUFFER_OWNED_BY_DMA;
 572         p_txdesc->cmd_sts |= MVGBE_TX_EN_INTERRUPT;
 573         p_txdesc->buf_ptr = (u8 *) p;
 574         p_txdesc->byte_cnt = datasize;
 575
 576         /* Set this tc desc as zeroth TXUQ */
 577         txuq0_reg_addr = (u32)&regs->tcqdp[TXUQ];
 578         writel((u32) p_txdesc, txuq0_reg_addr);
 579
 580         /* ensure tx desc writes above are performed before we start Tx DMA */
 581         isb();
 582
 583         /* Apply send command using zeroth TXUQ */
 584         MVGBE_REG_WR(regs->tqc, (1 << TXUQ));
 585
 586         /*
 587          * wait for packet xmit completion
 588          */
 589         cmd_sts = readl(&p_txdesc->cmd_sts);
 590         while (cmd_sts & MVGBE_BUFFER_OWNED_BY_DMA) {
 591                 /* return fail if error is detected */
 592                 if ((cmd_sts & (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME)) ==
 593                                 (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME) &&
 594                                 cmd_sts & (MVGBE_UR_ERROR | MVGBE_RL_ERROR)) {
 595                         printf("Err..(%s) in xmit packet\n", __FUNCTION__);
 596                         return -1;
 597                 }
 598                 cmd_sts = readl(&p_txdesc->cmd_sts);
 599         };
 600         return 0;
 601 }
 602
 603 static int mvgbe_recv(struct eth_device *dev)
 604 {
 605         struct mvgbe_device *dmvgbe = to_mvgbe(dev);
 606         struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr;
 607         u32 cmd_sts;
 608         u32 timeout = 0;
 609         u32 rxdesc_curr_addr;
 610
 611         /* wait untill rx packet available or timeout */
 612         do {
 613                 if (timeout < MVGBE_PHY_SMI_TIMEOUT)
 614                         timeout++;
 615                 else {
 616                         debug("%s time out...\n", __FUNCTION__);
 617                         return -1;
 618                 }
 619         } while (readl(&p_rxdesc_curr->cmd_sts) & MVGBE_BUFFER_OWNED_BY_DMA);
 620
 621         if (p_rxdesc_curr->byte_cnt != 0) {
 622                 debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
 623                         __FUNCTION__, (u32) p_rxdesc_curr->byte_cnt,
 624                         (u32) p_rxdesc_curr->buf_ptr,
 625                         (u32) p_rxdesc_curr->cmd_sts);
 626         }
 627
 628         /*
 629          * In case received a packet without first/last bits on
 630          * OR the error summary bit is on,
 631          * the packets needs to be dropeed.
 632          */
 633         cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
 634
 635         if ((cmd_sts &
 636                 (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC))
 637                 != (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) {
 638
 639                 printf("Err..(%s) Dropping packet spread on"
 640                         " multiple descriptors\n", __FUNCTION__);
 641
 642         } else if (cmd_sts & MVGBE_ERROR_SUMMARY) {
 643
 644                 printf("Err..(%s) Dropping packet with errors\n",
 645                         __FUNCTION__);
 646
 647         } else {
 648                 /* !!! call higher layer processing */
 649                 debug("%s: Sending Received packet to"
 650                         " upper layer (NetReceive)\n", __FUNCTION__);
 651
 652                 /* let the upper layer handle the packet */
 653                 NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET),
 654                         (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
 655         }
 656         /*
 657          * free these descriptors and point next in the ring
 658          */
 659         p_rxdesc_curr->cmd_sts =
 660                 MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
 661         p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
 662         p_rxdesc_curr->byte_cnt = 0;
 663
 664         rxdesc_curr_addr = (u32)&dmvgbe->p_rxdesc_curr;
 665         writel((unsigned)p_rxdesc_curr->nxtdesc_p, rxdesc_curr_addr);
 666
 667         return 0;
 668 }
 669
 670 #if defined(CONFIG_PHYLIB)
 671 int mvgbe_phylib_init(struct eth_device *dev, int phyid)
 672 {
 673         struct mii_dev *bus;
 674         struct phy_device *phydev;
 675         int ret;
 676
 677         bus = mdio_alloc();
 678         if (!bus) {
 679                 printf("mdio_alloc failed\n");
 680                 return -ENOMEM;
 681         }
 682         bus->read = mvgbe_phy_read;
 683         bus->write = mvgbe_phy_write;
 684         sprintf(bus->name, dev->name);
 685
 686         ret = mdio_register(bus);
 687         if (ret) {
 688                 printf("mdio_register failed\n");
 689                 free(bus);
 690                 return -ENOMEM;
 691         }
 692
 693         /* Set phy address of the port */
 694         mvgbe_phy_write(bus, MV_PHY_ADR_REQUEST, 0, MV_PHY_ADR_REQUEST, phyid);
 695
 696         phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RGMII);
 697         if (!phydev) {
 698                 printf("phy_connect failed\n");
 699                 return -ENODEV;
 700         }
 701
 702         phy_config(phydev);
 703         phy_startup(phydev);
 704
 705         return 0;
 706 }
 707 #endif
 708
 709 int mvgbe_initialize(bd_t *bis)
 710 {
 711         struct mvgbe_device *dmvgbe;
 712         struct eth_device *dev;
 713         int devnum;
 714         u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS;
 715
 716         for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) {
 717                 /*skip if port is configured not to use */
 718                 if (used_ports[devnum] == 0)
 719                         continue;
 720
 721                 dmvgbe = malloc(sizeof(struct mvgbe_device));
 722
 723                 if (!dmvgbe)
 724                         goto error1;
 725
 726                 memset(dmvgbe, 0, sizeof(struct mvgbe_device));
 727
 728                 dmvgbe->p_rxdesc =
 729                         (struct mvgbe_rxdesc *)memalign(PKTALIGN,
 730                         MV_RXQ_DESC_ALIGNED_SIZE*RINGSZ + 1);
 731
 732                 if (!dmvgbe->p_rxdesc)
 733                         goto error2;
 734
 735                 dmvgbe->p_rxbuf = (u8 *) memalign(PKTALIGN,
 736                         RINGSZ*PKTSIZE_ALIGN + 1);
 737
 738                 if (!dmvgbe->p_rxbuf)
 739                         goto error3;
 740
 741                 dmvgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
 742
 743                 if (!dmvgbe->p_aligned_txbuf)
 744                         goto error4;
 745
 746                 dmvgbe->p_txdesc = (struct mvgbe_txdesc *) memalign(
 747                         PKTALIGN, sizeof(struct mvgbe_txdesc) + 1);
 748
 749                 if (!dmvgbe->p_txdesc) {
 750                         free(dmvgbe->p_aligned_txbuf);
 751 error4:
 752                         free(dmvgbe->p_rxbuf);
 753 error3:
 754                         free(dmvgbe->p_rxdesc);
 755 error2:
 756                         free(dmvgbe);
 757 error1:
 758                         printf("Err.. %s Failed to allocate memory\n",
 759                                 __FUNCTION__);
 760                         return -1;
 761                 }
 762
 763                 dev = &dmvgbe->dev;
 764
 765                 /* must be less than sizeof(dev->name) */
 766                 sprintf(dev->name, "egiga%d", devnum);
 767
 768                 switch (devnum) {
 769                 case 0:
 770                         dmvgbe->regs = (void *)MVGBE0_BASE;
 771                         break;
 772 #if defined(MVGBE1_BASE)
 773                 case 1:
 774                         dmvgbe->regs = (void *)MVGBE1_BASE;
 775                         break;
 776 #endif
 777                 default:        /* this should never happen */
 778                         printf("Err..(%s) Invalid device number %d\n",
 779                                 __FUNCTION__, devnum);
 780                         return -1;
 781                 }
 782
 783                 dev->init = (void *)mvgbe_init;
 784                 dev->halt = (void *)mvgbe_halt;
 785                 dev->send = (void *)mvgbe_send;
 786                 dev->recv = (void *)mvgbe_recv;
 787                 dev->write_hwaddr = (void *)mvgbe_write_hwaddr;
 788
 789                 eth_register(dev);
 790
 791 #if defined(CONFIG_PHYLIB)
 792                 mvgbe_phylib_init(dev, PHY_BASE_ADR + devnum);
 793 #elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 794                 miiphy_register(dev->name, smi_reg_read, smi_reg_write);
 795                 /* Set phy address of the port */
 796                 miiphy_write(dev->name, MV_PHY_ADR_REQUEST,
 797                                 MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
 798 #endif
 799         }
 800         return 0;
 801 }