2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
5 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
7 * Based on the Linux version which is:
8 * Copyright (C) 2012 Marvell
10 * Rami Rosen <rosenr@marvell.com>
11 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 * SPDX-License-Identifier: GPL-2.0
23 #include <linux/errno.h>
27 #include <asm/arch/cpu.h>
28 #include <asm/arch/soc.h>
29 #include <linux/compat.h>
30 #include <linux/mbus.h>
32 DECLARE_GLOBAL_DATA_PTR
;
34 #if !defined(CONFIG_PHYLIB)
35 # error Marvell mvneta requires PHYLIB
38 /* Some linux -> U-Boot compatibility stuff */
39 #define netdev_err(dev, fmt, args...) \
41 #define netdev_warn(dev, fmt, args...) \
43 #define netdev_info(dev, fmt, args...) \
46 #define CONFIG_NR_CPUS 1
47 #define ETH_HLEN 14 /* Total octets in header */
49 /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
50 #define WRAP (2 + ETH_HLEN + 4 + 32)
52 #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
54 #define MVNETA_SMI_TIMEOUT 10000
57 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
58 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1)
59 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
60 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
61 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
62 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
63 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
64 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
65 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
66 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
67 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
68 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
69 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
70 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
71 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
72 #define MVNETA_PORT_RX_RESET 0x1cc0
73 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
74 #define MVNETA_PHY_ADDR 0x2000
75 #define MVNETA_PHY_ADDR_MASK 0x1f
76 #define MVNETA_SMI 0x2004
77 #define MVNETA_PHY_REG_MASK 0x1f
78 /* SMI register fields */
79 #define MVNETA_SMI_DATA_OFFS 0 /* Data */
80 #define MVNETA_SMI_DATA_MASK (0xffff << MVNETA_SMI_DATA_OFFS)
81 #define MVNETA_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
82 #define MVNETA_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/
83 #define MVNETA_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
84 #define MVNETA_SMI_OPCODE_READ (1 << MVNETA_SMI_OPCODE_OFFS)
85 #define MVNETA_SMI_READ_VALID (1 << 27) /* Read Valid */
86 #define MVNETA_SMI_BUSY (1 << 28) /* Busy */
87 #define MVNETA_MBUS_RETRY 0x2010
88 #define MVNETA_UNIT_INTR_CAUSE 0x2080
89 #define MVNETA_UNIT_CONTROL 0x20B0
90 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
91 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
92 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
93 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
94 #define MVNETA_WIN_SIZE_MASK (0xffff0000)
95 #define MVNETA_BASE_ADDR_ENABLE 0x2290
96 #define MVNETA_BASE_ADDR_ENABLE_BIT 0x1
97 #define MVNETA_PORT_ACCESS_PROTECT 0x2294
98 #define MVNETA_PORT_ACCESS_PROTECT_WIN0_RW 0x3
99 #define MVNETA_PORT_CONFIG 0x2400
100 #define MVNETA_UNI_PROMISC_MODE BIT(0)
101 #define MVNETA_DEF_RXQ(q) ((q) << 1)
102 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
103 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
104 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
105 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
106 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
107 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
108 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
109 MVNETA_DEF_RXQ_ARP(q) | \
110 MVNETA_DEF_RXQ_TCP(q) | \
111 MVNETA_DEF_RXQ_UDP(q) | \
112 MVNETA_DEF_RXQ_BPDU(q) | \
113 MVNETA_TX_UNSET_ERR_SUM | \
114 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
115 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
116 #define MVNETA_MAC_ADDR_LOW 0x2414
117 #define MVNETA_MAC_ADDR_HIGH 0x2418
118 #define MVNETA_SDMA_CONFIG 0x241c
119 #define MVNETA_SDMA_BRST_SIZE_16 4
120 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
121 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
122 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
123 #define MVNETA_DESC_SWAP BIT(6)
124 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
125 #define MVNETA_PORT_STATUS 0x2444
126 #define MVNETA_TX_IN_PRGRS BIT(1)
127 #define MVNETA_TX_FIFO_EMPTY BIT(8)
128 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
129 #define MVNETA_SERDES_CFG 0x24A0
130 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
131 #define MVNETA_QSGMII_SERDES_PROTO 0x0667
132 #define MVNETA_TYPE_PRIO 0x24bc
133 #define MVNETA_FORCE_UNI BIT(21)
134 #define MVNETA_TXQ_CMD_1 0x24e4
135 #define MVNETA_TXQ_CMD 0x2448
136 #define MVNETA_TXQ_DISABLE_SHIFT 8
137 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
138 #define MVNETA_ACC_MODE 0x2500
139 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
140 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
141 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
142 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
144 /* Exception Interrupt Port/Queue Cause register */
146 #define MVNETA_INTR_NEW_CAUSE 0x25a0
147 #define MVNETA_INTR_NEW_MASK 0x25a4
149 /* bits 0..7 = TXQ SENT, one bit per queue.
150 * bits 8..15 = RXQ OCCUP, one bit per queue.
151 * bits 16..23 = RXQ FREE, one bit per queue.
152 * bit 29 = OLD_REG_SUM, see old reg ?
153 * bit 30 = TX_ERR_SUM, one bit for 4 ports
154 * bit 31 = MISC_SUM, one bit for 4 ports
156 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
157 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
158 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
159 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
161 #define MVNETA_INTR_OLD_CAUSE 0x25a8
162 #define MVNETA_INTR_OLD_MASK 0x25ac
164 /* Data Path Port/Queue Cause Register */
165 #define MVNETA_INTR_MISC_CAUSE 0x25b0
166 #define MVNETA_INTR_MISC_MASK 0x25b4
167 #define MVNETA_INTR_ENABLE 0x25b8
169 #define MVNETA_RXQ_CMD 0x2680
170 #define MVNETA_RXQ_DISABLE_SHIFT 8
171 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
172 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
173 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
174 #define MVNETA_GMAC_CTRL_0 0x2c00
175 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
176 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
177 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
178 #define MVNETA_GMAC_CTRL_2 0x2c08
179 #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
180 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
181 #define MVNETA_GMAC2_PORT_RESET BIT(6)
182 #define MVNETA_GMAC_STATUS 0x2c10
183 #define MVNETA_GMAC_LINK_UP BIT(0)
184 #define MVNETA_GMAC_SPEED_1000 BIT(1)
185 #define MVNETA_GMAC_SPEED_100 BIT(2)
186 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
187 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
188 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
189 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
190 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
191 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
192 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
193 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
194 #define MVNETA_GMAC_FORCE_LINK_UP (BIT(0) | BIT(1))
195 #define MVNETA_GMAC_IB_BYPASS_AN_EN BIT(3)
196 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
197 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
198 #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
199 #define MVNETA_GMAC_SET_FC_EN BIT(8)
200 #define MVNETA_GMAC_ADVERT_FC_EN BIT(9)
201 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
202 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
203 #define MVNETA_GMAC_SAMPLE_TX_CFG_EN BIT(15)
204 #define MVNETA_MIB_COUNTERS_BASE 0x3080
205 #define MVNETA_MIB_LATE_COLLISION 0x7c
206 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
207 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
208 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
209 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
210 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
211 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
212 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
213 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
214 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
215 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
216 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
217 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
218 #define MVNETA_PORT_TX_RESET 0x3cf0
219 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
220 #define MVNETA_TX_MTU 0x3e0c
221 #define MVNETA_TX_TOKEN_SIZE 0x3e14
222 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
223 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
224 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
226 /* Descriptor ring Macros */
227 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
228 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
230 /* Various constants */
233 #define MVNETA_TXDONE_COAL_PKTS 16
234 #define MVNETA_RX_COAL_PKTS 32
235 #define MVNETA_RX_COAL_USEC 100
237 /* The two bytes Marvell header. Either contains a special value used
238 * by Marvell switches when a specific hardware mode is enabled (not
239 * supported by this driver) or is filled automatically by zeroes on
240 * the RX side. Those two bytes being at the front of the Ethernet
241 * header, they allow to have the IP header aligned on a 4 bytes
242 * boundary automatically: the hardware skips those two bytes on its
245 #define MVNETA_MH_SIZE 2
247 #define MVNETA_VLAN_TAG_LEN 4
249 #define MVNETA_CPU_D_CACHE_LINE_SIZE 32
250 #define MVNETA_TX_CSUM_MAX_SIZE 9800
251 #define MVNETA_ACC_MODE_EXT 1
253 /* Timeout constants */
254 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
255 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
256 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
258 #define MVNETA_TX_MTU_MAX 0x3ffff
260 /* Max number of Rx descriptors */
261 #define MVNETA_MAX_RXD 16
263 /* Max number of Tx descriptors */
264 #define MVNETA_MAX_TXD 16
266 /* descriptor aligned size */
267 #define MVNETA_DESC_ALIGNED_SIZE 32
271 struct mvneta_rx_queue
*rxqs
;
272 struct mvneta_tx_queue
*txqs
;
278 phy_interface_t phy_interface
;
285 struct phy_device
*phydev
;
289 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
290 * layout of the transmit and reception DMA descriptors, and their
291 * layout is therefore defined by the hardware design
294 #define MVNETA_TX_L3_OFF_SHIFT 0
295 #define MVNETA_TX_IP_HLEN_SHIFT 8
296 #define MVNETA_TX_L4_UDP BIT(16)
297 #define MVNETA_TX_L3_IP6 BIT(17)
298 #define MVNETA_TXD_IP_CSUM BIT(18)
299 #define MVNETA_TXD_Z_PAD BIT(19)
300 #define MVNETA_TXD_L_DESC BIT(20)
301 #define MVNETA_TXD_F_DESC BIT(21)
302 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
303 MVNETA_TXD_L_DESC | \
305 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
306 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
308 #define MVNETA_RXD_ERR_CRC 0x0
309 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
310 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
311 #define MVNETA_RXD_ERR_LEN BIT(18)
312 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
313 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
314 #define MVNETA_RXD_L3_IP4 BIT(25)
315 #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
316 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
318 struct mvneta_tx_desc
{
319 u32 command
; /* Options used by HW for packet transmitting.*/
320 u16 reserverd1
; /* csum_l4 (for future use) */
321 u16 data_size
; /* Data size of transmitted packet in bytes */
322 u32 buf_phys_addr
; /* Physical addr of transmitted buffer */
323 u32 reserved2
; /* hw_cmd - (for future use, PMT) */
324 u32 reserved3
[4]; /* Reserved - (for future use) */
327 struct mvneta_rx_desc
{
328 u32 status
; /* Info about received packet */
329 u16 reserved1
; /* pnc_info - (for future use, PnC) */
330 u16 data_size
; /* Size of received packet in bytes */
332 u32 buf_phys_addr
; /* Physical address of the buffer */
333 u32 reserved2
; /* pnc_flow_id (for future use, PnC) */
335 u32 buf_cookie
; /* cookie for access to RX buffer in rx path */
336 u16 reserved3
; /* prefetch_cmd, for future use */
337 u16 reserved4
; /* csum_l4 - (for future use, PnC) */
339 u32 reserved5
; /* pnc_extra PnC (for future use, PnC) */
340 u32 reserved6
; /* hw_cmd (for future use, PnC and HWF) */
343 struct mvneta_tx_queue
{
344 /* Number of this TX queue, in the range 0-7 */
347 /* Number of TX DMA descriptors in the descriptor ring */
350 /* Index of last TX DMA descriptor that was inserted */
353 /* Index of the TX DMA descriptor to be cleaned up */
356 /* Virtual address of the TX DMA descriptors array */
357 struct mvneta_tx_desc
*descs
;
359 /* DMA address of the TX DMA descriptors array */
360 dma_addr_t descs_phys
;
362 /* Index of the last TX DMA descriptor */
365 /* Index of the next TX DMA descriptor to process */
366 int next_desc_to_proc
;
369 struct mvneta_rx_queue
{
370 /* rx queue number, in the range 0-7 */
373 /* num of rx descriptors in the rx descriptor ring */
376 /* Virtual address of the RX DMA descriptors array */
377 struct mvneta_rx_desc
*descs
;
379 /* DMA address of the RX DMA descriptors array */
380 dma_addr_t descs_phys
;
382 /* Index of the last RX DMA descriptor */
385 /* Index of the next RX DMA descriptor to process */
386 int next_desc_to_proc
;
389 /* U-Boot doesn't use the queues, so set the number to 1 */
390 static int rxq_number
= 1;
391 static int txq_number
= 1;
394 struct buffer_location
{
395 struct mvneta_tx_desc
*tx_descs
;
396 struct mvneta_rx_desc
*rx_descs
;
401 * All 4 interfaces use the same global buffer, since only one interface
402 * can be enabled at once
404 static struct buffer_location buffer_loc
;
407 * Page table entries are set to 1MB, or multiples of 1MB
408 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
410 #define BD_SPACE (1 << 20)
413 * Dummy implementation that can be overwritten by a board
416 __weak
int board_network_enable(struct mii_dev
*bus
)
421 /* Utility/helper methods */
423 /* Write helper method */
424 static void mvreg_write(struct mvneta_port
*pp
, u32 offset
, u32 data
)
426 writel(data
, pp
->base
+ offset
);
429 /* Read helper method */
430 static u32
mvreg_read(struct mvneta_port
*pp
, u32 offset
)
432 return readl(pp
->base
+ offset
);
435 /* Clear all MIB counters */
436 static void mvneta_mib_counters_clear(struct mvneta_port
*pp
)
440 /* Perform dummy reads from MIB counters */
441 for (i
= 0; i
< MVNETA_MIB_LATE_COLLISION
; i
+= 4)
442 mvreg_read(pp
, (MVNETA_MIB_COUNTERS_BASE
+ i
));
445 /* Rx descriptors helper methods */
447 /* Checks whether the RX descriptor having this status is both the first
448 * and the last descriptor for the RX packet. Each RX packet is currently
449 * received through a single RX descriptor, so not having each RX
450 * descriptor with its first and last bits set is an error
452 static int mvneta_rxq_desc_is_first_last(u32 status
)
454 return (status
& MVNETA_RXD_FIRST_LAST_DESC
) ==
455 MVNETA_RXD_FIRST_LAST_DESC
;
458 /* Add number of descriptors ready to receive new packets */
459 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port
*pp
,
460 struct mvneta_rx_queue
*rxq
,
463 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
466 while (ndescs
> MVNETA_RXQ_ADD_NON_OCCUPIED_MAX
) {
467 mvreg_write(pp
, MVNETA_RXQ_STATUS_UPDATE_REG(rxq
->id
),
468 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX
<<
469 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT
));
470 ndescs
-= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX
;
473 mvreg_write(pp
, MVNETA_RXQ_STATUS_UPDATE_REG(rxq
->id
),
474 (ndescs
<< MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT
));
477 /* Get number of RX descriptors occupied by received packets */
478 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port
*pp
,
479 struct mvneta_rx_queue
*rxq
)
483 val
= mvreg_read(pp
, MVNETA_RXQ_STATUS_REG(rxq
->id
));
484 return val
& MVNETA_RXQ_OCCUPIED_ALL_MASK
;
487 /* Update num of rx desc called upon return from rx path or
488 * from mvneta_rxq_drop_pkts().
490 static void mvneta_rxq_desc_num_update(struct mvneta_port
*pp
,
491 struct mvneta_rx_queue
*rxq
,
492 int rx_done
, int rx_filled
)
496 if ((rx_done
<= 0xff) && (rx_filled
<= 0xff)) {
498 (rx_filled
<< MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT
);
499 mvreg_write(pp
, MVNETA_RXQ_STATUS_UPDATE_REG(rxq
->id
), val
);
503 /* Only 255 descriptors can be added at once */
504 while ((rx_done
> 0) || (rx_filled
> 0)) {
505 if (rx_done
<= 0xff) {
512 if (rx_filled
<= 0xff) {
513 val
|= rx_filled
<< MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT
;
516 val
|= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT
;
519 mvreg_write(pp
, MVNETA_RXQ_STATUS_UPDATE_REG(rxq
->id
), val
);
523 /* Get pointer to next RX descriptor to be processed by SW */
524 static struct mvneta_rx_desc
*
525 mvneta_rxq_next_desc_get(struct mvneta_rx_queue
*rxq
)
527 int rx_desc
= rxq
->next_desc_to_proc
;
529 rxq
->next_desc_to_proc
= MVNETA_QUEUE_NEXT_DESC(rxq
, rx_desc
);
530 return rxq
->descs
+ rx_desc
;
533 /* Tx descriptors helper methods */
535 /* Update HW with number of TX descriptors to be sent */
536 static void mvneta_txq_pend_desc_add(struct mvneta_port
*pp
,
537 struct mvneta_tx_queue
*txq
,
542 /* Only 255 descriptors can be added at once ; Assume caller
543 * process TX desriptors in quanta less than 256
546 mvreg_write(pp
, MVNETA_TXQ_UPDATE_REG(txq
->id
), val
);
549 /* Get pointer to next TX descriptor to be processed (send) by HW */
550 static struct mvneta_tx_desc
*
551 mvneta_txq_next_desc_get(struct mvneta_tx_queue
*txq
)
553 int tx_desc
= txq
->next_desc_to_proc
;
555 txq
->next_desc_to_proc
= MVNETA_QUEUE_NEXT_DESC(txq
, tx_desc
);
556 return txq
->descs
+ tx_desc
;
559 /* Set rxq buf size */
560 static void mvneta_rxq_buf_size_set(struct mvneta_port
*pp
,
561 struct mvneta_rx_queue
*rxq
,
566 val
= mvreg_read(pp
, MVNETA_RXQ_SIZE_REG(rxq
->id
));
568 val
&= ~MVNETA_RXQ_BUF_SIZE_MASK
;
569 val
|= ((buf_size
>> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT
);
571 mvreg_write(pp
, MVNETA_RXQ_SIZE_REG(rxq
->id
), val
);
574 static int mvneta_port_is_fixed_link(struct mvneta_port
*pp
)
576 /* phy_addr is set to invalid value for fixed link */
577 return pp
->phyaddr
> PHY_MAX_ADDR
;
581 /* Start the Ethernet port RX and TX activity */
582 static void mvneta_port_up(struct mvneta_port
*pp
)
587 /* Enable all initialized TXs. */
588 mvneta_mib_counters_clear(pp
);
590 for (queue
= 0; queue
< txq_number
; queue
++) {
591 struct mvneta_tx_queue
*txq
= &pp
->txqs
[queue
];
592 if (txq
->descs
!= NULL
)
593 q_map
|= (1 << queue
);
595 mvreg_write(pp
, MVNETA_TXQ_CMD
, q_map
);
597 /* Enable all initialized RXQs. */
599 for (queue
= 0; queue
< rxq_number
; queue
++) {
600 struct mvneta_rx_queue
*rxq
= &pp
->rxqs
[queue
];
601 if (rxq
->descs
!= NULL
)
602 q_map
|= (1 << queue
);
604 mvreg_write(pp
, MVNETA_RXQ_CMD
, q_map
);
607 /* Stop the Ethernet port activity */
608 static void mvneta_port_down(struct mvneta_port
*pp
)
613 /* Stop Rx port activity. Check port Rx activity. */
614 val
= mvreg_read(pp
, MVNETA_RXQ_CMD
) & MVNETA_RXQ_ENABLE_MASK
;
616 /* Issue stop command for active channels only */
618 mvreg_write(pp
, MVNETA_RXQ_CMD
,
619 val
<< MVNETA_RXQ_DISABLE_SHIFT
);
621 /* Wait for all Rx activity to terminate. */
624 if (count
++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC
) {
626 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
632 val
= mvreg_read(pp
, MVNETA_RXQ_CMD
);
633 } while (val
& 0xff);
635 /* Stop Tx port activity. Check port Tx activity. Issue stop
636 * command for active channels only
638 val
= (mvreg_read(pp
, MVNETA_TXQ_CMD
)) & MVNETA_TXQ_ENABLE_MASK
;
641 mvreg_write(pp
, MVNETA_TXQ_CMD
,
642 (val
<< MVNETA_TXQ_DISABLE_SHIFT
));
644 /* Wait for all Tx activity to terminate. */
647 if (count
++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC
) {
649 "TIMEOUT for TX stopped status=0x%08x\n",
655 /* Check TX Command reg that all Txqs are stopped */
656 val
= mvreg_read(pp
, MVNETA_TXQ_CMD
);
658 } while (val
& 0xff);
660 /* Double check to verify that TX FIFO is empty */
663 if (count
++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT
) {
665 "TX FIFO empty timeout status=0x08%x\n",
671 val
= mvreg_read(pp
, MVNETA_PORT_STATUS
);
672 } while (!(val
& MVNETA_TX_FIFO_EMPTY
) &&
673 (val
& MVNETA_TX_IN_PRGRS
));
678 /* Enable the port by setting the port enable bit of the MAC control register */
679 static void mvneta_port_enable(struct mvneta_port
*pp
)
684 val
= mvreg_read(pp
, MVNETA_GMAC_CTRL_0
);
685 val
|= MVNETA_GMAC0_PORT_ENABLE
;
686 mvreg_write(pp
, MVNETA_GMAC_CTRL_0
, val
);
689 /* Disable the port and wait for about 200 usec before retuning */
690 static void mvneta_port_disable(struct mvneta_port
*pp
)
694 /* Reset the Enable bit in the Serial Control Register */
695 val
= mvreg_read(pp
, MVNETA_GMAC_CTRL_0
);
696 val
&= ~MVNETA_GMAC0_PORT_ENABLE
;
697 mvreg_write(pp
, MVNETA_GMAC_CTRL_0
, val
);
702 /* Multicast tables methods */
704 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
705 static void mvneta_set_ucast_table(struct mvneta_port
*pp
, int queue
)
713 val
= 0x1 | (queue
<< 1);
714 val
|= (val
<< 24) | (val
<< 16) | (val
<< 8);
717 for (offset
= 0; offset
<= 0xc; offset
+= 4)
718 mvreg_write(pp
, MVNETA_DA_FILT_UCAST_BASE
+ offset
, val
);
721 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
722 static void mvneta_set_special_mcast_table(struct mvneta_port
*pp
, int queue
)
730 val
= 0x1 | (queue
<< 1);
731 val
|= (val
<< 24) | (val
<< 16) | (val
<< 8);
734 for (offset
= 0; offset
<= 0xfc; offset
+= 4)
735 mvreg_write(pp
, MVNETA_DA_FILT_SPEC_MCAST
+ offset
, val
);
738 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
739 static void mvneta_set_other_mcast_table(struct mvneta_port
*pp
, int queue
)
745 memset(pp
->mcast_count
, 0, sizeof(pp
->mcast_count
));
748 memset(pp
->mcast_count
, 1, sizeof(pp
->mcast_count
));
749 val
= 0x1 | (queue
<< 1);
750 val
|= (val
<< 24) | (val
<< 16) | (val
<< 8);
753 for (offset
= 0; offset
<= 0xfc; offset
+= 4)
754 mvreg_write(pp
, MVNETA_DA_FILT_OTH_MCAST
+ offset
, val
);
757 /* This method sets defaults to the NETA port:
758 * Clears interrupt Cause and Mask registers.
759 * Clears all MAC tables.
760 * Sets defaults to all registers.
761 * Resets RX and TX descriptor rings.
763 * This method can be called after mvneta_port_down() to return the port
764 * settings to defaults.
766 static void mvneta_defaults_set(struct mvneta_port
*pp
)
772 /* Clear all Cause registers */
773 mvreg_write(pp
, MVNETA_INTR_NEW_CAUSE
, 0);
774 mvreg_write(pp
, MVNETA_INTR_OLD_CAUSE
, 0);
775 mvreg_write(pp
, MVNETA_INTR_MISC_CAUSE
, 0);
777 /* Mask all interrupts */
778 mvreg_write(pp
, MVNETA_INTR_NEW_MASK
, 0);
779 mvreg_write(pp
, MVNETA_INTR_OLD_MASK
, 0);
780 mvreg_write(pp
, MVNETA_INTR_MISC_MASK
, 0);
781 mvreg_write(pp
, MVNETA_INTR_ENABLE
, 0);
783 /* Enable MBUS Retry bit16 */
784 mvreg_write(pp
, MVNETA_MBUS_RETRY
, 0x20);
786 /* Set CPU queue access map - all CPUs have access to all RX
787 * queues and to all TX queues
789 for (cpu
= 0; cpu
< CONFIG_NR_CPUS
; cpu
++)
790 mvreg_write(pp
, MVNETA_CPU_MAP(cpu
),
791 (MVNETA_CPU_RXQ_ACCESS_ALL_MASK
|
792 MVNETA_CPU_TXQ_ACCESS_ALL_MASK
));
794 /* Reset RX and TX DMAs */
795 mvreg_write(pp
, MVNETA_PORT_RX_RESET
, MVNETA_PORT_RX_DMA_RESET
);
796 mvreg_write(pp
, MVNETA_PORT_TX_RESET
, MVNETA_PORT_TX_DMA_RESET
);
798 /* Disable Legacy WRR, Disable EJP, Release from reset */
799 mvreg_write(pp
, MVNETA_TXQ_CMD_1
, 0);
800 for (queue
= 0; queue
< txq_number
; queue
++) {
801 mvreg_write(pp
, MVETH_TXQ_TOKEN_COUNT_REG(queue
), 0);
802 mvreg_write(pp
, MVETH_TXQ_TOKEN_CFG_REG(queue
), 0);
805 mvreg_write(pp
, MVNETA_PORT_TX_RESET
, 0);
806 mvreg_write(pp
, MVNETA_PORT_RX_RESET
, 0);
808 /* Set Port Acceleration Mode */
809 val
= MVNETA_ACC_MODE_EXT
;
810 mvreg_write(pp
, MVNETA_ACC_MODE
, val
);
812 /* Update val of portCfg register accordingly with all RxQueue types */
813 val
= MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def
);
814 mvreg_write(pp
, MVNETA_PORT_CONFIG
, val
);
817 mvreg_write(pp
, MVNETA_PORT_CONFIG_EXTEND
, val
);
818 mvreg_write(pp
, MVNETA_RX_MIN_FRAME_SIZE
, 64);
820 /* Build PORT_SDMA_CONFIG_REG */
823 /* Default burst size */
824 val
|= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16
);
825 val
|= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16
);
826 val
|= MVNETA_RX_NO_DATA_SWAP
| MVNETA_TX_NO_DATA_SWAP
;
828 /* Assign port SDMA configuration */
829 mvreg_write(pp
, MVNETA_SDMA_CONFIG
, val
);
831 /* Enable PHY polling in hardware if not in fixed-link mode */
832 if (!mvneta_port_is_fixed_link(pp
)) {
833 val
= mvreg_read(pp
, MVNETA_UNIT_CONTROL
);
834 val
|= MVNETA_PHY_POLLING_ENABLE
;
835 mvreg_write(pp
, MVNETA_UNIT_CONTROL
, val
);
838 mvneta_set_ucast_table(pp
, -1);
839 mvneta_set_special_mcast_table(pp
, -1);
840 mvneta_set_other_mcast_table(pp
, -1);
843 /* Set unicast address */
844 static void mvneta_set_ucast_addr(struct mvneta_port
*pp
, u8 last_nibble
,
847 unsigned int unicast_reg
;
848 unsigned int tbl_offset
;
849 unsigned int reg_offset
;
851 /* Locate the Unicast table entry */
852 last_nibble
= (0xf & last_nibble
);
854 /* offset from unicast tbl base */
855 tbl_offset
= (last_nibble
/ 4) * 4;
857 /* offset within the above reg */
858 reg_offset
= last_nibble
% 4;
860 unicast_reg
= mvreg_read(pp
, (MVNETA_DA_FILT_UCAST_BASE
+ tbl_offset
));
863 /* Clear accepts frame bit at specified unicast DA tbl entry */
864 unicast_reg
&= ~(0xff << (8 * reg_offset
));
866 unicast_reg
&= ~(0xff << (8 * reg_offset
));
867 unicast_reg
|= ((0x01 | (queue
<< 1)) << (8 * reg_offset
));
870 mvreg_write(pp
, (MVNETA_DA_FILT_UCAST_BASE
+ tbl_offset
), unicast_reg
);
873 /* Set mac address */
874 static void mvneta_mac_addr_set(struct mvneta_port
*pp
, unsigned char *addr
,
881 mac_l
= (addr
[4] << 8) | (addr
[5]);
882 mac_h
= (addr
[0] << 24) | (addr
[1] << 16) |
883 (addr
[2] << 8) | (addr
[3] << 0);
885 mvreg_write(pp
, MVNETA_MAC_ADDR_LOW
, mac_l
);
886 mvreg_write(pp
, MVNETA_MAC_ADDR_HIGH
, mac_h
);
889 /* Accept frames of this address */
890 mvneta_set_ucast_addr(pp
, addr
[5], queue
);
893 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
894 static void mvneta_rx_desc_fill(struct mvneta_rx_desc
*rx_desc
,
895 u32 phys_addr
, u32 cookie
)
897 rx_desc
->buf_cookie
= cookie
;
898 rx_desc
->buf_phys_addr
= phys_addr
;
901 /* Decrement sent descriptors counter */
902 static void mvneta_txq_sent_desc_dec(struct mvneta_port
*pp
,
903 struct mvneta_tx_queue
*txq
,
908 /* Only 255 TX descriptors can be updated at once */
909 while (sent_desc
> 0xff) {
910 val
= 0xff << MVNETA_TXQ_DEC_SENT_SHIFT
;
911 mvreg_write(pp
, MVNETA_TXQ_UPDATE_REG(txq
->id
), val
);
912 sent_desc
= sent_desc
- 0xff;
915 val
= sent_desc
<< MVNETA_TXQ_DEC_SENT_SHIFT
;
916 mvreg_write(pp
, MVNETA_TXQ_UPDATE_REG(txq
->id
), val
);
919 /* Get number of TX descriptors already sent by HW */
920 static int mvneta_txq_sent_desc_num_get(struct mvneta_port
*pp
,
921 struct mvneta_tx_queue
*txq
)
926 val
= mvreg_read(pp
, MVNETA_TXQ_STATUS_REG(txq
->id
));
927 sent_desc
= (val
& MVNETA_TXQ_SENT_DESC_MASK
) >>
928 MVNETA_TXQ_SENT_DESC_SHIFT
;
933 /* Display more error info */
934 static void mvneta_rx_error(struct mvneta_port
*pp
,
935 struct mvneta_rx_desc
*rx_desc
)
937 u32 status
= rx_desc
->status
;
939 if (!mvneta_rxq_desc_is_first_last(status
)) {
941 "bad rx status %08x (buffer oversize), size=%d\n",
942 status
, rx_desc
->data_size
);
946 switch (status
& MVNETA_RXD_ERR_CODE_MASK
) {
947 case MVNETA_RXD_ERR_CRC
:
948 netdev_err(pp
->dev
, "bad rx status %08x (crc error), size=%d\n",
949 status
, rx_desc
->data_size
);
951 case MVNETA_RXD_ERR_OVERRUN
:
952 netdev_err(pp
->dev
, "bad rx status %08x (overrun error), size=%d\n",
953 status
, rx_desc
->data_size
);
955 case MVNETA_RXD_ERR_LEN
:
956 netdev_err(pp
->dev
, "bad rx status %08x (max frame length error), size=%d\n",
957 status
, rx_desc
->data_size
);
959 case MVNETA_RXD_ERR_RESOURCE
:
960 netdev_err(pp
->dev
, "bad rx status %08x (resource error), size=%d\n",
961 status
, rx_desc
->data_size
);
966 static struct mvneta_rx_queue
*mvneta_rxq_handle_get(struct mvneta_port
*pp
,
969 return &pp
->rxqs
[rxq
];
973 /* Drop packets received by the RXQ and free buffers */
974 static void mvneta_rxq_drop_pkts(struct mvneta_port
*pp
,
975 struct mvneta_rx_queue
*rxq
)
979 rx_done
= mvneta_rxq_busy_desc_num_get(pp
, rxq
);
981 mvneta_rxq_desc_num_update(pp
, rxq
, rx_done
, rx_done
);
984 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
985 static int mvneta_rxq_fill(struct mvneta_port
*pp
, struct mvneta_rx_queue
*rxq
,
990 for (i
= 0; i
< num
; i
++) {
993 /* U-Boot special: Fill in the rx buffer addresses */
994 addr
= buffer_loc
.rx_buffers
+ (i
* RX_BUFFER_SIZE
);
995 mvneta_rx_desc_fill(rxq
->descs
+ i
, addr
, addr
);
998 /* Add this number of RX descriptors as non occupied (ready to
1001 mvneta_rxq_non_occup_desc_add(pp
, rxq
, i
);
1006 /* Rx/Tx queue initialization/cleanup methods */
1008 /* Create a specified RX queue */
1009 static int mvneta_rxq_init(struct mvneta_port
*pp
,
1010 struct mvneta_rx_queue
*rxq
)
1013 rxq
->size
= pp
->rx_ring_size
;
1015 /* Allocate memory for RX descriptors */
1016 rxq
->descs_phys
= (dma_addr_t
)rxq
->descs
;
1017 if (rxq
->descs
== NULL
)
1020 rxq
->last_desc
= rxq
->size
- 1;
1022 /* Set Rx descriptors queue starting address */
1023 mvreg_write(pp
, MVNETA_RXQ_BASE_ADDR_REG(rxq
->id
), rxq
->descs_phys
);
1024 mvreg_write(pp
, MVNETA_RXQ_SIZE_REG(rxq
->id
), rxq
->size
);
1026 /* Fill RXQ with buffers from RX pool */
1027 mvneta_rxq_buf_size_set(pp
, rxq
, RX_BUFFER_SIZE
);
1028 mvneta_rxq_fill(pp
, rxq
, rxq
->size
);
1033 /* Cleanup Rx queue */
1034 static void mvneta_rxq_deinit(struct mvneta_port
*pp
,
1035 struct mvneta_rx_queue
*rxq
)
1037 mvneta_rxq_drop_pkts(pp
, rxq
);
1041 rxq
->next_desc_to_proc
= 0;
1042 rxq
->descs_phys
= 0;
1045 /* Create and initialize a tx queue */
1046 static int mvneta_txq_init(struct mvneta_port
*pp
,
1047 struct mvneta_tx_queue
*txq
)
1049 txq
->size
= pp
->tx_ring_size
;
1051 /* Allocate memory for TX descriptors */
1052 txq
->descs_phys
= (dma_addr_t
)txq
->descs
;
1053 if (txq
->descs
== NULL
)
1056 txq
->last_desc
= txq
->size
- 1;
1058 /* Set maximum bandwidth for enabled TXQs */
1059 mvreg_write(pp
, MVETH_TXQ_TOKEN_CFG_REG(txq
->id
), 0x03ffffff);
1060 mvreg_write(pp
, MVETH_TXQ_TOKEN_COUNT_REG(txq
->id
), 0x3fffffff);
1062 /* Set Tx descriptors queue starting address */
1063 mvreg_write(pp
, MVNETA_TXQ_BASE_ADDR_REG(txq
->id
), txq
->descs_phys
);
1064 mvreg_write(pp
, MVNETA_TXQ_SIZE_REG(txq
->id
), txq
->size
);
1069 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
1070 static void mvneta_txq_deinit(struct mvneta_port
*pp
,
1071 struct mvneta_tx_queue
*txq
)
1075 txq
->next_desc_to_proc
= 0;
1076 txq
->descs_phys
= 0;
1078 /* Set minimum bandwidth for disabled TXQs */
1079 mvreg_write(pp
, MVETH_TXQ_TOKEN_CFG_REG(txq
->id
), 0);
1080 mvreg_write(pp
, MVETH_TXQ_TOKEN_COUNT_REG(txq
->id
), 0);
1082 /* Set Tx descriptors queue starting address and size */
1083 mvreg_write(pp
, MVNETA_TXQ_BASE_ADDR_REG(txq
->id
), 0);
1084 mvreg_write(pp
, MVNETA_TXQ_SIZE_REG(txq
->id
), 0);
1087 /* Cleanup all Tx queues */
1088 static void mvneta_cleanup_txqs(struct mvneta_port
*pp
)
1092 for (queue
= 0; queue
< txq_number
; queue
++)
1093 mvneta_txq_deinit(pp
, &pp
->txqs
[queue
]);
1096 /* Cleanup all Rx queues */
1097 static void mvneta_cleanup_rxqs(struct mvneta_port
*pp
)
1101 for (queue
= 0; queue
< rxq_number
; queue
++)
1102 mvneta_rxq_deinit(pp
, &pp
->rxqs
[queue
]);
1106 /* Init all Rx queues */
1107 static int mvneta_setup_rxqs(struct mvneta_port
*pp
)
1111 for (queue
= 0; queue
< rxq_number
; queue
++) {
1112 int err
= mvneta_rxq_init(pp
, &pp
->rxqs
[queue
]);
1114 netdev_err(pp
->dev
, "%s: can't create rxq=%d\n",
1116 mvneta_cleanup_rxqs(pp
);
1124 /* Init all tx queues */
1125 static int mvneta_setup_txqs(struct mvneta_port
*pp
)
1129 for (queue
= 0; queue
< txq_number
; queue
++) {
1130 int err
= mvneta_txq_init(pp
, &pp
->txqs
[queue
]);
1132 netdev_err(pp
->dev
, "%s: can't create txq=%d\n",
1134 mvneta_cleanup_txqs(pp
);
1142 static void mvneta_start_dev(struct mvneta_port
*pp
)
1144 /* start the Rx/Tx activity */
1145 mvneta_port_enable(pp
);
1148 static void mvneta_adjust_link(struct udevice
*dev
)
1150 struct mvneta_port
*pp
= dev_get_priv(dev
);
1151 struct phy_device
*phydev
= pp
->phydev
;
1152 int status_change
= 0;
1154 if (mvneta_port_is_fixed_link(pp
)) {
1155 debug("Using fixed link, skip link adjust\n");
1160 if ((pp
->speed
!= phydev
->speed
) ||
1161 (pp
->duplex
!= phydev
->duplex
)) {
1164 val
= mvreg_read(pp
, MVNETA_GMAC_AUTONEG_CONFIG
);
1165 val
&= ~(MVNETA_GMAC_CONFIG_MII_SPEED
|
1166 MVNETA_GMAC_CONFIG_GMII_SPEED
|
1167 MVNETA_GMAC_CONFIG_FULL_DUPLEX
|
1168 MVNETA_GMAC_AN_SPEED_EN
|
1169 MVNETA_GMAC_AN_DUPLEX_EN
);
1172 val
|= MVNETA_GMAC_CONFIG_FULL_DUPLEX
;
1174 if (phydev
->speed
== SPEED_1000
)
1175 val
|= MVNETA_GMAC_CONFIG_GMII_SPEED
;
1177 val
|= MVNETA_GMAC_CONFIG_MII_SPEED
;
1179 mvreg_write(pp
, MVNETA_GMAC_AUTONEG_CONFIG
, val
);
1181 pp
->duplex
= phydev
->duplex
;
1182 pp
->speed
= phydev
->speed
;
1186 if (phydev
->link
!= pp
->link
) {
1187 if (!phydev
->link
) {
1192 pp
->link
= phydev
->link
;
1196 if (status_change
) {
1198 u32 val
= mvreg_read(pp
, MVNETA_GMAC_AUTONEG_CONFIG
);
1199 val
|= (MVNETA_GMAC_FORCE_LINK_PASS
|
1200 MVNETA_GMAC_FORCE_LINK_DOWN
);
1201 mvreg_write(pp
, MVNETA_GMAC_AUTONEG_CONFIG
, val
);
1204 mvneta_port_down(pp
);
1209 static int mvneta_open(struct udevice
*dev
)
1211 struct mvneta_port
*pp
= dev_get_priv(dev
);
1214 ret
= mvneta_setup_rxqs(pp
);
1218 ret
= mvneta_setup_txqs(pp
);
1222 mvneta_adjust_link(dev
);
1224 mvneta_start_dev(pp
);
1230 static int mvneta_init2(struct mvneta_port
*pp
)
1235 mvneta_port_disable(pp
);
1237 /* Set port default values */
1238 mvneta_defaults_set(pp
);
1240 pp
->txqs
= kzalloc(txq_number
* sizeof(struct mvneta_tx_queue
),
1245 /* U-Boot special: use preallocated area */
1246 pp
->txqs
[0].descs
= buffer_loc
.tx_descs
;
1248 /* Initialize TX descriptor rings */
1249 for (queue
= 0; queue
< txq_number
; queue
++) {
1250 struct mvneta_tx_queue
*txq
= &pp
->txqs
[queue
];
1252 txq
->size
= pp
->tx_ring_size
;
1255 pp
->rxqs
= kzalloc(rxq_number
* sizeof(struct mvneta_rx_queue
),
1262 /* U-Boot special: use preallocated area */
1263 pp
->rxqs
[0].descs
= buffer_loc
.rx_descs
;
1265 /* Create Rx descriptor rings */
1266 for (queue
= 0; queue
< rxq_number
; queue
++) {
1267 struct mvneta_rx_queue
*rxq
= &pp
->rxqs
[queue
];
1269 rxq
->size
= pp
->rx_ring_size
;
1275 /* platform glue : initialize decoding windows */
1278 * Not like A380, in Armada3700, there are two layers of decode windows for GBE:
1279 * First layer is: GbE Address window that resides inside the GBE unit,
1280 * Second layer is: Fabric address window which is located in the NIC400
1282 * To simplify the address decode configuration for Armada3700, we bypass the
1283 * first layer of GBE decode window by setting the first window to 4GB.
1285 static void mvneta_bypass_mbus_windows(struct mvneta_port
*pp
)
1288 * Set window size to 4GB, to bypass GBE address decode, leave the
1289 * work to MBUS decode window
1291 mvreg_write(pp
, MVNETA_WIN_SIZE(0), MVNETA_WIN_SIZE_MASK
);
1293 /* Enable GBE address decode window 0 by set bit 0 to 0 */
1294 clrbits_le32(pp
->base
+ MVNETA_BASE_ADDR_ENABLE
,
1295 MVNETA_BASE_ADDR_ENABLE_BIT
);
1297 /* Set GBE address decode window 0 to full Access (read or write) */
1298 setbits_le32(pp
->base
+ MVNETA_PORT_ACCESS_PROTECT
,
1299 MVNETA_PORT_ACCESS_PROTECT_WIN0_RW
);
1302 static void mvneta_conf_mbus_windows(struct mvneta_port
*pp
)
1304 const struct mbus_dram_target_info
*dram
;
1309 dram
= mvebu_mbus_dram_info();
1310 for (i
= 0; i
< 6; i
++) {
1311 mvreg_write(pp
, MVNETA_WIN_BASE(i
), 0);
1312 mvreg_write(pp
, MVNETA_WIN_SIZE(i
), 0);
1315 mvreg_write(pp
, MVNETA_WIN_REMAP(i
), 0);
1321 for (i
= 0; i
< dram
->num_cs
; i
++) {
1322 const struct mbus_dram_window
*cs
= dram
->cs
+ i
;
1323 mvreg_write(pp
, MVNETA_WIN_BASE(i
), (cs
->base
& 0xffff0000) |
1324 (cs
->mbus_attr
<< 8) | dram
->mbus_dram_target_id
);
1326 mvreg_write(pp
, MVNETA_WIN_SIZE(i
),
1327 (cs
->size
- 1) & 0xffff0000);
1329 win_enable
&= ~(1 << i
);
1330 win_protect
|= 3 << (2 * i
);
1333 mvreg_write(pp
, MVNETA_BASE_ADDR_ENABLE
, win_enable
);
1336 /* Power up the port */
1337 static int mvneta_port_power_up(struct mvneta_port
*pp
, int phy_mode
)
1341 /* MAC Cause register should be cleared */
1342 mvreg_write(pp
, MVNETA_UNIT_INTR_CAUSE
, 0);
1344 ctrl
= mvreg_read(pp
, MVNETA_GMAC_CTRL_2
);
1346 /* Even though it might look weird, when we're configured in
1347 * SGMII or QSGMII mode, the RGMII bit needs to be set.
1350 case PHY_INTERFACE_MODE_QSGMII
:
1351 mvreg_write(pp
, MVNETA_SERDES_CFG
, MVNETA_QSGMII_SERDES_PROTO
);
1352 ctrl
|= MVNETA_GMAC2_PCS_ENABLE
| MVNETA_GMAC2_PORT_RGMII
;
1354 case PHY_INTERFACE_MODE_SGMII
:
1355 mvreg_write(pp
, MVNETA_SERDES_CFG
, MVNETA_SGMII_SERDES_PROTO
);
1356 ctrl
|= MVNETA_GMAC2_PCS_ENABLE
| MVNETA_GMAC2_PORT_RGMII
;
1358 case PHY_INTERFACE_MODE_RGMII
:
1359 case PHY_INTERFACE_MODE_RGMII_ID
:
1360 ctrl
|= MVNETA_GMAC2_PORT_RGMII
;
1366 /* Cancel Port Reset */
1367 ctrl
&= ~MVNETA_GMAC2_PORT_RESET
;
1368 mvreg_write(pp
, MVNETA_GMAC_CTRL_2
, ctrl
);
1370 while ((mvreg_read(pp
, MVNETA_GMAC_CTRL_2
) &
1371 MVNETA_GMAC2_PORT_RESET
) != 0)
1377 /* Device initialization routine */
1378 static int mvneta_init(struct udevice
*dev
)
1380 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
1381 struct mvneta_port
*pp
= dev_get_priv(dev
);
1384 pp
->tx_ring_size
= MVNETA_MAX_TXD
;
1385 pp
->rx_ring_size
= MVNETA_MAX_RXD
;
1387 err
= mvneta_init2(pp
);
1389 dev_err(&pdev
->dev
, "can't init eth hal\n");
1393 mvneta_mac_addr_set(pp
, pdata
->enetaddr
, rxq_def
);
1395 err
= mvneta_port_power_up(pp
, pp
->phy_interface
);
1397 dev_err(&pdev
->dev
, "can't power up port\n");
1401 /* Call open() now as it needs to be done before runing send() */
1407 /* U-Boot only functions follow here */
1409 /* SMI / MDIO functions */
1411 static int smi_wait_ready(struct mvneta_port
*pp
)
1413 u32 timeout
= MVNETA_SMI_TIMEOUT
;
1416 /* wait till the SMI is not busy */
1418 /* read smi register */
1419 smi_reg
= mvreg_read(pp
, MVNETA_SMI
);
1420 if (timeout
-- == 0) {
1421 printf("Error: SMI busy timeout\n");
1424 } while (smi_reg
& MVNETA_SMI_BUSY
);
1430 * mvneta_mdio_read - miiphy_read callback function.
1432 * Returns 16bit phy register value, or 0xffff on error
1434 static int mvneta_mdio_read(struct mii_dev
*bus
, int addr
, int devad
, int reg
)
1436 struct mvneta_port
*pp
= bus
->priv
;
1440 /* check parameters */
1441 if (addr
> MVNETA_PHY_ADDR_MASK
) {
1442 printf("Error: Invalid PHY address %d\n", addr
);
1446 if (reg
> MVNETA_PHY_REG_MASK
) {
1447 printf("Err: Invalid register offset %d\n", reg
);
1451 /* wait till the SMI is not busy */
1452 if (smi_wait_ready(pp
) < 0)
1455 /* fill the phy address and regiser offset and read opcode */
1456 smi_reg
= (addr
<< MVNETA_SMI_DEV_ADDR_OFFS
)
1457 | (reg
<< MVNETA_SMI_REG_ADDR_OFFS
)
1458 | MVNETA_SMI_OPCODE_READ
;
1460 /* write the smi register */
1461 mvreg_write(pp
, MVNETA_SMI
, smi_reg
);
1463 /* wait till read value is ready */
1464 timeout
= MVNETA_SMI_TIMEOUT
;
1467 /* read smi register */
1468 smi_reg
= mvreg_read(pp
, MVNETA_SMI
);
1469 if (timeout
-- == 0) {
1470 printf("Err: SMI read ready timeout\n");
1473 } while (!(smi_reg
& MVNETA_SMI_READ_VALID
));
1475 /* Wait for the data to update in the SMI register */
1476 for (timeout
= 0; timeout
< MVNETA_SMI_TIMEOUT
; timeout
++)
1479 return mvreg_read(pp
, MVNETA_SMI
) & MVNETA_SMI_DATA_MASK
;
1483 * mvneta_mdio_write - miiphy_write callback function.
1485 * Returns 0 if write succeed, -EINVAL on bad parameters
1488 static int mvneta_mdio_write(struct mii_dev
*bus
, int addr
, int devad
, int reg
,
1491 struct mvneta_port
*pp
= bus
->priv
;
1494 /* check parameters */
1495 if (addr
> MVNETA_PHY_ADDR_MASK
) {
1496 printf("Error: Invalid PHY address %d\n", addr
);
1500 if (reg
> MVNETA_PHY_REG_MASK
) {
1501 printf("Err: Invalid register offset %d\n", reg
);
1505 /* wait till the SMI is not busy */
1506 if (smi_wait_ready(pp
) < 0)
1509 /* fill the phy addr and reg offset and write opcode and data */
1510 smi_reg
= value
<< MVNETA_SMI_DATA_OFFS
;
1511 smi_reg
|= (addr
<< MVNETA_SMI_DEV_ADDR_OFFS
)
1512 | (reg
<< MVNETA_SMI_REG_ADDR_OFFS
);
1513 smi_reg
&= ~MVNETA_SMI_OPCODE_READ
;
1515 /* write the smi register */
1516 mvreg_write(pp
, MVNETA_SMI
, smi_reg
);
1521 static int mvneta_start(struct udevice
*dev
)
1523 struct mvneta_port
*pp
= dev_get_priv(dev
);
1524 struct phy_device
*phydev
;
1526 mvneta_port_power_up(pp
, pp
->phy_interface
);
1528 if (!pp
->init
|| pp
->link
== 0) {
1529 if (mvneta_port_is_fixed_link(pp
)) {
1536 val
= MVNETA_GMAC_FORCE_LINK_UP
|
1537 MVNETA_GMAC_IB_BYPASS_AN_EN
|
1538 MVNETA_GMAC_SET_FC_EN
|
1539 MVNETA_GMAC_ADVERT_FC_EN
|
1540 MVNETA_GMAC_SAMPLE_TX_CFG_EN
;
1543 val
|= MVNETA_GMAC_CONFIG_FULL_DUPLEX
;
1545 if (pp
->speed
== SPEED_1000
)
1546 val
|= MVNETA_GMAC_CONFIG_GMII_SPEED
;
1547 else if (pp
->speed
== SPEED_100
)
1548 val
|= MVNETA_GMAC_CONFIG_MII_SPEED
;
1550 mvreg_write(pp
, MVNETA_GMAC_AUTONEG_CONFIG
, val
);
1552 /* Set phy address of the port */
1553 mvreg_write(pp
, MVNETA_PHY_ADDR
, pp
->phyaddr
);
1555 phydev
= phy_connect(pp
->bus
, pp
->phyaddr
, dev
,
1558 pp
->phydev
= phydev
;
1560 phy_startup(phydev
);
1561 if (!phydev
->link
) {
1562 printf("%s: No link.\n", phydev
->dev
->name
);
1566 /* Full init on first call */
1573 /* Upon all following calls, this is enough */
1575 mvneta_port_enable(pp
);
1580 static int mvneta_send(struct udevice
*dev
, void *packet
, int length
)
1582 struct mvneta_port
*pp
= dev_get_priv(dev
);
1583 struct mvneta_tx_queue
*txq
= &pp
->txqs
[0];
1584 struct mvneta_tx_desc
*tx_desc
;
1588 /* Get a descriptor for the first part of the packet */
1589 tx_desc
= mvneta_txq_next_desc_get(txq
);
1591 tx_desc
->buf_phys_addr
= (u32
)(uintptr_t)packet
;
1592 tx_desc
->data_size
= length
;
1593 flush_dcache_range((ulong
)packet
,
1594 (ulong
)packet
+ ALIGN(length
, PKTALIGN
));
1596 /* First and Last descriptor */
1597 tx_desc
->command
= MVNETA_TX_L4_CSUM_NOT
| MVNETA_TXD_FLZ_DESC
;
1598 mvneta_txq_pend_desc_add(pp
, txq
, 1);
1600 /* Wait for packet to be sent (queue might help with speed here) */
1601 sent_desc
= mvneta_txq_sent_desc_num_get(pp
, txq
);
1602 while (!sent_desc
) {
1603 if (timeout
++ > 10000) {
1604 printf("timeout: packet not sent\n");
1607 sent_desc
= mvneta_txq_sent_desc_num_get(pp
, txq
);
1610 /* txDone has increased - hw sent packet */
1611 mvneta_txq_sent_desc_dec(pp
, txq
, sent_desc
);
1616 static int mvneta_recv(struct udevice
*dev
, int flags
, uchar
**packetp
)
1618 struct mvneta_port
*pp
= dev_get_priv(dev
);
1620 struct mvneta_rx_queue
*rxq
;
1624 rxq
= mvneta_rxq_handle_get(pp
, rxq_def
);
1625 rx_done
= mvneta_rxq_busy_desc_num_get(pp
, rxq
);
1628 struct mvneta_rx_desc
*rx_desc
;
1629 unsigned char *data
;
1633 * No cache invalidation needed here, since the desc's are
1634 * located in a uncached memory region
1636 rx_desc
= mvneta_rxq_next_desc_get(rxq
);
1638 rx_status
= rx_desc
->status
;
1639 if (!mvneta_rxq_desc_is_first_last(rx_status
) ||
1640 (rx_status
& MVNETA_RXD_ERR_SUMMARY
)) {
1641 mvneta_rx_error(pp
, rx_desc
);
1642 /* leave the descriptor untouched */
1646 /* 2 bytes for marvell header. 4 bytes for crc */
1647 rx_bytes
= rx_desc
->data_size
- 6;
1649 /* give packet to stack - skip on first 2 bytes */
1650 data
= (u8
*)(uintptr_t)rx_desc
->buf_cookie
+ 2;
1652 * No cache invalidation needed here, since the rx_buffer's are
1653 * located in a uncached memory region
1657 mvneta_rxq_desc_num_update(pp
, rxq
, rx_done
, rx_done
);
1663 static int mvneta_probe(struct udevice
*dev
)
1665 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
1666 struct mvneta_port
*pp
= dev_get_priv(dev
);
1667 void *blob
= (void *)gd
->fdt_blob
;
1668 int node
= dev_of_offset(dev
);
1669 struct mii_dev
*bus
;
1676 * Allocate buffer area for descs and rx_buffers. This is only
1677 * done once for all interfaces. As only one interface can
1678 * be active. Make this area DMA safe by disabling the D-cache
1680 if (!buffer_loc
.tx_descs
) {
1681 /* Align buffer area for descs and rx_buffers to 1MiB */
1682 bd_space
= memalign(1 << MMU_SECTION_SHIFT
, BD_SPACE
);
1683 mmu_set_region_dcache_behaviour((phys_addr_t
)bd_space
, BD_SPACE
,
1685 buffer_loc
.tx_descs
= (struct mvneta_tx_desc
*)bd_space
;
1686 buffer_loc
.rx_descs
= (struct mvneta_rx_desc
*)
1687 ((phys_addr_t
)bd_space
+
1688 MVNETA_MAX_TXD
* sizeof(struct mvneta_tx_desc
));
1689 buffer_loc
.rx_buffers
= (phys_addr_t
)
1691 MVNETA_MAX_TXD
* sizeof(struct mvneta_tx_desc
) +
1692 MVNETA_MAX_RXD
* sizeof(struct mvneta_rx_desc
));
1695 pp
->base
= (void __iomem
*)pdata
->iobase
;
1697 /* Configure MBUS address windows */
1698 if (device_is_compatible(dev
, "marvell,armada-3700-neta"))
1699 mvneta_bypass_mbus_windows(pp
);
1701 mvneta_conf_mbus_windows(pp
);
1703 /* PHY interface is already decoded in mvneta_ofdata_to_platdata() */
1704 pp
->phy_interface
= pdata
->phy_interface
;
1706 /* fetch 'fixed-link' property from 'neta' node */
1707 fl_node
= fdt_subnode_offset(blob
, node
, "fixed-link");
1708 if (fl_node
!= -FDT_ERR_NOTFOUND
) {
1709 /* set phy_addr to invalid value for fixed link */
1710 pp
->phyaddr
= PHY_MAX_ADDR
+ 1;
1711 pp
->duplex
= fdtdec_get_bool(blob
, fl_node
, "full-duplex");
1712 pp
->speed
= fdtdec_get_int(blob
, fl_node
, "speed", 0);
1714 /* Now read phyaddr from DT */
1715 addr
= fdtdec_get_int(blob
, node
, "phy", 0);
1716 addr
= fdt_node_offset_by_phandle(blob
, addr
);
1717 pp
->phyaddr
= fdtdec_get_int(blob
, addr
, "reg", 0);
1722 printf("Failed to allocate MDIO bus\n");
1726 bus
->read
= mvneta_mdio_read
;
1727 bus
->write
= mvneta_mdio_write
;
1728 snprintf(bus
->name
, sizeof(bus
->name
), dev
->name
);
1729 bus
->priv
= (void *)pp
;
1732 ret
= mdio_register(bus
);
1736 return board_network_enable(bus
);
1739 static void mvneta_stop(struct udevice
*dev
)
1741 struct mvneta_port
*pp
= dev_get_priv(dev
);
1743 mvneta_port_down(pp
);
1744 mvneta_port_disable(pp
);
1747 static const struct eth_ops mvneta_ops
= {
1748 .start
= mvneta_start
,
1749 .send
= mvneta_send
,
1750 .recv
= mvneta_recv
,
1751 .stop
= mvneta_stop
,
1754 static int mvneta_ofdata_to_platdata(struct udevice
*dev
)
1756 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
1757 const char *phy_mode
;
1759 pdata
->iobase
= devfdt_get_addr(dev
);
1761 /* Get phy-mode / phy_interface from DT */
1762 pdata
->phy_interface
= -1;
1763 phy_mode
= fdt_getprop(gd
->fdt_blob
, dev_of_offset(dev
), "phy-mode",
1766 pdata
->phy_interface
= phy_get_interface_by_name(phy_mode
);
1767 if (pdata
->phy_interface
== -1) {
1768 debug("%s: Invalid PHY interface '%s'\n", __func__
, phy_mode
);
1775 static const struct udevice_id mvneta_ids
[] = {
1776 { .compatible
= "marvell,armada-370-neta" },
1777 { .compatible
= "marvell,armada-xp-neta" },
1778 { .compatible
= "marvell,armada-3700-neta" },
1782 U_BOOT_DRIVER(mvneta
) = {
1785 .of_match
= mvneta_ids
,
1786 .ofdata_to_platdata
= mvneta_ofdata_to_platdata
,
1787 .probe
= mvneta_probe
,
1789 .priv_auto_alloc_size
= sizeof(struct mvneta_port
),
1790 .platdata_auto_alloc_size
= sizeof(struct eth_pdata
),