2 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
4 * Copyright (C) 2014 Marvell
6 * Marcin Wojtas <mw@semihalf.com>
9 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
18 #include <dm/device-internal.h>
25 #include <linux/errno.h>
29 #include <asm/arch/cpu.h>
30 #include <asm/arch/soc.h>
31 #include <linux/compat.h>
32 #include <linux/mbus.h>
34 DECLARE_GLOBAL_DATA_PTR
;
36 /* Some linux -> U-Boot compatibility stuff */
37 #define netdev_err(dev, fmt, args...) \
39 #define netdev_warn(dev, fmt, args...) \
41 #define netdev_info(dev, fmt, args...) \
43 #define netdev_dbg(dev, fmt, args...) \
46 #define ETH_ALEN 6 /* Octets in one ethernet addr */
48 #define __verify_pcpu_ptr(ptr) \
50 const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL; \
54 #define VERIFY_PERCPU_PTR(__p) \
56 __verify_pcpu_ptr(__p); \
57 (typeof(*(__p)) __kernel __force *)(__p); \
60 #define per_cpu_ptr(ptr, cpu) ({ (void)(cpu); VERIFY_PERCPU_PTR(ptr); })
61 #define smp_processor_id() 0
62 #define num_present_cpus() 1
63 #define for_each_present_cpu(cpu) \
64 for ((cpu) = 0; (cpu) < 1; (cpu)++)
66 #define NET_SKB_PAD max(32, MVPP2_CPU_D_CACHE_LINE_SIZE)
68 #define CONFIG_NR_CPUS 1
69 #define ETH_HLEN ETHER_HDR_SIZE /* Total octets in header */
71 /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
72 #define WRAP (2 + ETH_HLEN + 4 + 32)
74 #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
76 #define MVPP2_SMI_TIMEOUT 10000
78 /* RX Fifo Registers */
79 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
80 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
81 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
82 #define MVPP2_RX_FIFO_INIT_REG 0x64
84 /* RX DMA Top Registers */
85 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
86 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
87 #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)
88 #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
89 #define MVPP2_POOL_BUF_SIZE_OFFSET 5
90 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
91 #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
92 #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
93 #define MVPP2_RXQ_POOL_SHORT_OFFS 20
94 #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000
95 #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000
96 #define MVPP2_RXQ_POOL_LONG_OFFS 24
97 #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000
98 #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000
99 #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
100 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
101 #define MVPP2_RXQ_DISABLE_MASK BIT(31)
103 /* Parser Registers */
104 #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
105 #define MVPP2_PRS_PORT_LU_MAX 0xf
106 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
107 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
108 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
109 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
110 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
111 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
112 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
113 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
114 #define MVPP2_PRS_TCAM_IDX_REG 0x1100
115 #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
116 #define MVPP2_PRS_TCAM_INV_MASK BIT(31)
117 #define MVPP2_PRS_SRAM_IDX_REG 0x1200
118 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
119 #define MVPP2_PRS_TCAM_CTRL_REG 0x1230
120 #define MVPP2_PRS_TCAM_EN_MASK BIT(0)
122 /* Classifier Registers */
123 #define MVPP2_CLS_MODE_REG 0x1800
124 #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
125 #define MVPP2_CLS_PORT_WAY_REG 0x1810
126 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))
127 #define MVPP2_CLS_LKP_INDEX_REG 0x1814
128 #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6
129 #define MVPP2_CLS_LKP_TBL_REG 0x1818
130 #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
131 #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)
132 #define MVPP2_CLS_FLOW_INDEX_REG 0x1820
133 #define MVPP2_CLS_FLOW_TBL0_REG 0x1824
134 #define MVPP2_CLS_FLOW_TBL1_REG 0x1828
135 #define MVPP2_CLS_FLOW_TBL2_REG 0x182c
136 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
137 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3
138 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
139 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
140 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
141 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))
143 /* Descriptor Manager Top Registers */
144 #define MVPP2_RXQ_NUM_REG 0x2040
145 #define MVPP2_RXQ_DESC_ADDR_REG 0x2044
146 #define MVPP22_DESC_ADDR_OFFS 8
147 #define MVPP2_RXQ_DESC_SIZE_REG 0x2048
148 #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
149 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
150 #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
151 #define MVPP2_RXQ_NUM_NEW_OFFSET 16
152 #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
153 #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
154 #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16
155 #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
156 #define MVPP2_RXQ_THRESH_REG 0x204c
157 #define MVPP2_OCCUPIED_THRESH_OFFSET 0
158 #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
159 #define MVPP2_RXQ_INDEX_REG 0x2050
160 #define MVPP2_TXQ_NUM_REG 0x2080
161 #define MVPP2_TXQ_DESC_ADDR_REG 0x2084
162 #define MVPP2_TXQ_DESC_SIZE_REG 0x2088
163 #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
164 #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
165 #define MVPP2_TXQ_THRESH_REG 0x2094
166 #define MVPP2_TRANSMITTED_THRESH_OFFSET 16
167 #define MVPP2_TRANSMITTED_THRESH_MASK 0x3fff0000
168 #define MVPP2_TXQ_INDEX_REG 0x2098
169 #define MVPP2_TXQ_PREF_BUF_REG 0x209c
170 #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
171 #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))
172 #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))
173 #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)
174 #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)
175 #define MVPP2_TXQ_PENDING_REG 0x20a0
176 #define MVPP2_TXQ_PENDING_MASK 0x3fff
177 #define MVPP2_TXQ_INT_STATUS_REG 0x20a4
178 #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
179 #define MVPP2_TRANSMITTED_COUNT_OFFSET 16
180 #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
181 #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
182 #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16
183 #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
184 #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
185 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
186 #define MVPP2_TXQ_RSVD_CLR_OFFSET 16
187 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
188 #define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8
189 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
190 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
191 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
192 #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
193 #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
195 /* MBUS bridge registers */
196 #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
197 #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
198 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
199 #define MVPP2_BASE_ADDR_ENABLE 0x4060
201 /* Interrupt Cause and Mask registers */
202 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
203 #define MVPP2_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq))
204 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
205 #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
206 #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
207 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
208 #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
209 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
210 #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
211 #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)
212 #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)
213 #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)
214 #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)
215 #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)
216 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
217 #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
218 #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
219 #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
220 #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
221 #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
223 /* Buffer Manager registers */
224 #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
225 #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
226 #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
227 #define MVPP2_BM_POOL_SIZE_MASK 0xfff0
228 #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
229 #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
230 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
231 #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
232 #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
233 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
234 #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
235 #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)
236 #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
237 #define MVPP2_BM_START_MASK BIT(0)
238 #define MVPP2_BM_STOP_MASK BIT(1)
239 #define MVPP2_BM_STATE_MASK BIT(4)
240 #define MVPP2_BM_LOW_THRESH_OFFS 8
241 #define MVPP2_BM_LOW_THRESH_MASK 0x7f00
242 #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \
243 MVPP2_BM_LOW_THRESH_OFFS)
244 #define MVPP2_BM_HIGH_THRESH_OFFS 16
245 #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
246 #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
247 MVPP2_BM_HIGH_THRESH_OFFS)
248 #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
249 #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
250 #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
251 #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)
252 #define MVPP2_BM_BPPE_FULL_MASK BIT(3)
253 #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)
254 #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
255 #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
256 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
257 #define MVPP2_BM_VIRT_ALLOC_REG 0x6440
258 #define MVPP2_BM_ADDR_HIGH_ALLOC 0x6444
259 #define MVPP2_BM_ADDR_HIGH_PHYS_MASK 0xff
260 #define MVPP2_BM_ADDR_HIGH_VIRT_MASK 0xff00
261 #define MVPP2_BM_ADDR_HIGH_VIRT_SHIFT 8
262 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
263 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
264 #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)
265 #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)
266 #define MVPP2_BM_VIRT_RLS_REG 0x64c0
267 #define MVPP21_BM_MC_RLS_REG 0x64c4
268 #define MVPP2_BM_MC_ID_MASK 0xfff
269 #define MVPP2_BM_FORCE_RELEASE_MASK BIT(12)
270 #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4
271 #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff
272 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
273 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
274 #define MVPP22_BM_MC_RLS_REG 0x64d4
276 /* TX Scheduler registers */
277 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
278 #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
279 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff
280 #define MVPP2_TXP_SCHED_DISQ_OFFSET 8
281 #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
282 #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
283 #define MVPP2_TXP_SCHED_MTU_REG 0x801c
284 #define MVPP2_TXP_MTU_MAX 0x7FFFF
285 #define MVPP2_TXP_SCHED_REFILL_REG 0x8020
286 #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
287 #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
288 #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)
289 #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
290 #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
291 #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
292 #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
293 #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
294 #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)
295 #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
296 #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
297 #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
298 #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
300 /* TX general registers */
301 #define MVPP2_TX_SNOOP_REG 0x8800
302 #define MVPP2_TX_PORT_FLUSH_REG 0x8810
303 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))
306 #define MVPP2_SRC_ADDR_MIDDLE 0x24
307 #define MVPP2_SRC_ADDR_HIGH 0x28
308 #define MVPP2_PHY_AN_CFG0_REG 0x34
309 #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
310 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
311 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
313 /* Per-port registers */
314 #define MVPP2_GMAC_CTRL_0_REG 0x0
315 #define MVPP2_GMAC_PORT_EN_MASK BIT(0)
316 #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
317 #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
318 #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
319 #define MVPP2_GMAC_CTRL_1_REG 0x4
320 #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
321 #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
322 #define MVPP2_GMAC_PCS_LB_EN_BIT 6
323 #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
324 #define MVPP2_GMAC_SA_LOW_OFFS 7
325 #define MVPP2_GMAC_CTRL_2_REG 0x8
326 #define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
327 #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
328 #define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
329 #define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
330 #define MVPP2_GMAC_AUTONEG_CONFIG 0xc
331 #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
332 #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
333 #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
334 #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
335 #define MVPP2_GMAC_AN_SPEED_EN BIT(7)
336 #define MVPP2_GMAC_FC_ADV_EN BIT(9)
337 #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
338 #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
339 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
340 #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
341 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
342 #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
343 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
345 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
347 /* Descriptor ring Macros */
348 #define MVPP2_QUEUE_NEXT_DESC(q, index) \
349 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
351 /* SMI: 0xc0054 -> offset 0x54 to lms_base */
352 #define MVPP2_SMI 0x0054
353 #define MVPP2_PHY_REG_MASK 0x1f
354 /* SMI register fields */
355 #define MVPP2_SMI_DATA_OFFS 0 /* Data */
356 #define MVPP2_SMI_DATA_MASK (0xffff << MVPP2_SMI_DATA_OFFS)
357 #define MVPP2_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
358 #define MVPP2_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/
359 #define MVPP2_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
360 #define MVPP2_SMI_OPCODE_READ (1 << MVPP2_SMI_OPCODE_OFFS)
361 #define MVPP2_SMI_READ_VALID (1 << 27) /* Read Valid */
362 #define MVPP2_SMI_BUSY (1 << 28) /* Busy */
364 #define MVPP2_PHY_ADDR_MASK 0x1f
365 #define MVPP2_PHY_REG_MASK 0x1f
367 /* Various constants */
370 #define MVPP2_TXDONE_COAL_PKTS_THRESH 15
371 #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL
372 #define MVPP2_RX_COAL_PKTS 32
373 #define MVPP2_RX_COAL_USEC 100
375 /* The two bytes Marvell header. Either contains a special value used
376 * by Marvell switches when a specific hardware mode is enabled (not
377 * supported by this driver) or is filled automatically by zeroes on
378 * the RX side. Those two bytes being at the front of the Ethernet
379 * header, they allow to have the IP header aligned on a 4 bytes
380 * boundary automatically: the hardware skips those two bytes on its
383 #define MVPP2_MH_SIZE 2
384 #define MVPP2_ETH_TYPE_LEN 2
385 #define MVPP2_PPPOE_HDR_SIZE 8
386 #define MVPP2_VLAN_TAG_LEN 4
388 /* Lbtd 802.3 type */
389 #define MVPP2_IP_LBDT_TYPE 0xfffa
391 #define MVPP2_CPU_D_CACHE_LINE_SIZE 32
392 #define MVPP2_TX_CSUM_MAX_SIZE 9800
394 /* Timeout constants */
395 #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000
396 #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000
398 #define MVPP2_TX_MTU_MAX 0x7ffff
400 /* Maximum number of T-CONTs of PON port */
401 #define MVPP2_MAX_TCONT 16
403 /* Maximum number of supported ports */
404 #define MVPP2_MAX_PORTS 4
406 /* Maximum number of TXQs used by single port */
407 #define MVPP2_MAX_TXQ 8
409 /* Maximum number of RXQs used by single port */
410 #define MVPP2_MAX_RXQ 8
412 /* Default number of TXQs in use */
413 #define MVPP2_DEFAULT_TXQ 1
415 /* Dfault number of RXQs in use */
416 #define MVPP2_DEFAULT_RXQ 1
417 #define CONFIG_MV_ETH_RXQ 8 /* increment by 8 */
419 /* Total number of RXQs available to all ports */
420 #define MVPP2_RXQ_TOTAL_NUM (MVPP2_MAX_PORTS * MVPP2_MAX_RXQ)
422 /* Max number of Rx descriptors */
423 #define MVPP2_MAX_RXD 16
425 /* Max number of Tx descriptors */
426 #define MVPP2_MAX_TXD 16
428 /* Amount of Tx descriptors that can be reserved at once by CPU */
429 #define MVPP2_CPU_DESC_CHUNK 64
431 /* Max number of Tx descriptors in each aggregated queue */
432 #define MVPP2_AGGR_TXQ_SIZE 256
434 /* Descriptor aligned size */
435 #define MVPP2_DESC_ALIGNED_SIZE 32
437 /* Descriptor alignment mask */
438 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
440 /* RX FIFO constants */
441 #define MVPP2_RX_FIFO_PORT_DATA_SIZE 0x2000
442 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE 0x80
443 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
445 /* RX buffer constants */
446 #define MVPP2_SKB_SHINFO_SIZE \
449 #define MVPP2_RX_PKT_SIZE(mtu) \
450 ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
451 ETH_HLEN + ETH_FCS_LEN, MVPP2_CPU_D_CACHE_LINE_SIZE)
453 #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
454 #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
455 #define MVPP2_RX_MAX_PKT_SIZE(total_size) \
456 ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
458 #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
460 /* IPv6 max L3 address size */
461 #define MVPP2_MAX_L3_ADDR_SIZE 16
464 #define MVPP2_F_LOOPBACK BIT(0)
466 /* Marvell tag types */
467 enum mvpp2_tag_type
{
468 MVPP2_TAG_TYPE_NONE
= 0,
469 MVPP2_TAG_TYPE_MH
= 1,
470 MVPP2_TAG_TYPE_DSA
= 2,
471 MVPP2_TAG_TYPE_EDSA
= 3,
472 MVPP2_TAG_TYPE_VLAN
= 4,
473 MVPP2_TAG_TYPE_LAST
= 5
476 /* Parser constants */
477 #define MVPP2_PRS_TCAM_SRAM_SIZE 256
478 #define MVPP2_PRS_TCAM_WORDS 6
479 #define MVPP2_PRS_SRAM_WORDS 4
480 #define MVPP2_PRS_FLOW_ID_SIZE 64
481 #define MVPP2_PRS_FLOW_ID_MASK 0x3f
482 #define MVPP2_PRS_TCAM_ENTRY_INVALID 1
483 #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
484 #define MVPP2_PRS_IPV4_HEAD 0x40
485 #define MVPP2_PRS_IPV4_HEAD_MASK 0xf0
486 #define MVPP2_PRS_IPV4_MC 0xe0
487 #define MVPP2_PRS_IPV4_MC_MASK 0xf0
488 #define MVPP2_PRS_IPV4_BC_MASK 0xff
489 #define MVPP2_PRS_IPV4_IHL 0x5
490 #define MVPP2_PRS_IPV4_IHL_MASK 0xf
491 #define MVPP2_PRS_IPV6_MC 0xff
492 #define MVPP2_PRS_IPV6_MC_MASK 0xff
493 #define MVPP2_PRS_IPV6_HOP_MASK 0xff
494 #define MVPP2_PRS_TCAM_PROTO_MASK 0xff
495 #define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f
496 #define MVPP2_PRS_DBL_VLANS_MAX 100
499 * - lookup ID - 4 bits
501 * - additional information - 1 byte
502 * - header data - 8 bytes
503 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
505 #define MVPP2_PRS_AI_BITS 8
506 #define MVPP2_PRS_PORT_MASK 0xff
507 #define MVPP2_PRS_LU_MASK 0xf
508 #define MVPP2_PRS_TCAM_DATA_BYTE(offs) \
509 (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
510 #define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \
511 (((offs) * 2) - ((offs) % 2) + 2)
512 #define MVPP2_PRS_TCAM_AI_BYTE 16
513 #define MVPP2_PRS_TCAM_PORT_BYTE 17
514 #define MVPP2_PRS_TCAM_LU_BYTE 20
515 #define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2)
516 #define MVPP2_PRS_TCAM_INV_WORD 5
517 /* Tcam entries ID */
518 #define MVPP2_PE_DROP_ALL 0
519 #define MVPP2_PE_FIRST_FREE_TID 1
520 #define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
521 #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
522 #define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
523 #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
524 #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
525 #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
526 #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
527 #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
528 #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
529 #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
530 #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
531 #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
532 #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
533 #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
534 #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
535 #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
536 #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
537 #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
538 #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
539 #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
540 #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
541 #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
542 #define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
543 #define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
544 #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
547 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
549 #define MVPP2_PRS_SRAM_RI_OFFS 0
550 #define MVPP2_PRS_SRAM_RI_WORD 0
551 #define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32
552 #define MVPP2_PRS_SRAM_RI_CTRL_WORD 1
553 #define MVPP2_PRS_SRAM_RI_CTRL_BITS 32
554 #define MVPP2_PRS_SRAM_SHIFT_OFFS 64
555 #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72
556 #define MVPP2_PRS_SRAM_UDF_OFFS 73
557 #define MVPP2_PRS_SRAM_UDF_BITS 8
558 #define MVPP2_PRS_SRAM_UDF_MASK 0xff
559 #define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81
560 #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82
561 #define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7
562 #define MVPP2_PRS_SRAM_UDF_TYPE_L3 1
563 #define MVPP2_PRS_SRAM_UDF_TYPE_L4 4
564 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85
565 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3
566 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1
567 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2
568 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3
569 #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87
570 #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2
571 #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3
572 #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0
573 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2
574 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3
575 #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89
576 #define MVPP2_PRS_SRAM_AI_OFFS 90
577 #define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98
578 #define MVPP2_PRS_SRAM_AI_CTRL_BITS 8
579 #define MVPP2_PRS_SRAM_AI_MASK 0xff
580 #define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106
581 #define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf
582 #define MVPP2_PRS_SRAM_LU_DONE_BIT 110
583 #define MVPP2_PRS_SRAM_LU_GEN_BIT 111
585 /* Sram result info bits assignment */
586 #define MVPP2_PRS_RI_MAC_ME_MASK 0x1
587 #define MVPP2_PRS_RI_DSA_MASK 0x2
588 #define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3))
589 #define MVPP2_PRS_RI_VLAN_NONE 0x0
590 #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
591 #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
592 #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
593 #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
594 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
595 #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10))
596 #define MVPP2_PRS_RI_L2_UCAST 0x0
597 #define MVPP2_PRS_RI_L2_MCAST BIT(9)
598 #define MVPP2_PRS_RI_L2_BCAST BIT(10)
599 #define MVPP2_PRS_RI_PPPOE_MASK 0x800
600 #define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14))
601 #define MVPP2_PRS_RI_L3_UN 0x0
602 #define MVPP2_PRS_RI_L3_IP4 BIT(12)
603 #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
604 #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
605 #define MVPP2_PRS_RI_L3_IP6 BIT(14)
606 #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
607 #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
608 #define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16))
609 #define MVPP2_PRS_RI_L3_UCAST 0x0
610 #define MVPP2_PRS_RI_L3_MCAST BIT(15)
611 #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
612 #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
613 #define MVPP2_PRS_RI_UDF3_MASK 0x300000
614 #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
615 #define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
616 #define MVPP2_PRS_RI_L4_TCP BIT(22)
617 #define MVPP2_PRS_RI_L4_UDP BIT(23)
618 #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
619 #define MVPP2_PRS_RI_UDF7_MASK 0x60000000
620 #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
621 #define MVPP2_PRS_RI_DROP_MASK 0x80000000
623 /* Sram additional info bits assignment */
624 #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
625 #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
626 #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
627 #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
628 #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
629 #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
630 #define MVPP2_PRS_SINGLE_VLAN_AI 0
631 #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
634 #define MVPP2_PRS_TAGGED true
635 #define MVPP2_PRS_UNTAGGED false
636 #define MVPP2_PRS_EDSA true
637 #define MVPP2_PRS_DSA false
639 /* MAC entries, shadow udf */
641 MVPP2_PRS_UDF_MAC_DEF
,
642 MVPP2_PRS_UDF_MAC_RANGE
,
643 MVPP2_PRS_UDF_L2_DEF
,
644 MVPP2_PRS_UDF_L2_DEF_COPY
,
645 MVPP2_PRS_UDF_L2_USER
,
649 enum mvpp2_prs_lookup
{
663 enum mvpp2_prs_l3_cast
{
664 MVPP2_PRS_L3_UNI_CAST
,
665 MVPP2_PRS_L3_MULTI_CAST
,
666 MVPP2_PRS_L3_BROAD_CAST
669 /* Classifier constants */
670 #define MVPP2_CLS_FLOWS_TBL_SIZE 512
671 #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3
672 #define MVPP2_CLS_LKP_TBL_SIZE 64
675 #define MVPP2_BM_POOLS_NUM 1
676 #define MVPP2_BM_LONG_BUF_NUM 16
677 #define MVPP2_BM_SHORT_BUF_NUM 16
678 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
679 #define MVPP2_BM_POOL_PTR_ALIGN 128
680 #define MVPP2_BM_SWF_LONG_POOL(port) 0
682 /* BM cookie (32 bits) definition */
683 #define MVPP2_BM_COOKIE_POOL_OFFS 8
684 #define MVPP2_BM_COOKIE_CPU_OFFS 24
686 /* BM short pool packet size
687 * These value assure that for SWF the total number
688 * of bytes allocated for each buffer will be 512
690 #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512)
700 /* Shared Packet Processor resources */
702 /* Shared registers' base addresses */
704 void __iomem
*lms_base
;
706 /* List of pointers to port structures */
707 struct mvpp2_port
**port_list
;
709 /* Aggregated TXQs */
710 struct mvpp2_tx_queue
*aggr_txqs
;
713 struct mvpp2_bm_pool
*bm_pools
;
715 /* PRS shadow table */
716 struct mvpp2_prs_shadow
*prs_shadow
;
717 /* PRS auxiliary table for double vlan entries control */
718 bool *prs_double_vlans
;
724 enum { MVPP21
, MVPP22
} hw_version
;
729 struct mvpp2_pcpu_stats
{
743 /* Per-port registers' base address */
746 struct mvpp2_rx_queue
**rxqs
;
747 struct mvpp2_tx_queue
**txqs
;
751 u32 pending_cause_rx
;
753 /* Per-CPU port control */
754 struct mvpp2_port_pcpu __percpu
*pcpu
;
761 struct mvpp2_pcpu_stats __percpu
*stats
;
763 struct phy_device
*phy_dev
;
764 phy_interface_t phy_interface
;
772 struct mvpp2_bm_pool
*pool_long
;
773 struct mvpp2_bm_pool
*pool_short
;
775 /* Index of first port's physical RXQ */
778 u8 dev_addr
[ETH_ALEN
];
781 /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
782 * layout of the transmit and reception DMA descriptors, and their
783 * layout is therefore defined by the hardware design
786 #define MVPP2_TXD_L3_OFF_SHIFT 0
787 #define MVPP2_TXD_IP_HLEN_SHIFT 8
788 #define MVPP2_TXD_L4_CSUM_FRAG BIT(13)
789 #define MVPP2_TXD_L4_CSUM_NOT BIT(14)
790 #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)
791 #define MVPP2_TXD_PADDING_DISABLE BIT(23)
792 #define MVPP2_TXD_L4_UDP BIT(24)
793 #define MVPP2_TXD_L3_IP6 BIT(26)
794 #define MVPP2_TXD_L_DESC BIT(28)
795 #define MVPP2_TXD_F_DESC BIT(29)
797 #define MVPP2_RXD_ERR_SUMMARY BIT(15)
798 #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))
799 #define MVPP2_RXD_ERR_CRC 0x0
800 #define MVPP2_RXD_ERR_OVERRUN BIT(13)
801 #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))
802 #define MVPP2_RXD_BM_POOL_ID_OFFS 16
803 #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))
804 #define MVPP2_RXD_HWF_SYNC BIT(21)
805 #define MVPP2_RXD_L4_CSUM_OK BIT(22)
806 #define MVPP2_RXD_IP4_HEADER_ERR BIT(24)
807 #define MVPP2_RXD_L4_TCP BIT(25)
808 #define MVPP2_RXD_L4_UDP BIT(26)
809 #define MVPP2_RXD_L3_IP4 BIT(28)
810 #define MVPP2_RXD_L3_IP6 BIT(30)
811 #define MVPP2_RXD_BUF_HDR BIT(31)
813 /* HW TX descriptor for PPv2.1 */
814 struct mvpp21_tx_desc
{
815 u32 command
; /* Options used by HW for packet transmitting.*/
816 u8 packet_offset
; /* the offset from the buffer beginning */
817 u8 phys_txq
; /* destination queue ID */
818 u16 data_size
; /* data size of transmitted packet in bytes */
819 u32 buf_dma_addr
; /* physical addr of transmitted buffer */
820 u32 buf_cookie
; /* cookie for access to TX buffer in tx path */
821 u32 reserved1
[3]; /* hw_cmd (for future use, BM, PON, PNC) */
822 u32 reserved2
; /* reserved (for future use) */
825 /* HW RX descriptor for PPv2.1 */
826 struct mvpp21_rx_desc
{
827 u32 status
; /* info about received packet */
828 u16 reserved1
; /* parser_info (for future use, PnC) */
829 u16 data_size
; /* size of received packet in bytes */
830 u32 buf_dma_addr
; /* physical address of the buffer */
831 u32 buf_cookie
; /* cookie for access to RX buffer in rx path */
832 u16 reserved2
; /* gem_port_id (for future use, PON) */
833 u16 reserved3
; /* csum_l4 (for future use, PnC) */
834 u8 reserved4
; /* bm_qset (for future use, BM) */
836 u16 reserved6
; /* classify_info (for future use, PnC) */
837 u32 reserved7
; /* flow_id (for future use, PnC) */
841 /* HW TX descriptor for PPv2.2 */
842 struct mvpp22_tx_desc
{
848 u64 buf_dma_addr_ptp
;
852 /* HW RX descriptor for PPv2.2 */
853 struct mvpp22_rx_desc
{
859 u64 buf_dma_addr_key_hash
;
863 /* Opaque type used by the driver to manipulate the HW TX and RX
866 struct mvpp2_tx_desc
{
868 struct mvpp21_tx_desc pp21
;
869 struct mvpp22_tx_desc pp22
;
873 struct mvpp2_rx_desc
{
875 struct mvpp21_rx_desc pp21
;
876 struct mvpp22_rx_desc pp22
;
880 /* Per-CPU Tx queue control */
881 struct mvpp2_txq_pcpu
{
884 /* Number of Tx DMA descriptors in the descriptor ring */
887 /* Number of currently used Tx DMA descriptor in the
892 /* Number of Tx DMA descriptors reserved for each CPU */
895 /* Index of last TX DMA descriptor that was inserted */
898 /* Index of the TX DMA descriptor to be cleaned up */
902 struct mvpp2_tx_queue
{
903 /* Physical number of this Tx queue */
906 /* Logical number of this Tx queue */
909 /* Number of Tx DMA descriptors in the descriptor ring */
912 /* Number of currently used Tx DMA descriptor in the descriptor ring */
915 /* Per-CPU control of physical Tx queues */
916 struct mvpp2_txq_pcpu __percpu
*pcpu
;
920 /* Virtual address of thex Tx DMA descriptors array */
921 struct mvpp2_tx_desc
*descs
;
923 /* DMA address of the Tx DMA descriptors array */
924 dma_addr_t descs_dma
;
926 /* Index of the last Tx DMA descriptor */
929 /* Index of the next Tx DMA descriptor to process */
930 int next_desc_to_proc
;
933 struct mvpp2_rx_queue
{
934 /* RX queue number, in the range 0-31 for physical RXQs */
937 /* Num of rx descriptors in the rx descriptor ring */
943 /* Virtual address of the RX DMA descriptors array */
944 struct mvpp2_rx_desc
*descs
;
946 /* DMA address of the RX DMA descriptors array */
947 dma_addr_t descs_dma
;
949 /* Index of the last RX DMA descriptor */
952 /* Index of the next RX DMA descriptor to process */
953 int next_desc_to_proc
;
955 /* ID of port to which physical RXQ is mapped */
958 /* Port's logic RXQ number to which physical RXQ is mapped */
962 union mvpp2_prs_tcam_entry
{
963 u32 word
[MVPP2_PRS_TCAM_WORDS
];
964 u8 byte
[MVPP2_PRS_TCAM_WORDS
* 4];
967 union mvpp2_prs_sram_entry
{
968 u32 word
[MVPP2_PRS_SRAM_WORDS
];
969 u8 byte
[MVPP2_PRS_SRAM_WORDS
* 4];
972 struct mvpp2_prs_entry
{
974 union mvpp2_prs_tcam_entry tcam
;
975 union mvpp2_prs_sram_entry sram
;
978 struct mvpp2_prs_shadow
{
985 /* User defined offset */
993 struct mvpp2_cls_flow_entry
{
995 u32 data
[MVPP2_CLS_FLOWS_TBL_DATA_WORDS
];
998 struct mvpp2_cls_lookup_entry
{
1004 struct mvpp2_bm_pool
{
1005 /* Pool number in the range 0-7 */
1007 enum mvpp2_bm_type type
;
1009 /* Buffer Pointers Pool External (BPPE) size */
1011 /* Number of buffers for this pool */
1013 /* Pool buffer size */
1018 /* BPPE virtual base address */
1019 unsigned long *virt_addr
;
1020 /* BPPE DMA base address */
1021 dma_addr_t dma_addr
;
1023 /* Ports using BM pool */
1026 /* Occupied buffers indicator */
1030 /* Static declaractions */
1032 /* Number of RXQs used by single port */
1033 static int rxq_number
= MVPP2_DEFAULT_RXQ
;
1034 /* Number of TXQs used by single port */
1035 static int txq_number
= MVPP2_DEFAULT_TXQ
;
1037 #define MVPP2_DRIVER_NAME "mvpp2"
1038 #define MVPP2_DRIVER_VERSION "1.0"
1041 * U-Boot internal data, mostly uncached buffers for descriptors and data
1043 struct buffer_location
{
1044 struct mvpp2_tx_desc
*aggr_tx_descs
;
1045 struct mvpp2_tx_desc
*tx_descs
;
1046 struct mvpp2_rx_desc
*rx_descs
;
1047 unsigned long *bm_pool
[MVPP2_BM_POOLS_NUM
];
1048 unsigned long *rx_buffer
[MVPP2_BM_LONG_BUF_NUM
];
1053 * All 4 interfaces use the same global buffer, since only one interface
1054 * can be enabled at once
1056 static struct buffer_location buffer_loc
;
1059 * Page table entries are set to 1MB, or multiples of 1MB
1060 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
1062 #define BD_SPACE (1 << 20)
1064 /* Utility/helper methods */
1066 static void mvpp2_write(struct mvpp2
*priv
, u32 offset
, u32 data
)
1068 writel(data
, priv
->base
+ offset
);
1071 static u32
mvpp2_read(struct mvpp2
*priv
, u32 offset
)
1073 return readl(priv
->base
+ offset
);
1076 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port
*port
,
1077 struct mvpp2_tx_desc
*tx_desc
,
1078 dma_addr_t dma_addr
)
1080 if (port
->priv
->hw_version
== MVPP21
) {
1081 tx_desc
->pp21
.buf_dma_addr
= dma_addr
;
1083 u64 val
= (u64
)dma_addr
;
1085 tx_desc
->pp22
.buf_dma_addr_ptp
&= ~GENMASK_ULL(40, 0);
1086 tx_desc
->pp22
.buf_dma_addr_ptp
|= val
;
1090 static void mvpp2_txdesc_size_set(struct mvpp2_port
*port
,
1091 struct mvpp2_tx_desc
*tx_desc
,
1094 if (port
->priv
->hw_version
== MVPP21
)
1095 tx_desc
->pp21
.data_size
= size
;
1097 tx_desc
->pp22
.data_size
= size
;
1100 static void mvpp2_txdesc_txq_set(struct mvpp2_port
*port
,
1101 struct mvpp2_tx_desc
*tx_desc
,
1104 if (port
->priv
->hw_version
== MVPP21
)
1105 tx_desc
->pp21
.phys_txq
= txq
;
1107 tx_desc
->pp22
.phys_txq
= txq
;
1110 static void mvpp2_txdesc_cmd_set(struct mvpp2_port
*port
,
1111 struct mvpp2_tx_desc
*tx_desc
,
1112 unsigned int command
)
1114 if (port
->priv
->hw_version
== MVPP21
)
1115 tx_desc
->pp21
.command
= command
;
1117 tx_desc
->pp22
.command
= command
;
1120 static void mvpp2_txdesc_offset_set(struct mvpp2_port
*port
,
1121 struct mvpp2_tx_desc
*tx_desc
,
1122 unsigned int offset
)
1124 if (port
->priv
->hw_version
== MVPP21
)
1125 tx_desc
->pp21
.packet_offset
= offset
;
1127 tx_desc
->pp22
.packet_offset
= offset
;
1130 static dma_addr_t
mvpp2_rxdesc_dma_addr_get(struct mvpp2_port
*port
,
1131 struct mvpp2_rx_desc
*rx_desc
)
1133 if (port
->priv
->hw_version
== MVPP21
)
1134 return rx_desc
->pp21
.buf_dma_addr
;
1136 return rx_desc
->pp22
.buf_dma_addr_key_hash
& GENMASK_ULL(40, 0);
1139 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port
*port
,
1140 struct mvpp2_rx_desc
*rx_desc
)
1142 if (port
->priv
->hw_version
== MVPP21
)
1143 return rx_desc
->pp21
.buf_cookie
;
1145 return rx_desc
->pp22
.buf_cookie_misc
& GENMASK_ULL(40, 0);
1148 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port
*port
,
1149 struct mvpp2_rx_desc
*rx_desc
)
1151 if (port
->priv
->hw_version
== MVPP21
)
1152 return rx_desc
->pp21
.data_size
;
1154 return rx_desc
->pp22
.data_size
;
1157 static u32
mvpp2_rxdesc_status_get(struct mvpp2_port
*port
,
1158 struct mvpp2_rx_desc
*rx_desc
)
1160 if (port
->priv
->hw_version
== MVPP21
)
1161 return rx_desc
->pp21
.status
;
1163 return rx_desc
->pp22
.status
;
1166 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu
*txq_pcpu
)
1168 txq_pcpu
->txq_get_index
++;
1169 if (txq_pcpu
->txq_get_index
== txq_pcpu
->size
)
1170 txq_pcpu
->txq_get_index
= 0;
1173 /* Get number of physical egress port */
1174 static inline int mvpp2_egress_port(struct mvpp2_port
*port
)
1176 return MVPP2_MAX_TCONT
+ port
->id
;
1179 /* Get number of physical TXQ */
1180 static inline int mvpp2_txq_phys(int port
, int txq
)
1182 return (MVPP2_MAX_TCONT
+ port
) * MVPP2_MAX_TXQ
+ txq
;
1185 /* Parser configuration routines */
1187 /* Update parser tcam and sram hw entries */
1188 static int mvpp2_prs_hw_write(struct mvpp2
*priv
, struct mvpp2_prs_entry
*pe
)
1192 if (pe
->index
> MVPP2_PRS_TCAM_SRAM_SIZE
- 1)
1195 /* Clear entry invalidation bit */
1196 pe
->tcam
.word
[MVPP2_PRS_TCAM_INV_WORD
] &= ~MVPP2_PRS_TCAM_INV_MASK
;
1198 /* Write tcam index - indirect access */
1199 mvpp2_write(priv
, MVPP2_PRS_TCAM_IDX_REG
, pe
->index
);
1200 for (i
= 0; i
< MVPP2_PRS_TCAM_WORDS
; i
++)
1201 mvpp2_write(priv
, MVPP2_PRS_TCAM_DATA_REG(i
), pe
->tcam
.word
[i
]);
1203 /* Write sram index - indirect access */
1204 mvpp2_write(priv
, MVPP2_PRS_SRAM_IDX_REG
, pe
->index
);
1205 for (i
= 0; i
< MVPP2_PRS_SRAM_WORDS
; i
++)
1206 mvpp2_write(priv
, MVPP2_PRS_SRAM_DATA_REG(i
), pe
->sram
.word
[i
]);
1211 /* Read tcam entry from hw */
1212 static int mvpp2_prs_hw_read(struct mvpp2
*priv
, struct mvpp2_prs_entry
*pe
)
1216 if (pe
->index
> MVPP2_PRS_TCAM_SRAM_SIZE
- 1)
1219 /* Write tcam index - indirect access */
1220 mvpp2_write(priv
, MVPP2_PRS_TCAM_IDX_REG
, pe
->index
);
1222 pe
->tcam
.word
[MVPP2_PRS_TCAM_INV_WORD
] = mvpp2_read(priv
,
1223 MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD
));
1224 if (pe
->tcam
.word
[MVPP2_PRS_TCAM_INV_WORD
] & MVPP2_PRS_TCAM_INV_MASK
)
1225 return MVPP2_PRS_TCAM_ENTRY_INVALID
;
1227 for (i
= 0; i
< MVPP2_PRS_TCAM_WORDS
; i
++)
1228 pe
->tcam
.word
[i
] = mvpp2_read(priv
, MVPP2_PRS_TCAM_DATA_REG(i
));
1230 /* Write sram index - indirect access */
1231 mvpp2_write(priv
, MVPP2_PRS_SRAM_IDX_REG
, pe
->index
);
1232 for (i
= 0; i
< MVPP2_PRS_SRAM_WORDS
; i
++)
1233 pe
->sram
.word
[i
] = mvpp2_read(priv
, MVPP2_PRS_SRAM_DATA_REG(i
));
1238 /* Invalidate tcam hw entry */
1239 static void mvpp2_prs_hw_inv(struct mvpp2
*priv
, int index
)
1241 /* Write index - indirect access */
1242 mvpp2_write(priv
, MVPP2_PRS_TCAM_IDX_REG
, index
);
1243 mvpp2_write(priv
, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD
),
1244 MVPP2_PRS_TCAM_INV_MASK
);
1247 /* Enable shadow table entry and set its lookup ID */
1248 static void mvpp2_prs_shadow_set(struct mvpp2
*priv
, int index
, int lu
)
1250 priv
->prs_shadow
[index
].valid
= true;
1251 priv
->prs_shadow
[index
].lu
= lu
;
1254 /* Update ri fields in shadow table entry */
1255 static void mvpp2_prs_shadow_ri_set(struct mvpp2
*priv
, int index
,
1256 unsigned int ri
, unsigned int ri_mask
)
1258 priv
->prs_shadow
[index
].ri_mask
= ri_mask
;
1259 priv
->prs_shadow
[index
].ri
= ri
;
1262 /* Update lookup field in tcam sw entry */
1263 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry
*pe
, unsigned int lu
)
1265 int enable_off
= MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE
);
1267 pe
->tcam
.byte
[MVPP2_PRS_TCAM_LU_BYTE
] = lu
;
1268 pe
->tcam
.byte
[enable_off
] = MVPP2_PRS_LU_MASK
;
1271 /* Update mask for single port in tcam sw entry */
1272 static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry
*pe
,
1273 unsigned int port
, bool add
)
1275 int enable_off
= MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE
);
1278 pe
->tcam
.byte
[enable_off
] &= ~(1 << port
);
1280 pe
->tcam
.byte
[enable_off
] |= 1 << port
;
1283 /* Update port map in tcam sw entry */
1284 static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry
*pe
,
1287 unsigned char port_mask
= MVPP2_PRS_PORT_MASK
;
1288 int enable_off
= MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE
);
1290 pe
->tcam
.byte
[MVPP2_PRS_TCAM_PORT_BYTE
] = 0;
1291 pe
->tcam
.byte
[enable_off
] &= ~port_mask
;
1292 pe
->tcam
.byte
[enable_off
] |= ~ports
& MVPP2_PRS_PORT_MASK
;
1295 /* Obtain port map from tcam sw entry */
1296 static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry
*pe
)
1298 int enable_off
= MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE
);
1300 return ~(pe
->tcam
.byte
[enable_off
]) & MVPP2_PRS_PORT_MASK
;
1303 /* Set byte of data and its enable bits in tcam sw entry */
1304 static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry
*pe
,
1305 unsigned int offs
, unsigned char byte
,
1306 unsigned char enable
)
1308 pe
->tcam
.byte
[MVPP2_PRS_TCAM_DATA_BYTE(offs
)] = byte
;
1309 pe
->tcam
.byte
[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs
)] = enable
;
1312 /* Get byte of data and its enable bits from tcam sw entry */
1313 static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry
*pe
,
1314 unsigned int offs
, unsigned char *byte
,
1315 unsigned char *enable
)
1317 *byte
= pe
->tcam
.byte
[MVPP2_PRS_TCAM_DATA_BYTE(offs
)];
1318 *enable
= pe
->tcam
.byte
[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs
)];
1321 /* Set ethertype in tcam sw entry */
1322 static void mvpp2_prs_match_etype(struct mvpp2_prs_entry
*pe
, int offset
,
1323 unsigned short ethertype
)
1325 mvpp2_prs_tcam_data_byte_set(pe
, offset
+ 0, ethertype
>> 8, 0xff);
1326 mvpp2_prs_tcam_data_byte_set(pe
, offset
+ 1, ethertype
& 0xff, 0xff);
1329 /* Set bits in sram sw entry */
1330 static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry
*pe
, int bit_num
,
1333 pe
->sram
.byte
[MVPP2_BIT_TO_BYTE(bit_num
)] |= (val
<< (bit_num
% 8));
1336 /* Clear bits in sram sw entry */
1337 static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry
*pe
, int bit_num
,
1340 pe
->sram
.byte
[MVPP2_BIT_TO_BYTE(bit_num
)] &= ~(val
<< (bit_num
% 8));
1343 /* Update ri bits in sram sw entry */
1344 static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry
*pe
,
1345 unsigned int bits
, unsigned int mask
)
1349 for (i
= 0; i
< MVPP2_PRS_SRAM_RI_CTRL_BITS
; i
++) {
1350 int ri_off
= MVPP2_PRS_SRAM_RI_OFFS
;
1352 if (!(mask
& BIT(i
)))
1356 mvpp2_prs_sram_bits_set(pe
, ri_off
+ i
, 1);
1358 mvpp2_prs_sram_bits_clear(pe
, ri_off
+ i
, 1);
1360 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_RI_CTRL_OFFS
+ i
, 1);
1364 /* Update ai bits in sram sw entry */
1365 static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry
*pe
,
1366 unsigned int bits
, unsigned int mask
)
1369 int ai_off
= MVPP2_PRS_SRAM_AI_OFFS
;
1371 for (i
= 0; i
< MVPP2_PRS_SRAM_AI_CTRL_BITS
; i
++) {
1373 if (!(mask
& BIT(i
)))
1377 mvpp2_prs_sram_bits_set(pe
, ai_off
+ i
, 1);
1379 mvpp2_prs_sram_bits_clear(pe
, ai_off
+ i
, 1);
1381 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_AI_CTRL_OFFS
+ i
, 1);
1385 /* Read ai bits from sram sw entry */
1386 static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry
*pe
)
1389 int ai_off
= MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS
);
1390 int ai_en_off
= ai_off
+ 1;
1391 int ai_shift
= MVPP2_PRS_SRAM_AI_OFFS
% 8;
1393 bits
= (pe
->sram
.byte
[ai_off
] >> ai_shift
) |
1394 (pe
->sram
.byte
[ai_en_off
] << (8 - ai_shift
));
1399 /* In sram sw entry set lookup ID field of the tcam key to be used in the next
1402 static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry
*pe
,
1405 int sram_next_off
= MVPP2_PRS_SRAM_NEXT_LU_OFFS
;
1407 mvpp2_prs_sram_bits_clear(pe
, sram_next_off
,
1408 MVPP2_PRS_SRAM_NEXT_LU_MASK
);
1409 mvpp2_prs_sram_bits_set(pe
, sram_next_off
, lu
);
1412 /* In the sram sw entry set sign and value of the next lookup offset
1413 * and the offset value generated to the classifier
1415 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry
*pe
, int shift
,
1420 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT
, 1);
1423 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT
, 1);
1427 pe
->sram
.byte
[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS
)] =
1428 (unsigned char)shift
;
1430 /* Reset and set operation */
1431 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS
,
1432 MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK
);
1433 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS
, op
);
1435 /* Set base offset as current */
1436 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS
, 1);
1439 /* In the sram sw entry set sign and value of the user defined offset
1440 * generated to the classifier
1442 static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry
*pe
,
1443 unsigned int type
, int offset
,
1448 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_UDF_SIGN_BIT
, 1);
1449 offset
= 0 - offset
;
1451 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_UDF_SIGN_BIT
, 1);
1455 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_UDF_OFFS
,
1456 MVPP2_PRS_SRAM_UDF_MASK
);
1457 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_UDF_OFFS
, offset
);
1458 pe
->sram
.byte
[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS
+
1459 MVPP2_PRS_SRAM_UDF_BITS
)] &=
1460 ~(MVPP2_PRS_SRAM_UDF_MASK
>> (8 - (MVPP2_PRS_SRAM_UDF_OFFS
% 8)));
1461 pe
->sram
.byte
[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS
+
1462 MVPP2_PRS_SRAM_UDF_BITS
)] |=
1463 (offset
>> (8 - (MVPP2_PRS_SRAM_UDF_OFFS
% 8)));
1465 /* Set offset type */
1466 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_UDF_TYPE_OFFS
,
1467 MVPP2_PRS_SRAM_UDF_TYPE_MASK
);
1468 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_UDF_TYPE_OFFS
, type
);
1470 /* Set offset operation */
1471 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS
,
1472 MVPP2_PRS_SRAM_OP_SEL_UDF_MASK
);
1473 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS
, op
);
1475 pe
->sram
.byte
[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS
+
1476 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS
)] &=
1477 ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK
>>
1478 (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS
% 8)));
1480 pe
->sram
.byte
[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS
+
1481 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS
)] |=
1482 (op
>> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS
% 8)));
1484 /* Set base offset as current */
1485 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS
, 1);
1488 /* Find parser flow entry */
1489 static struct mvpp2_prs_entry
*mvpp2_prs_flow_find(struct mvpp2
*priv
, int flow
)
1491 struct mvpp2_prs_entry
*pe
;
1494 pe
= kzalloc(sizeof(*pe
), GFP_KERNEL
);
1497 mvpp2_prs_tcam_lu_set(pe
, MVPP2_PRS_LU_FLOWS
);
1499 /* Go through the all entires with MVPP2_PRS_LU_FLOWS */
1500 for (tid
= MVPP2_PRS_TCAM_SRAM_SIZE
- 1; tid
>= 0; tid
--) {
1503 if (!priv
->prs_shadow
[tid
].valid
||
1504 priv
->prs_shadow
[tid
].lu
!= MVPP2_PRS_LU_FLOWS
)
1508 mvpp2_prs_hw_read(priv
, pe
);
1509 bits
= mvpp2_prs_sram_ai_get(pe
);
1511 /* Sram store classification lookup ID in AI bits [5:0] */
1512 if ((bits
& MVPP2_PRS_FLOW_ID_MASK
) == flow
)
1520 /* Return first free tcam index, seeking from start to end */
1521 static int mvpp2_prs_tcam_first_free(struct mvpp2
*priv
, unsigned char start
,
1529 if (end
>= MVPP2_PRS_TCAM_SRAM_SIZE
)
1530 end
= MVPP2_PRS_TCAM_SRAM_SIZE
- 1;
1532 for (tid
= start
; tid
<= end
; tid
++) {
1533 if (!priv
->prs_shadow
[tid
].valid
)
1540 /* Enable/disable dropping all mac da's */
1541 static void mvpp2_prs_mac_drop_all_set(struct mvpp2
*priv
, int port
, bool add
)
1543 struct mvpp2_prs_entry pe
;
1545 if (priv
->prs_shadow
[MVPP2_PE_DROP_ALL
].valid
) {
1546 /* Entry exist - update port only */
1547 pe
.index
= MVPP2_PE_DROP_ALL
;
1548 mvpp2_prs_hw_read(priv
, &pe
);
1550 /* Entry doesn't exist - create new */
1551 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
1552 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_MAC
);
1553 pe
.index
= MVPP2_PE_DROP_ALL
;
1555 /* Non-promiscuous mode for all ports - DROP unknown packets */
1556 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_DROP_MASK
,
1557 MVPP2_PRS_RI_DROP_MASK
);
1559 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
1560 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
1562 /* Update shadow table */
1563 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_MAC
);
1565 /* Mask all ports */
1566 mvpp2_prs_tcam_port_map_set(&pe
, 0);
1569 /* Update port mask */
1570 mvpp2_prs_tcam_port_set(&pe
, port
, add
);
1572 mvpp2_prs_hw_write(priv
, &pe
);
1575 /* Set port to promiscuous mode */
1576 static void mvpp2_prs_mac_promisc_set(struct mvpp2
*priv
, int port
, bool add
)
1578 struct mvpp2_prs_entry pe
;
1580 /* Promiscuous mode - Accept unknown packets */
1582 if (priv
->prs_shadow
[MVPP2_PE_MAC_PROMISCUOUS
].valid
) {
1583 /* Entry exist - update port only */
1584 pe
.index
= MVPP2_PE_MAC_PROMISCUOUS
;
1585 mvpp2_prs_hw_read(priv
, &pe
);
1587 /* Entry doesn't exist - create new */
1588 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
1589 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_MAC
);
1590 pe
.index
= MVPP2_PE_MAC_PROMISCUOUS
;
1592 /* Continue - set next lookup */
1593 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_DSA
);
1595 /* Set result info bits */
1596 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L2_UCAST
,
1597 MVPP2_PRS_RI_L2_CAST_MASK
);
1599 /* Shift to ethertype */
1600 mvpp2_prs_sram_shift_set(&pe
, 2 * ETH_ALEN
,
1601 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
1603 /* Mask all ports */
1604 mvpp2_prs_tcam_port_map_set(&pe
, 0);
1606 /* Update shadow table */
1607 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_MAC
);
1610 /* Update port mask */
1611 mvpp2_prs_tcam_port_set(&pe
, port
, add
);
1613 mvpp2_prs_hw_write(priv
, &pe
);
1616 /* Accept multicast */
1617 static void mvpp2_prs_mac_multi_set(struct mvpp2
*priv
, int port
, int index
,
1620 struct mvpp2_prs_entry pe
;
1621 unsigned char da_mc
;
1623 /* Ethernet multicast address first byte is
1624 * 0x01 for IPv4 and 0x33 for IPv6
1626 da_mc
= (index
== MVPP2_PE_MAC_MC_ALL
) ? 0x01 : 0x33;
1628 if (priv
->prs_shadow
[index
].valid
) {
1629 /* Entry exist - update port only */
1631 mvpp2_prs_hw_read(priv
, &pe
);
1633 /* Entry doesn't exist - create new */
1634 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
1635 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_MAC
);
1638 /* Continue - set next lookup */
1639 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_DSA
);
1641 /* Set result info bits */
1642 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L2_MCAST
,
1643 MVPP2_PRS_RI_L2_CAST_MASK
);
1645 /* Update tcam entry data first byte */
1646 mvpp2_prs_tcam_data_byte_set(&pe
, 0, da_mc
, 0xff);
1648 /* Shift to ethertype */
1649 mvpp2_prs_sram_shift_set(&pe
, 2 * ETH_ALEN
,
1650 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
1652 /* Mask all ports */
1653 mvpp2_prs_tcam_port_map_set(&pe
, 0);
1655 /* Update shadow table */
1656 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_MAC
);
1659 /* Update port mask */
1660 mvpp2_prs_tcam_port_set(&pe
, port
, add
);
1662 mvpp2_prs_hw_write(priv
, &pe
);
1665 /* Parser per-port initialization */
1666 static void mvpp2_prs_hw_port_init(struct mvpp2
*priv
, int port
, int lu_first
,
1667 int lu_max
, int offset
)
1672 val
= mvpp2_read(priv
, MVPP2_PRS_INIT_LOOKUP_REG
);
1673 val
&= ~MVPP2_PRS_PORT_LU_MASK(port
);
1674 val
|= MVPP2_PRS_PORT_LU_VAL(port
, lu_first
);
1675 mvpp2_write(priv
, MVPP2_PRS_INIT_LOOKUP_REG
, val
);
1677 /* Set maximum number of loops for packet received from port */
1678 val
= mvpp2_read(priv
, MVPP2_PRS_MAX_LOOP_REG(port
));
1679 val
&= ~MVPP2_PRS_MAX_LOOP_MASK(port
);
1680 val
|= MVPP2_PRS_MAX_LOOP_VAL(port
, lu_max
);
1681 mvpp2_write(priv
, MVPP2_PRS_MAX_LOOP_REG(port
), val
);
1683 /* Set initial offset for packet header extraction for the first
1686 val
= mvpp2_read(priv
, MVPP2_PRS_INIT_OFFS_REG(port
));
1687 val
&= ~MVPP2_PRS_INIT_OFF_MASK(port
);
1688 val
|= MVPP2_PRS_INIT_OFF_VAL(port
, offset
);
1689 mvpp2_write(priv
, MVPP2_PRS_INIT_OFFS_REG(port
), val
);
1692 /* Default flow entries initialization for all ports */
1693 static void mvpp2_prs_def_flow_init(struct mvpp2
*priv
)
1695 struct mvpp2_prs_entry pe
;
1698 for (port
= 0; port
< MVPP2_MAX_PORTS
; port
++) {
1699 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
1700 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
1701 pe
.index
= MVPP2_PE_FIRST_DEFAULT_FLOW
- port
;
1703 /* Mask all ports */
1704 mvpp2_prs_tcam_port_map_set(&pe
, 0);
1707 mvpp2_prs_sram_ai_update(&pe
, port
, MVPP2_PRS_FLOW_ID_MASK
);
1708 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_DONE_BIT
, 1);
1710 /* Update shadow table and hw entry */
1711 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_FLOWS
);
1712 mvpp2_prs_hw_write(priv
, &pe
);
1716 /* Set default entry for Marvell Header field */
1717 static void mvpp2_prs_mh_init(struct mvpp2
*priv
)
1719 struct mvpp2_prs_entry pe
;
1721 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
1723 pe
.index
= MVPP2_PE_MH_DEFAULT
;
1724 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_MH
);
1725 mvpp2_prs_sram_shift_set(&pe
, MVPP2_MH_SIZE
,
1726 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
1727 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_MAC
);
1729 /* Unmask all ports */
1730 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
1732 /* Update shadow table and hw entry */
1733 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_MH
);
1734 mvpp2_prs_hw_write(priv
, &pe
);
1737 /* Set default entires (place holder) for promiscuous, non-promiscuous and
1738 * multicast MAC addresses
1740 static void mvpp2_prs_mac_init(struct mvpp2
*priv
)
1742 struct mvpp2_prs_entry pe
;
1744 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
1746 /* Non-promiscuous mode for all ports - DROP unknown packets */
1747 pe
.index
= MVPP2_PE_MAC_NON_PROMISCUOUS
;
1748 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_MAC
);
1750 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_DROP_MASK
,
1751 MVPP2_PRS_RI_DROP_MASK
);
1752 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
1753 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
1755 /* Unmask all ports */
1756 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
1758 /* Update shadow table and hw entry */
1759 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_MAC
);
1760 mvpp2_prs_hw_write(priv
, &pe
);
1762 /* place holders only - no ports */
1763 mvpp2_prs_mac_drop_all_set(priv
, 0, false);
1764 mvpp2_prs_mac_promisc_set(priv
, 0, false);
1765 mvpp2_prs_mac_multi_set(priv
, MVPP2_PE_MAC_MC_ALL
, 0, false);
1766 mvpp2_prs_mac_multi_set(priv
, MVPP2_PE_MAC_MC_IP6
, 0, false);
1769 /* Match basic ethertypes */
1770 static int mvpp2_prs_etype_init(struct mvpp2
*priv
)
1772 struct mvpp2_prs_entry pe
;
1775 /* Ethertype: PPPoE */
1776 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
1777 MVPP2_PE_LAST_FREE_TID
);
1781 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
1782 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_L2
);
1785 mvpp2_prs_match_etype(&pe
, 0, PROT_PPP_SES
);
1787 mvpp2_prs_sram_shift_set(&pe
, MVPP2_PPPOE_HDR_SIZE
,
1788 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
1789 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_PPPOE
);
1790 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_PPPOE_MASK
,
1791 MVPP2_PRS_RI_PPPOE_MASK
);
1793 /* Update shadow table and hw entry */
1794 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_L2
);
1795 priv
->prs_shadow
[pe
.index
].udf
= MVPP2_PRS_UDF_L2_DEF
;
1796 priv
->prs_shadow
[pe
.index
].finish
= false;
1797 mvpp2_prs_shadow_ri_set(priv
, pe
.index
, MVPP2_PRS_RI_PPPOE_MASK
,
1798 MVPP2_PRS_RI_PPPOE_MASK
);
1799 mvpp2_prs_hw_write(priv
, &pe
);
1801 /* Ethertype: ARP */
1802 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
1803 MVPP2_PE_LAST_FREE_TID
);
1807 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
1808 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_L2
);
1811 mvpp2_prs_match_etype(&pe
, 0, PROT_ARP
);
1813 /* Generate flow in the next iteration*/
1814 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
1815 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
1816 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_ARP
,
1817 MVPP2_PRS_RI_L3_PROTO_MASK
);
1819 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L3
,
1821 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
1823 /* Update shadow table and hw entry */
1824 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_L2
);
1825 priv
->prs_shadow
[pe
.index
].udf
= MVPP2_PRS_UDF_L2_DEF
;
1826 priv
->prs_shadow
[pe
.index
].finish
= true;
1827 mvpp2_prs_shadow_ri_set(priv
, pe
.index
, MVPP2_PRS_RI_L3_ARP
,
1828 MVPP2_PRS_RI_L3_PROTO_MASK
);
1829 mvpp2_prs_hw_write(priv
, &pe
);
1831 /* Ethertype: LBTD */
1832 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
1833 MVPP2_PE_LAST_FREE_TID
);
1837 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
1838 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_L2
);
1841 mvpp2_prs_match_etype(&pe
, 0, MVPP2_IP_LBDT_TYPE
);
1843 /* Generate flow in the next iteration*/
1844 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
1845 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
1846 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_CPU_CODE_RX_SPEC
|
1847 MVPP2_PRS_RI_UDF3_RX_SPECIAL
,
1848 MVPP2_PRS_RI_CPU_CODE_MASK
|
1849 MVPP2_PRS_RI_UDF3_MASK
);
1851 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L3
,
1853 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
1855 /* Update shadow table and hw entry */
1856 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_L2
);
1857 priv
->prs_shadow
[pe
.index
].udf
= MVPP2_PRS_UDF_L2_DEF
;
1858 priv
->prs_shadow
[pe
.index
].finish
= true;
1859 mvpp2_prs_shadow_ri_set(priv
, pe
.index
, MVPP2_PRS_RI_CPU_CODE_RX_SPEC
|
1860 MVPP2_PRS_RI_UDF3_RX_SPECIAL
,
1861 MVPP2_PRS_RI_CPU_CODE_MASK
|
1862 MVPP2_PRS_RI_UDF3_MASK
);
1863 mvpp2_prs_hw_write(priv
, &pe
);
1865 /* Ethertype: IPv4 without options */
1866 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
1867 MVPP2_PE_LAST_FREE_TID
);
1871 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
1872 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_L2
);
1875 mvpp2_prs_match_etype(&pe
, 0, PROT_IP
);
1876 mvpp2_prs_tcam_data_byte_set(&pe
, MVPP2_ETH_TYPE_LEN
,
1877 MVPP2_PRS_IPV4_HEAD
| MVPP2_PRS_IPV4_IHL
,
1878 MVPP2_PRS_IPV4_HEAD_MASK
|
1879 MVPP2_PRS_IPV4_IHL_MASK
);
1881 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_IP4
);
1882 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_IP4
,
1883 MVPP2_PRS_RI_L3_PROTO_MASK
);
1884 /* Skip eth_type + 4 bytes of IP header */
1885 mvpp2_prs_sram_shift_set(&pe
, MVPP2_ETH_TYPE_LEN
+ 4,
1886 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
1888 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L3
,
1890 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
1892 /* Update shadow table and hw entry */
1893 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_L2
);
1894 priv
->prs_shadow
[pe
.index
].udf
= MVPP2_PRS_UDF_L2_DEF
;
1895 priv
->prs_shadow
[pe
.index
].finish
= false;
1896 mvpp2_prs_shadow_ri_set(priv
, pe
.index
, MVPP2_PRS_RI_L3_IP4
,
1897 MVPP2_PRS_RI_L3_PROTO_MASK
);
1898 mvpp2_prs_hw_write(priv
, &pe
);
1900 /* Ethertype: IPv4 with options */
1901 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
1902 MVPP2_PE_LAST_FREE_TID
);
1908 /* Clear tcam data before updating */
1909 pe
.tcam
.byte
[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN
)] = 0x0;
1910 pe
.tcam
.byte
[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN
)] = 0x0;
1912 mvpp2_prs_tcam_data_byte_set(&pe
, MVPP2_ETH_TYPE_LEN
,
1913 MVPP2_PRS_IPV4_HEAD
,
1914 MVPP2_PRS_IPV4_HEAD_MASK
);
1916 /* Clear ri before updating */
1917 pe
.sram
.word
[MVPP2_PRS_SRAM_RI_WORD
] = 0x0;
1918 pe
.sram
.word
[MVPP2_PRS_SRAM_RI_CTRL_WORD
] = 0x0;
1919 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_IP4_OPT
,
1920 MVPP2_PRS_RI_L3_PROTO_MASK
);
1922 /* Update shadow table and hw entry */
1923 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_L2
);
1924 priv
->prs_shadow
[pe
.index
].udf
= MVPP2_PRS_UDF_L2_DEF
;
1925 priv
->prs_shadow
[pe
.index
].finish
= false;
1926 mvpp2_prs_shadow_ri_set(priv
, pe
.index
, MVPP2_PRS_RI_L3_IP4_OPT
,
1927 MVPP2_PRS_RI_L3_PROTO_MASK
);
1928 mvpp2_prs_hw_write(priv
, &pe
);
1930 /* Ethertype: IPv6 without options */
1931 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
1932 MVPP2_PE_LAST_FREE_TID
);
1936 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
1937 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_L2
);
1940 mvpp2_prs_match_etype(&pe
, 0, PROT_IPV6
);
1942 /* Skip DIP of IPV6 header */
1943 mvpp2_prs_sram_shift_set(&pe
, MVPP2_ETH_TYPE_LEN
+ 8 +
1944 MVPP2_MAX_L3_ADDR_SIZE
,
1945 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
1946 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_IP6
);
1947 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_IP6
,
1948 MVPP2_PRS_RI_L3_PROTO_MASK
);
1950 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L3
,
1952 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
1954 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_L2
);
1955 priv
->prs_shadow
[pe
.index
].udf
= MVPP2_PRS_UDF_L2_DEF
;
1956 priv
->prs_shadow
[pe
.index
].finish
= false;
1957 mvpp2_prs_shadow_ri_set(priv
, pe
.index
, MVPP2_PRS_RI_L3_IP6
,
1958 MVPP2_PRS_RI_L3_PROTO_MASK
);
1959 mvpp2_prs_hw_write(priv
, &pe
);
1961 /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */
1962 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
1963 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_L2
);
1964 pe
.index
= MVPP2_PE_ETH_TYPE_UN
;
1966 /* Unmask all ports */
1967 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
1969 /* Generate flow in the next iteration*/
1970 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
1971 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
1972 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_UN
,
1973 MVPP2_PRS_RI_L3_PROTO_MASK
);
1974 /* Set L3 offset even it's unknown L3 */
1975 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L3
,
1977 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
1979 /* Update shadow table and hw entry */
1980 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_L2
);
1981 priv
->prs_shadow
[pe
.index
].udf
= MVPP2_PRS_UDF_L2_DEF
;
1982 priv
->prs_shadow
[pe
.index
].finish
= true;
1983 mvpp2_prs_shadow_ri_set(priv
, pe
.index
, MVPP2_PRS_RI_L3_UN
,
1984 MVPP2_PRS_RI_L3_PROTO_MASK
);
1985 mvpp2_prs_hw_write(priv
, &pe
);
1990 /* Parser default initialization */
1991 static int mvpp2_prs_default_init(struct udevice
*dev
,
1996 /* Enable tcam table */
1997 mvpp2_write(priv
, MVPP2_PRS_TCAM_CTRL_REG
, MVPP2_PRS_TCAM_EN_MASK
);
1999 /* Clear all tcam and sram entries */
2000 for (index
= 0; index
< MVPP2_PRS_TCAM_SRAM_SIZE
; index
++) {
2001 mvpp2_write(priv
, MVPP2_PRS_TCAM_IDX_REG
, index
);
2002 for (i
= 0; i
< MVPP2_PRS_TCAM_WORDS
; i
++)
2003 mvpp2_write(priv
, MVPP2_PRS_TCAM_DATA_REG(i
), 0);
2005 mvpp2_write(priv
, MVPP2_PRS_SRAM_IDX_REG
, index
);
2006 for (i
= 0; i
< MVPP2_PRS_SRAM_WORDS
; i
++)
2007 mvpp2_write(priv
, MVPP2_PRS_SRAM_DATA_REG(i
), 0);
2010 /* Invalidate all tcam entries */
2011 for (index
= 0; index
< MVPP2_PRS_TCAM_SRAM_SIZE
; index
++)
2012 mvpp2_prs_hw_inv(priv
, index
);
2014 priv
->prs_shadow
= devm_kcalloc(dev
, MVPP2_PRS_TCAM_SRAM_SIZE
,
2015 sizeof(struct mvpp2_prs_shadow
),
2017 if (!priv
->prs_shadow
)
2020 /* Always start from lookup = 0 */
2021 for (index
= 0; index
< MVPP2_MAX_PORTS
; index
++)
2022 mvpp2_prs_hw_port_init(priv
, index
, MVPP2_PRS_LU_MH
,
2023 MVPP2_PRS_PORT_LU_MAX
, 0);
2025 mvpp2_prs_def_flow_init(priv
);
2027 mvpp2_prs_mh_init(priv
);
2029 mvpp2_prs_mac_init(priv
);
2031 err
= mvpp2_prs_etype_init(priv
);
2038 /* Compare MAC DA with tcam entry data */
2039 static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry
*pe
,
2040 const u8
*da
, unsigned char *mask
)
2042 unsigned char tcam_byte
, tcam_mask
;
2045 for (index
= 0; index
< ETH_ALEN
; index
++) {
2046 mvpp2_prs_tcam_data_byte_get(pe
, index
, &tcam_byte
, &tcam_mask
);
2047 if (tcam_mask
!= mask
[index
])
2050 if ((tcam_mask
& tcam_byte
) != (da
[index
] & mask
[index
]))
2057 /* Find tcam entry with matched pair <MAC DA, port> */
2058 static struct mvpp2_prs_entry
*
2059 mvpp2_prs_mac_da_range_find(struct mvpp2
*priv
, int pmap
, const u8
*da
,
2060 unsigned char *mask
, int udf_type
)
2062 struct mvpp2_prs_entry
*pe
;
2065 pe
= kzalloc(sizeof(*pe
), GFP_KERNEL
);
2068 mvpp2_prs_tcam_lu_set(pe
, MVPP2_PRS_LU_MAC
);
2070 /* Go through the all entires with MVPP2_PRS_LU_MAC */
2071 for (tid
= MVPP2_PE_FIRST_FREE_TID
;
2072 tid
<= MVPP2_PE_LAST_FREE_TID
; tid
++) {
2073 unsigned int entry_pmap
;
2075 if (!priv
->prs_shadow
[tid
].valid
||
2076 (priv
->prs_shadow
[tid
].lu
!= MVPP2_PRS_LU_MAC
) ||
2077 (priv
->prs_shadow
[tid
].udf
!= udf_type
))
2081 mvpp2_prs_hw_read(priv
, pe
);
2082 entry_pmap
= mvpp2_prs_tcam_port_map_get(pe
);
2084 if (mvpp2_prs_mac_range_equals(pe
, da
, mask
) &&
2093 /* Update parser's mac da entry */
2094 static int mvpp2_prs_mac_da_accept(struct mvpp2
*priv
, int port
,
2095 const u8
*da
, bool add
)
2097 struct mvpp2_prs_entry
*pe
;
2098 unsigned int pmap
, len
, ri
;
2099 unsigned char mask
[ETH_ALEN
] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
2102 /* Scan TCAM and see if entry with this <MAC DA, port> already exist */
2103 pe
= mvpp2_prs_mac_da_range_find(priv
, (1 << port
), da
, mask
,
2104 MVPP2_PRS_UDF_MAC_DEF
);
2111 /* Create new TCAM entry */
2112 /* Find first range mac entry*/
2113 for (tid
= MVPP2_PE_FIRST_FREE_TID
;
2114 tid
<= MVPP2_PE_LAST_FREE_TID
; tid
++)
2115 if (priv
->prs_shadow
[tid
].valid
&&
2116 (priv
->prs_shadow
[tid
].lu
== MVPP2_PRS_LU_MAC
) &&
2117 (priv
->prs_shadow
[tid
].udf
==
2118 MVPP2_PRS_UDF_MAC_RANGE
))
2121 /* Go through the all entries from first to last */
2122 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
2127 pe
= kzalloc(sizeof(*pe
), GFP_KERNEL
);
2130 mvpp2_prs_tcam_lu_set(pe
, MVPP2_PRS_LU_MAC
);
2133 /* Mask all ports */
2134 mvpp2_prs_tcam_port_map_set(pe
, 0);
2137 /* Update port mask */
2138 mvpp2_prs_tcam_port_set(pe
, port
, add
);
2140 /* Invalidate the entry if no ports are left enabled */
2141 pmap
= mvpp2_prs_tcam_port_map_get(pe
);
2147 mvpp2_prs_hw_inv(priv
, pe
->index
);
2148 priv
->prs_shadow
[pe
->index
].valid
= false;
2153 /* Continue - set next lookup */
2154 mvpp2_prs_sram_next_lu_set(pe
, MVPP2_PRS_LU_DSA
);
2156 /* Set match on DA */
2159 mvpp2_prs_tcam_data_byte_set(pe
, len
, da
[len
], 0xff);
2161 /* Set result info bits */
2162 ri
= MVPP2_PRS_RI_L2_UCAST
| MVPP2_PRS_RI_MAC_ME_MASK
;
2164 mvpp2_prs_sram_ri_update(pe
, ri
, MVPP2_PRS_RI_L2_CAST_MASK
|
2165 MVPP2_PRS_RI_MAC_ME_MASK
);
2166 mvpp2_prs_shadow_ri_set(priv
, pe
->index
, ri
, MVPP2_PRS_RI_L2_CAST_MASK
|
2167 MVPP2_PRS_RI_MAC_ME_MASK
);
2169 /* Shift to ethertype */
2170 mvpp2_prs_sram_shift_set(pe
, 2 * ETH_ALEN
,
2171 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
2173 /* Update shadow table and hw entry */
2174 priv
->prs_shadow
[pe
->index
].udf
= MVPP2_PRS_UDF_MAC_DEF
;
2175 mvpp2_prs_shadow_set(priv
, pe
->index
, MVPP2_PRS_LU_MAC
);
2176 mvpp2_prs_hw_write(priv
, pe
);
2183 static int mvpp2_prs_update_mac_da(struct mvpp2_port
*port
, const u8
*da
)
2187 /* Remove old parser entry */
2188 err
= mvpp2_prs_mac_da_accept(port
->priv
, port
->id
, port
->dev_addr
,
2193 /* Add new parser entry */
2194 err
= mvpp2_prs_mac_da_accept(port
->priv
, port
->id
, da
, true);
2198 /* Set addr in the device */
2199 memcpy(port
->dev_addr
, da
, ETH_ALEN
);
2204 /* Set prs flow for the port */
2205 static int mvpp2_prs_def_flow(struct mvpp2_port
*port
)
2207 struct mvpp2_prs_entry
*pe
;
2210 pe
= mvpp2_prs_flow_find(port
->priv
, port
->id
);
2212 /* Such entry not exist */
2214 /* Go through the all entires from last to first */
2215 tid
= mvpp2_prs_tcam_first_free(port
->priv
,
2216 MVPP2_PE_LAST_FREE_TID
,
2217 MVPP2_PE_FIRST_FREE_TID
);
2221 pe
= kzalloc(sizeof(*pe
), GFP_KERNEL
);
2225 mvpp2_prs_tcam_lu_set(pe
, MVPP2_PRS_LU_FLOWS
);
2229 mvpp2_prs_sram_ai_update(pe
, port
->id
, MVPP2_PRS_FLOW_ID_MASK
);
2230 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_LU_DONE_BIT
, 1);
2232 /* Update shadow table */
2233 mvpp2_prs_shadow_set(port
->priv
, pe
->index
, MVPP2_PRS_LU_FLOWS
);
2236 mvpp2_prs_tcam_port_map_set(pe
, (1 << port
->id
));
2237 mvpp2_prs_hw_write(port
->priv
, pe
);
2243 /* Classifier configuration routines */
2245 /* Update classification flow table registers */
2246 static void mvpp2_cls_flow_write(struct mvpp2
*priv
,
2247 struct mvpp2_cls_flow_entry
*fe
)
2249 mvpp2_write(priv
, MVPP2_CLS_FLOW_INDEX_REG
, fe
->index
);
2250 mvpp2_write(priv
, MVPP2_CLS_FLOW_TBL0_REG
, fe
->data
[0]);
2251 mvpp2_write(priv
, MVPP2_CLS_FLOW_TBL1_REG
, fe
->data
[1]);
2252 mvpp2_write(priv
, MVPP2_CLS_FLOW_TBL2_REG
, fe
->data
[2]);
2255 /* Update classification lookup table register */
2256 static void mvpp2_cls_lookup_write(struct mvpp2
*priv
,
2257 struct mvpp2_cls_lookup_entry
*le
)
2261 val
= (le
->way
<< MVPP2_CLS_LKP_INDEX_WAY_OFFS
) | le
->lkpid
;
2262 mvpp2_write(priv
, MVPP2_CLS_LKP_INDEX_REG
, val
);
2263 mvpp2_write(priv
, MVPP2_CLS_LKP_TBL_REG
, le
->data
);
2266 /* Classifier default initialization */
2267 static void mvpp2_cls_init(struct mvpp2
*priv
)
2269 struct mvpp2_cls_lookup_entry le
;
2270 struct mvpp2_cls_flow_entry fe
;
2273 /* Enable classifier */
2274 mvpp2_write(priv
, MVPP2_CLS_MODE_REG
, MVPP2_CLS_MODE_ACTIVE_MASK
);
2276 /* Clear classifier flow table */
2277 memset(&fe
.data
, 0, MVPP2_CLS_FLOWS_TBL_DATA_WORDS
);
2278 for (index
= 0; index
< MVPP2_CLS_FLOWS_TBL_SIZE
; index
++) {
2280 mvpp2_cls_flow_write(priv
, &fe
);
2283 /* Clear classifier lookup table */
2285 for (index
= 0; index
< MVPP2_CLS_LKP_TBL_SIZE
; index
++) {
2288 mvpp2_cls_lookup_write(priv
, &le
);
2291 mvpp2_cls_lookup_write(priv
, &le
);
2295 static void mvpp2_cls_port_config(struct mvpp2_port
*port
)
2297 struct mvpp2_cls_lookup_entry le
;
2300 /* Set way for the port */
2301 val
= mvpp2_read(port
->priv
, MVPP2_CLS_PORT_WAY_REG
);
2302 val
&= ~MVPP2_CLS_PORT_WAY_MASK(port
->id
);
2303 mvpp2_write(port
->priv
, MVPP2_CLS_PORT_WAY_REG
, val
);
2305 /* Pick the entry to be accessed in lookup ID decoding table
2306 * according to the way and lkpid.
2308 le
.lkpid
= port
->id
;
2312 /* Set initial CPU queue for receiving packets */
2313 le
.data
&= ~MVPP2_CLS_LKP_TBL_RXQ_MASK
;
2314 le
.data
|= port
->first_rxq
;
2316 /* Disable classification engines */
2317 le
.data
&= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK
;
2319 /* Update lookup ID table entry */
2320 mvpp2_cls_lookup_write(port
->priv
, &le
);
2323 /* Set CPU queue number for oversize packets */
2324 static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port
*port
)
2328 mvpp2_write(port
->priv
, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port
->id
),
2329 port
->first_rxq
& MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK
);
2331 mvpp2_write(port
->priv
, MVPP2_CLS_SWFWD_P2HQ_REG(port
->id
),
2332 (port
->first_rxq
>> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS
));
2334 val
= mvpp2_read(port
->priv
, MVPP2_CLS_SWFWD_PCTRL_REG
);
2335 val
|= MVPP2_CLS_SWFWD_PCTRL_MASK(port
->id
);
2336 mvpp2_write(port
->priv
, MVPP2_CLS_SWFWD_PCTRL_REG
, val
);
2339 /* Buffer Manager configuration routines */
2342 static int mvpp2_bm_pool_create(struct udevice
*dev
,
2344 struct mvpp2_bm_pool
*bm_pool
, int size
)
2348 /* Number of buffer pointers must be a multiple of 16, as per
2349 * hardware constraints
2351 if (!IS_ALIGNED(size
, 16))
2354 bm_pool
->virt_addr
= buffer_loc
.bm_pool
[bm_pool
->id
];
2355 bm_pool
->dma_addr
= (dma_addr_t
)buffer_loc
.bm_pool
[bm_pool
->id
];
2356 if (!bm_pool
->virt_addr
)
2359 if (!IS_ALIGNED((unsigned long)bm_pool
->virt_addr
,
2360 MVPP2_BM_POOL_PTR_ALIGN
)) {
2361 dev_err(&pdev
->dev
, "BM pool %d is not %d bytes aligned\n",
2362 bm_pool
->id
, MVPP2_BM_POOL_PTR_ALIGN
);
2366 mvpp2_write(priv
, MVPP2_BM_POOL_BASE_REG(bm_pool
->id
),
2367 lower_32_bits(bm_pool
->dma_addr
));
2368 mvpp2_write(priv
, MVPP2_BM_POOL_SIZE_REG(bm_pool
->id
), size
);
2370 val
= mvpp2_read(priv
, MVPP2_BM_POOL_CTRL_REG(bm_pool
->id
));
2371 val
|= MVPP2_BM_START_MASK
;
2372 mvpp2_write(priv
, MVPP2_BM_POOL_CTRL_REG(bm_pool
->id
), val
);
2374 bm_pool
->type
= MVPP2_BM_FREE
;
2375 bm_pool
->size
= size
;
2376 bm_pool
->pkt_size
= 0;
2377 bm_pool
->buf_num
= 0;
2382 /* Set pool buffer size */
2383 static void mvpp2_bm_pool_bufsize_set(struct mvpp2
*priv
,
2384 struct mvpp2_bm_pool
*bm_pool
,
2389 bm_pool
->buf_size
= buf_size
;
2391 val
= ALIGN(buf_size
, 1 << MVPP2_POOL_BUF_SIZE_OFFSET
);
2392 mvpp2_write(priv
, MVPP2_POOL_BUF_SIZE_REG(bm_pool
->id
), val
);
2395 /* Free all buffers from the pool */
2396 static void mvpp2_bm_bufs_free(struct udevice
*dev
, struct mvpp2
*priv
,
2397 struct mvpp2_bm_pool
*bm_pool
)
2399 bm_pool
->buf_num
= 0;
2403 static int mvpp2_bm_pool_destroy(struct udevice
*dev
,
2405 struct mvpp2_bm_pool
*bm_pool
)
2409 mvpp2_bm_bufs_free(dev
, priv
, bm_pool
);
2410 if (bm_pool
->buf_num
) {
2411 dev_err(dev
, "cannot free all buffers in pool %d\n", bm_pool
->id
);
2415 val
= mvpp2_read(priv
, MVPP2_BM_POOL_CTRL_REG(bm_pool
->id
));
2416 val
|= MVPP2_BM_STOP_MASK
;
2417 mvpp2_write(priv
, MVPP2_BM_POOL_CTRL_REG(bm_pool
->id
), val
);
2422 static int mvpp2_bm_pools_init(struct udevice
*dev
,
2426 struct mvpp2_bm_pool
*bm_pool
;
2428 /* Create all pools with maximum size */
2429 size
= MVPP2_BM_POOL_SIZE_MAX
;
2430 for (i
= 0; i
< MVPP2_BM_POOLS_NUM
; i
++) {
2431 bm_pool
= &priv
->bm_pools
[i
];
2433 err
= mvpp2_bm_pool_create(dev
, priv
, bm_pool
, size
);
2435 goto err_unroll_pools
;
2436 mvpp2_bm_pool_bufsize_set(priv
, bm_pool
, 0);
2441 dev_err(&pdev
->dev
, "failed to create BM pool %d, size %d\n", i
, size
);
2442 for (i
= i
- 1; i
>= 0; i
--)
2443 mvpp2_bm_pool_destroy(dev
, priv
, &priv
->bm_pools
[i
]);
2447 static int mvpp2_bm_init(struct udevice
*dev
, struct mvpp2
*priv
)
2451 for (i
= 0; i
< MVPP2_BM_POOLS_NUM
; i
++) {
2452 /* Mask BM all interrupts */
2453 mvpp2_write(priv
, MVPP2_BM_INTR_MASK_REG(i
), 0);
2454 /* Clear BM cause register */
2455 mvpp2_write(priv
, MVPP2_BM_INTR_CAUSE_REG(i
), 0);
2458 /* Allocate and initialize BM pools */
2459 priv
->bm_pools
= devm_kcalloc(dev
, MVPP2_BM_POOLS_NUM
,
2460 sizeof(struct mvpp2_bm_pool
), GFP_KERNEL
);
2461 if (!priv
->bm_pools
)
2464 err
= mvpp2_bm_pools_init(dev
, priv
);
2470 /* Attach long pool to rxq */
2471 static void mvpp2_rxq_long_pool_set(struct mvpp2_port
*port
,
2472 int lrxq
, int long_pool
)
2477 /* Get queue physical ID */
2478 prxq
= port
->rxqs
[lrxq
]->id
;
2480 if (port
->priv
->hw_version
== MVPP21
)
2481 mask
= MVPP21_RXQ_POOL_LONG_MASK
;
2483 mask
= MVPP22_RXQ_POOL_LONG_MASK
;
2485 val
= mvpp2_read(port
->priv
, MVPP2_RXQ_CONFIG_REG(prxq
));
2487 val
|= (long_pool
<< MVPP2_RXQ_POOL_LONG_OFFS
) & mask
;
2488 mvpp2_write(port
->priv
, MVPP2_RXQ_CONFIG_REG(prxq
), val
);
2491 /* Set pool number in a BM cookie */
2492 static inline u32
mvpp2_bm_cookie_pool_set(u32 cookie
, int pool
)
2496 bm
= cookie
& ~(0xFF << MVPP2_BM_COOKIE_POOL_OFFS
);
2497 bm
|= ((pool
& 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS
);
2502 /* Get pool number from a BM cookie */
2503 static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie
)
2505 return (cookie
>> MVPP2_BM_COOKIE_POOL_OFFS
) & 0xFF;
2508 /* Release buffer to BM */
2509 static inline void mvpp2_bm_pool_put(struct mvpp2_port
*port
, int pool
,
2510 dma_addr_t buf_dma_addr
,
2511 unsigned long buf_phys_addr
)
2513 if (port
->priv
->hw_version
== MVPP22
) {
2516 if (sizeof(dma_addr_t
) == 8)
2517 val
|= upper_32_bits(buf_dma_addr
) &
2518 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK
;
2520 if (sizeof(phys_addr_t
) == 8)
2521 val
|= (upper_32_bits(buf_phys_addr
)
2522 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT
) &
2523 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK
;
2525 mvpp2_write(port
->priv
, MVPP22_BM_ADDR_HIGH_RLS_REG
, val
);
2528 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
2529 * returned in the "cookie" field of the RX
2530 * descriptor. Instead of storing the virtual address, we
2531 * store the physical address
2533 mvpp2_write(port
->priv
, MVPP2_BM_VIRT_RLS_REG
, buf_phys_addr
);
2534 mvpp2_write(port
->priv
, MVPP2_BM_PHY_RLS_REG(pool
), buf_dma_addr
);
2537 /* Refill BM pool */
2538 static void mvpp2_pool_refill(struct mvpp2_port
*port
, u32 bm
,
2539 dma_addr_t dma_addr
,
2540 phys_addr_t phys_addr
)
2542 int pool
= mvpp2_bm_cookie_pool_get(bm
);
2544 mvpp2_bm_pool_put(port
, pool
, dma_addr
, phys_addr
);
2547 /* Allocate buffers for the pool */
2548 static int mvpp2_bm_bufs_add(struct mvpp2_port
*port
,
2549 struct mvpp2_bm_pool
*bm_pool
, int buf_num
)
2554 (buf_num
+ bm_pool
->buf_num
> bm_pool
->size
)) {
2555 netdev_err(port
->dev
,
2556 "cannot allocate %d buffers for pool %d\n",
2557 buf_num
, bm_pool
->id
);
2561 for (i
= 0; i
< buf_num
; i
++) {
2562 mvpp2_bm_pool_put(port
, bm_pool
->id
,
2563 (dma_addr_t
)buffer_loc
.rx_buffer
[i
],
2564 (unsigned long)buffer_loc
.rx_buffer
[i
]);
2568 /* Update BM driver with number of buffers added to pool */
2569 bm_pool
->buf_num
+= i
;
2570 bm_pool
->in_use_thresh
= bm_pool
->buf_num
/ 4;
2575 /* Notify the driver that BM pool is being used as specific type and return the
2576 * pool pointer on success
2578 static struct mvpp2_bm_pool
*
2579 mvpp2_bm_pool_use(struct mvpp2_port
*port
, int pool
, enum mvpp2_bm_type type
,
2582 struct mvpp2_bm_pool
*new_pool
= &port
->priv
->bm_pools
[pool
];
2585 if (new_pool
->type
!= MVPP2_BM_FREE
&& new_pool
->type
!= type
) {
2586 netdev_err(port
->dev
, "mixing pool types is forbidden\n");
2590 if (new_pool
->type
== MVPP2_BM_FREE
)
2591 new_pool
->type
= type
;
2593 /* Allocate buffers in case BM pool is used as long pool, but packet
2594 * size doesn't match MTU or BM pool hasn't being used yet
2596 if (((type
== MVPP2_BM_SWF_LONG
) && (pkt_size
> new_pool
->pkt_size
)) ||
2597 (new_pool
->pkt_size
== 0)) {
2600 /* Set default buffer number or free all the buffers in case
2601 * the pool is not empty
2603 pkts_num
= new_pool
->buf_num
;
2605 pkts_num
= type
== MVPP2_BM_SWF_LONG
?
2606 MVPP2_BM_LONG_BUF_NUM
:
2607 MVPP2_BM_SHORT_BUF_NUM
;
2609 mvpp2_bm_bufs_free(NULL
,
2610 port
->priv
, new_pool
);
2612 new_pool
->pkt_size
= pkt_size
;
2614 /* Allocate buffers for this pool */
2615 num
= mvpp2_bm_bufs_add(port
, new_pool
, pkts_num
);
2616 if (num
!= pkts_num
) {
2617 dev_err(dev
, "pool %d: %d of %d allocated\n",
2618 new_pool
->id
, num
, pkts_num
);
2623 mvpp2_bm_pool_bufsize_set(port
->priv
, new_pool
,
2624 MVPP2_RX_BUF_SIZE(new_pool
->pkt_size
));
2629 /* Initialize pools for swf */
2630 static int mvpp2_swf_bm_pool_init(struct mvpp2_port
*port
)
2634 if (!port
->pool_long
) {
2636 mvpp2_bm_pool_use(port
, MVPP2_BM_SWF_LONG_POOL(port
->id
),
2639 if (!port
->pool_long
)
2642 port
->pool_long
->port_map
|= (1 << port
->id
);
2644 for (rxq
= 0; rxq
< rxq_number
; rxq
++)
2645 mvpp2_rxq_long_pool_set(port
, rxq
, port
->pool_long
->id
);
2651 /* Port configuration routines */
2653 static void mvpp2_port_mii_set(struct mvpp2_port
*port
)
2657 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_2_REG
);
2659 switch (port
->phy_interface
) {
2660 case PHY_INTERFACE_MODE_SGMII
:
2661 val
|= MVPP2_GMAC_INBAND_AN_MASK
;
2663 case PHY_INTERFACE_MODE_RGMII
:
2664 val
|= MVPP2_GMAC_PORT_RGMII_MASK
;
2666 val
&= ~MVPP2_GMAC_PCS_ENABLE_MASK
;
2669 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_2_REG
);
2672 static void mvpp2_port_fc_adv_enable(struct mvpp2_port
*port
)
2676 val
= readl(port
->base
+ MVPP2_GMAC_AUTONEG_CONFIG
);
2677 val
|= MVPP2_GMAC_FC_ADV_EN
;
2678 writel(val
, port
->base
+ MVPP2_GMAC_AUTONEG_CONFIG
);
2681 static void mvpp2_port_enable(struct mvpp2_port
*port
)
2685 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_0_REG
);
2686 val
|= MVPP2_GMAC_PORT_EN_MASK
;
2687 val
|= MVPP2_GMAC_MIB_CNTR_EN_MASK
;
2688 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_0_REG
);
2691 static void mvpp2_port_disable(struct mvpp2_port
*port
)
2695 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_0_REG
);
2696 val
&= ~(MVPP2_GMAC_PORT_EN_MASK
);
2697 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_0_REG
);
2700 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
2701 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port
*port
)
2705 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_1_REG
) &
2706 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK
;
2707 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_1_REG
);
2710 /* Configure loopback port */
2711 static void mvpp2_port_loopback_set(struct mvpp2_port
*port
)
2715 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_1_REG
);
2717 if (port
->speed
== 1000)
2718 val
|= MVPP2_GMAC_GMII_LB_EN_MASK
;
2720 val
&= ~MVPP2_GMAC_GMII_LB_EN_MASK
;
2722 if (port
->phy_interface
== PHY_INTERFACE_MODE_SGMII
)
2723 val
|= MVPP2_GMAC_PCS_LB_EN_MASK
;
2725 val
&= ~MVPP2_GMAC_PCS_LB_EN_MASK
;
2727 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_1_REG
);
2730 static void mvpp2_port_reset(struct mvpp2_port
*port
)
2734 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_2_REG
) &
2735 ~MVPP2_GMAC_PORT_RESET_MASK
;
2736 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_2_REG
);
2738 while (readl(port
->base
+ MVPP2_GMAC_CTRL_2_REG
) &
2739 MVPP2_GMAC_PORT_RESET_MASK
)
2743 /* Change maximum receive size of the port */
2744 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port
*port
)
2748 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_0_REG
);
2749 val
&= ~MVPP2_GMAC_MAX_RX_SIZE_MASK
;
2750 val
|= (((port
->pkt_size
- MVPP2_MH_SIZE
) / 2) <<
2751 MVPP2_GMAC_MAX_RX_SIZE_OFFS
);
2752 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_0_REG
);
2755 /* Set defaults to the MVPP2 port */
2756 static void mvpp2_defaults_set(struct mvpp2_port
*port
)
2758 int tx_port_num
, val
, queue
, ptxq
, lrxq
;
2760 if (port
->priv
->hw_version
== MVPP21
) {
2761 /* Configure port to loopback if needed */
2762 if (port
->flags
& MVPP2_F_LOOPBACK
)
2763 mvpp2_port_loopback_set(port
);
2765 /* Update TX FIFO MIN Threshold */
2766 val
= readl(port
->base
+ MVPP2_GMAC_PORT_FIFO_CFG_1_REG
);
2767 val
&= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK
;
2768 /* Min. TX threshold must be less than minimal packet length */
2769 val
|= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
2770 writel(val
, port
->base
+ MVPP2_GMAC_PORT_FIFO_CFG_1_REG
);
2773 /* Disable Legacy WRR, Disable EJP, Release from reset */
2774 tx_port_num
= mvpp2_egress_port(port
);
2775 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_PORT_INDEX_REG
,
2777 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_CMD_1_REG
, 0);
2779 /* Close bandwidth for all queues */
2780 for (queue
= 0; queue
< MVPP2_MAX_TXQ
; queue
++) {
2781 ptxq
= mvpp2_txq_phys(port
->id
, queue
);
2782 mvpp2_write(port
->priv
,
2783 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq
), 0);
2786 /* Set refill period to 1 usec, refill tokens
2787 * and bucket size to maximum
2789 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_PERIOD_REG
, 0xc8);
2790 val
= mvpp2_read(port
->priv
, MVPP2_TXP_SCHED_REFILL_REG
);
2791 val
&= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK
;
2792 val
|= MVPP2_TXP_REFILL_PERIOD_MASK(1);
2793 val
|= MVPP2_TXP_REFILL_TOKENS_ALL_MASK
;
2794 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_REFILL_REG
, val
);
2795 val
= MVPP2_TXP_TOKEN_SIZE_MAX
;
2796 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_TOKEN_SIZE_REG
, val
);
2798 /* Set MaximumLowLatencyPacketSize value to 256 */
2799 mvpp2_write(port
->priv
, MVPP2_RX_CTRL_REG(port
->id
),
2800 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK
|
2801 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
2803 /* Enable Rx cache snoop */
2804 for (lrxq
= 0; lrxq
< rxq_number
; lrxq
++) {
2805 queue
= port
->rxqs
[lrxq
]->id
;
2806 val
= mvpp2_read(port
->priv
, MVPP2_RXQ_CONFIG_REG(queue
));
2807 val
|= MVPP2_SNOOP_PKT_SIZE_MASK
|
2808 MVPP2_SNOOP_BUF_HDR_MASK
;
2809 mvpp2_write(port
->priv
, MVPP2_RXQ_CONFIG_REG(queue
), val
);
2813 /* Enable/disable receiving packets */
2814 static void mvpp2_ingress_enable(struct mvpp2_port
*port
)
2819 for (lrxq
= 0; lrxq
< rxq_number
; lrxq
++) {
2820 queue
= port
->rxqs
[lrxq
]->id
;
2821 val
= mvpp2_read(port
->priv
, MVPP2_RXQ_CONFIG_REG(queue
));
2822 val
&= ~MVPP2_RXQ_DISABLE_MASK
;
2823 mvpp2_write(port
->priv
, MVPP2_RXQ_CONFIG_REG(queue
), val
);
2827 static void mvpp2_ingress_disable(struct mvpp2_port
*port
)
2832 for (lrxq
= 0; lrxq
< rxq_number
; lrxq
++) {
2833 queue
= port
->rxqs
[lrxq
]->id
;
2834 val
= mvpp2_read(port
->priv
, MVPP2_RXQ_CONFIG_REG(queue
));
2835 val
|= MVPP2_RXQ_DISABLE_MASK
;
2836 mvpp2_write(port
->priv
, MVPP2_RXQ_CONFIG_REG(queue
), val
);
2840 /* Enable transmit via physical egress queue
2841 * - HW starts take descriptors from DRAM
2843 static void mvpp2_egress_enable(struct mvpp2_port
*port
)
2847 int tx_port_num
= mvpp2_egress_port(port
);
2849 /* Enable all initialized TXs. */
2851 for (queue
= 0; queue
< txq_number
; queue
++) {
2852 struct mvpp2_tx_queue
*txq
= port
->txqs
[queue
];
2854 if (txq
->descs
!= NULL
)
2855 qmap
|= (1 << queue
);
2858 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_PORT_INDEX_REG
, tx_port_num
);
2859 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_Q_CMD_REG
, qmap
);
2862 /* Disable transmit via physical egress queue
2863 * - HW doesn't take descriptors from DRAM
2865 static void mvpp2_egress_disable(struct mvpp2_port
*port
)
2869 int tx_port_num
= mvpp2_egress_port(port
);
2871 /* Issue stop command for active channels only */
2872 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_PORT_INDEX_REG
, tx_port_num
);
2873 reg_data
= (mvpp2_read(port
->priv
, MVPP2_TXP_SCHED_Q_CMD_REG
)) &
2874 MVPP2_TXP_SCHED_ENQ_MASK
;
2876 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_Q_CMD_REG
,
2877 (reg_data
<< MVPP2_TXP_SCHED_DISQ_OFFSET
));
2879 /* Wait for all Tx activity to terminate. */
2882 if (delay
>= MVPP2_TX_DISABLE_TIMEOUT_MSEC
) {
2883 netdev_warn(port
->dev
,
2884 "Tx stop timed out, status=0x%08x\n",
2891 /* Check port TX Command register that all
2892 * Tx queues are stopped
2894 reg_data
= mvpp2_read(port
->priv
, MVPP2_TXP_SCHED_Q_CMD_REG
);
2895 } while (reg_data
& MVPP2_TXP_SCHED_ENQ_MASK
);
2898 /* Rx descriptors helper methods */
2900 /* Get number of Rx descriptors occupied by received packets */
2902 mvpp2_rxq_received(struct mvpp2_port
*port
, int rxq_id
)
2904 u32 val
= mvpp2_read(port
->priv
, MVPP2_RXQ_STATUS_REG(rxq_id
));
2906 return val
& MVPP2_RXQ_OCCUPIED_MASK
;
2909 /* Update Rx queue status with the number of occupied and available
2910 * Rx descriptor slots.
2913 mvpp2_rxq_status_update(struct mvpp2_port
*port
, int rxq_id
,
2914 int used_count
, int free_count
)
2916 /* Decrement the number of used descriptors and increment count
2917 * increment the number of free descriptors.
2919 u32 val
= used_count
| (free_count
<< MVPP2_RXQ_NUM_NEW_OFFSET
);
2921 mvpp2_write(port
->priv
, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id
), val
);
2924 /* Get pointer to next RX descriptor to be processed by SW */
2925 static inline struct mvpp2_rx_desc
*
2926 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue
*rxq
)
2928 int rx_desc
= rxq
->next_desc_to_proc
;
2930 rxq
->next_desc_to_proc
= MVPP2_QUEUE_NEXT_DESC(rxq
, rx_desc
);
2931 prefetch(rxq
->descs
+ rxq
->next_desc_to_proc
);
2932 return rxq
->descs
+ rx_desc
;
2935 /* Set rx queue offset */
2936 static void mvpp2_rxq_offset_set(struct mvpp2_port
*port
,
2937 int prxq
, int offset
)
2941 /* Convert offset from bytes to units of 32 bytes */
2942 offset
= offset
>> 5;
2944 val
= mvpp2_read(port
->priv
, MVPP2_RXQ_CONFIG_REG(prxq
));
2945 val
&= ~MVPP2_RXQ_PACKET_OFFSET_MASK
;
2948 val
|= ((offset
<< MVPP2_RXQ_PACKET_OFFSET_OFFS
) &
2949 MVPP2_RXQ_PACKET_OFFSET_MASK
);
2951 mvpp2_write(port
->priv
, MVPP2_RXQ_CONFIG_REG(prxq
), val
);
2954 /* Obtain BM cookie information from descriptor */
2955 static u32
mvpp2_bm_cookie_build(struct mvpp2_port
*port
,
2956 struct mvpp2_rx_desc
*rx_desc
)
2958 int cpu
= smp_processor_id();
2961 pool
= (mvpp2_rxdesc_status_get(port
, rx_desc
) &
2962 MVPP2_RXD_BM_POOL_ID_MASK
) >>
2963 MVPP2_RXD_BM_POOL_ID_OFFS
;
2965 return ((pool
& 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS
) |
2966 ((cpu
& 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS
);
2969 /* Tx descriptors helper methods */
2971 /* Get number of Tx descriptors waiting to be transmitted by HW */
2972 static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port
*port
,
2973 struct mvpp2_tx_queue
*txq
)
2977 mvpp2_write(port
->priv
, MVPP2_TXQ_NUM_REG
, txq
->id
);
2978 val
= mvpp2_read(port
->priv
, MVPP2_TXQ_PENDING_REG
);
2980 return val
& MVPP2_TXQ_PENDING_MASK
;
2983 /* Get pointer to next Tx descriptor to be processed (send) by HW */
2984 static struct mvpp2_tx_desc
*
2985 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue
*txq
)
2987 int tx_desc
= txq
->next_desc_to_proc
;
2989 txq
->next_desc_to_proc
= MVPP2_QUEUE_NEXT_DESC(txq
, tx_desc
);
2990 return txq
->descs
+ tx_desc
;
2993 /* Update HW with number of aggregated Tx descriptors to be sent */
2994 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port
*port
, int pending
)
2996 /* aggregated access - relevant TXQ number is written in TX desc */
2997 mvpp2_write(port
->priv
, MVPP2_AGGR_TXQ_UPDATE_REG
, pending
);
3000 /* Get number of sent descriptors and decrement counter.
3001 * The number of sent descriptors is returned.
3004 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port
*port
,
3005 struct mvpp2_tx_queue
*txq
)
3009 /* Reading status reg resets transmitted descriptor counter */
3010 val
= mvpp2_read(port
->priv
, MVPP2_TXQ_SENT_REG(txq
->id
));
3012 return (val
& MVPP2_TRANSMITTED_COUNT_MASK
) >>
3013 MVPP2_TRANSMITTED_COUNT_OFFSET
;
3016 static void mvpp2_txq_sent_counter_clear(void *arg
)
3018 struct mvpp2_port
*port
= arg
;
3021 for (queue
= 0; queue
< txq_number
; queue
++) {
3022 int id
= port
->txqs
[queue
]->id
;
3024 mvpp2_read(port
->priv
, MVPP2_TXQ_SENT_REG(id
));
3028 /* Set max sizes for Tx queues */
3029 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port
*port
)
3032 int txq
, tx_port_num
;
3034 mtu
= port
->pkt_size
* 8;
3035 if (mtu
> MVPP2_TXP_MTU_MAX
)
3036 mtu
= MVPP2_TXP_MTU_MAX
;
3038 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
3041 /* Indirect access to registers */
3042 tx_port_num
= mvpp2_egress_port(port
);
3043 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_PORT_INDEX_REG
, tx_port_num
);
3046 val
= mvpp2_read(port
->priv
, MVPP2_TXP_SCHED_MTU_REG
);
3047 val
&= ~MVPP2_TXP_MTU_MAX
;
3049 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_MTU_REG
, val
);
3051 /* TXP token size and all TXQs token size must be larger that MTU */
3052 val
= mvpp2_read(port
->priv
, MVPP2_TXP_SCHED_TOKEN_SIZE_REG
);
3053 size
= val
& MVPP2_TXP_TOKEN_SIZE_MAX
;
3056 val
&= ~MVPP2_TXP_TOKEN_SIZE_MAX
;
3058 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_TOKEN_SIZE_REG
, val
);
3061 for (txq
= 0; txq
< txq_number
; txq
++) {
3062 val
= mvpp2_read(port
->priv
,
3063 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq
));
3064 size
= val
& MVPP2_TXQ_TOKEN_SIZE_MAX
;
3068 val
&= ~MVPP2_TXQ_TOKEN_SIZE_MAX
;
3070 mvpp2_write(port
->priv
,
3071 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq
),
3077 /* Free Tx queue skbuffs */
3078 static void mvpp2_txq_bufs_free(struct mvpp2_port
*port
,
3079 struct mvpp2_tx_queue
*txq
,
3080 struct mvpp2_txq_pcpu
*txq_pcpu
, int num
)
3084 for (i
= 0; i
< num
; i
++)
3085 mvpp2_txq_inc_get(txq_pcpu
);
3088 static inline struct mvpp2_rx_queue
*mvpp2_get_rx_queue(struct mvpp2_port
*port
,
3091 int queue
= fls(cause
) - 1;
3093 return port
->rxqs
[queue
];
3096 static inline struct mvpp2_tx_queue
*mvpp2_get_tx_queue(struct mvpp2_port
*port
,
3099 int queue
= fls(cause
) - 1;
3101 return port
->txqs
[queue
];
3104 /* Rx/Tx queue initialization/cleanup methods */
3106 /* Allocate and initialize descriptors for aggr TXQ */
3107 static int mvpp2_aggr_txq_init(struct udevice
*dev
,
3108 struct mvpp2_tx_queue
*aggr_txq
,
3109 int desc_num
, int cpu
,
3114 /* Allocate memory for TX descriptors */
3115 aggr_txq
->descs
= buffer_loc
.aggr_tx_descs
;
3116 aggr_txq
->descs_dma
= (dma_addr_t
)buffer_loc
.aggr_tx_descs
;
3117 if (!aggr_txq
->descs
)
3120 /* Make sure descriptor address is cache line size aligned */
3121 BUG_ON(aggr_txq
->descs
!=
3122 PTR_ALIGN(aggr_txq
->descs
, MVPP2_CPU_D_CACHE_LINE_SIZE
));
3124 aggr_txq
->last_desc
= aggr_txq
->size
- 1;
3126 /* Aggr TXQ no reset WA */
3127 aggr_txq
->next_desc_to_proc
= mvpp2_read(priv
,
3128 MVPP2_AGGR_TXQ_INDEX_REG(cpu
));
3130 /* Set Tx descriptors queue starting address indirect
3133 if (priv
->hw_version
== MVPP21
)
3134 txq_dma
= aggr_txq
->descs_dma
;
3136 txq_dma
= aggr_txq
->descs_dma
>>
3137 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS
;
3139 mvpp2_write(priv
, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu
), txq_dma
);
3140 mvpp2_write(priv
, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu
), desc_num
);
3145 /* Create a specified Rx queue */
3146 static int mvpp2_rxq_init(struct mvpp2_port
*port
,
3147 struct mvpp2_rx_queue
*rxq
)
3152 rxq
->size
= port
->rx_ring_size
;
3154 /* Allocate memory for RX descriptors */
3155 rxq
->descs
= buffer_loc
.rx_descs
;
3156 rxq
->descs_dma
= (dma_addr_t
)buffer_loc
.rx_descs
;
3160 BUG_ON(rxq
->descs
!=
3161 PTR_ALIGN(rxq
->descs
, MVPP2_CPU_D_CACHE_LINE_SIZE
));
3163 rxq
->last_desc
= rxq
->size
- 1;
3165 /* Zero occupied and non-occupied counters - direct access */
3166 mvpp2_write(port
->priv
, MVPP2_RXQ_STATUS_REG(rxq
->id
), 0);
3168 /* Set Rx descriptors queue starting address - indirect access */
3169 mvpp2_write(port
->priv
, MVPP2_RXQ_NUM_REG
, rxq
->id
);
3170 if (port
->priv
->hw_version
== MVPP21
)
3171 rxq_dma
= rxq
->descs_dma
;
3173 rxq_dma
= rxq
->descs_dma
>> MVPP22_DESC_ADDR_OFFS
;
3174 mvpp2_write(port
->priv
, MVPP2_RXQ_DESC_ADDR_REG
, rxq_dma
);
3175 mvpp2_write(port
->priv
, MVPP2_RXQ_DESC_SIZE_REG
, rxq
->size
);
3176 mvpp2_write(port
->priv
, MVPP2_RXQ_INDEX_REG
, 0);
3179 mvpp2_rxq_offset_set(port
, rxq
->id
, NET_SKB_PAD
);
3181 /* Add number of descriptors ready for receiving packets */
3182 mvpp2_rxq_status_update(port
, rxq
->id
, 0, rxq
->size
);
3187 /* Push packets received by the RXQ to BM pool */
3188 static void mvpp2_rxq_drop_pkts(struct mvpp2_port
*port
,
3189 struct mvpp2_rx_queue
*rxq
)
3193 rx_received
= mvpp2_rxq_received(port
, rxq
->id
);
3197 for (i
= 0; i
< rx_received
; i
++) {
3198 struct mvpp2_rx_desc
*rx_desc
= mvpp2_rxq_next_desc_get(rxq
);
3199 u32 bm
= mvpp2_bm_cookie_build(port
, rx_desc
);
3201 mvpp2_pool_refill(port
, bm
,
3202 mvpp2_rxdesc_dma_addr_get(port
, rx_desc
),
3203 mvpp2_rxdesc_cookie_get(port
, rx_desc
));
3205 mvpp2_rxq_status_update(port
, rxq
->id
, rx_received
, rx_received
);
3208 /* Cleanup Rx queue */
3209 static void mvpp2_rxq_deinit(struct mvpp2_port
*port
,
3210 struct mvpp2_rx_queue
*rxq
)
3212 mvpp2_rxq_drop_pkts(port
, rxq
);
3216 rxq
->next_desc_to_proc
= 0;
3219 /* Clear Rx descriptors queue starting address and size;
3220 * free descriptor number
3222 mvpp2_write(port
->priv
, MVPP2_RXQ_STATUS_REG(rxq
->id
), 0);
3223 mvpp2_write(port
->priv
, MVPP2_RXQ_NUM_REG
, rxq
->id
);
3224 mvpp2_write(port
->priv
, MVPP2_RXQ_DESC_ADDR_REG
, 0);
3225 mvpp2_write(port
->priv
, MVPP2_RXQ_DESC_SIZE_REG
, 0);
3228 /* Create and initialize a Tx queue */
3229 static int mvpp2_txq_init(struct mvpp2_port
*port
,
3230 struct mvpp2_tx_queue
*txq
)
3233 int cpu
, desc
, desc_per_txq
, tx_port_num
;
3234 struct mvpp2_txq_pcpu
*txq_pcpu
;
3236 txq
->size
= port
->tx_ring_size
;
3238 /* Allocate memory for Tx descriptors */
3239 txq
->descs
= buffer_loc
.tx_descs
;
3240 txq
->descs_dma
= (dma_addr_t
)buffer_loc
.tx_descs
;
3244 /* Make sure descriptor address is cache line size aligned */
3245 BUG_ON(txq
->descs
!=
3246 PTR_ALIGN(txq
->descs
, MVPP2_CPU_D_CACHE_LINE_SIZE
));
3248 txq
->last_desc
= txq
->size
- 1;
3250 /* Set Tx descriptors queue starting address - indirect access */
3251 mvpp2_write(port
->priv
, MVPP2_TXQ_NUM_REG
, txq
->id
);
3252 mvpp2_write(port
->priv
, MVPP2_TXQ_DESC_ADDR_REG
, txq
->descs_dma
);
3253 mvpp2_write(port
->priv
, MVPP2_TXQ_DESC_SIZE_REG
, txq
->size
&
3254 MVPP2_TXQ_DESC_SIZE_MASK
);
3255 mvpp2_write(port
->priv
, MVPP2_TXQ_INDEX_REG
, 0);
3256 mvpp2_write(port
->priv
, MVPP2_TXQ_RSVD_CLR_REG
,
3257 txq
->id
<< MVPP2_TXQ_RSVD_CLR_OFFSET
);
3258 val
= mvpp2_read(port
->priv
, MVPP2_TXQ_PENDING_REG
);
3259 val
&= ~MVPP2_TXQ_PENDING_MASK
;
3260 mvpp2_write(port
->priv
, MVPP2_TXQ_PENDING_REG
, val
);
3262 /* Calculate base address in prefetch buffer. We reserve 16 descriptors
3263 * for each existing TXQ.
3264 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
3265 * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS
3268 desc
= (port
->id
* MVPP2_MAX_TXQ
* desc_per_txq
) +
3269 (txq
->log_id
* desc_per_txq
);
3271 mvpp2_write(port
->priv
, MVPP2_TXQ_PREF_BUF_REG
,
3272 MVPP2_PREF_BUF_PTR(desc
) | MVPP2_PREF_BUF_SIZE_16
|
3273 MVPP2_PREF_BUF_THRESH(desc_per_txq
/2));
3275 /* WRR / EJP configuration - indirect access */
3276 tx_port_num
= mvpp2_egress_port(port
);
3277 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_PORT_INDEX_REG
, tx_port_num
);
3279 val
= mvpp2_read(port
->priv
, MVPP2_TXQ_SCHED_REFILL_REG(txq
->log_id
));
3280 val
&= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK
;
3281 val
|= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
3282 val
|= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK
;
3283 mvpp2_write(port
->priv
, MVPP2_TXQ_SCHED_REFILL_REG(txq
->log_id
), val
);
3285 val
= MVPP2_TXQ_TOKEN_SIZE_MAX
;
3286 mvpp2_write(port
->priv
, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq
->log_id
),
3289 for_each_present_cpu(cpu
) {
3290 txq_pcpu
= per_cpu_ptr(txq
->pcpu
, cpu
);
3291 txq_pcpu
->size
= txq
->size
;
3297 /* Free allocated TXQ resources */
3298 static void mvpp2_txq_deinit(struct mvpp2_port
*port
,
3299 struct mvpp2_tx_queue
*txq
)
3303 txq
->next_desc_to_proc
= 0;
3306 /* Set minimum bandwidth for disabled TXQs */
3307 mvpp2_write(port
->priv
, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq
->id
), 0);
3309 /* Set Tx descriptors queue starting address and size */
3310 mvpp2_write(port
->priv
, MVPP2_TXQ_NUM_REG
, txq
->id
);
3311 mvpp2_write(port
->priv
, MVPP2_TXQ_DESC_ADDR_REG
, 0);
3312 mvpp2_write(port
->priv
, MVPP2_TXQ_DESC_SIZE_REG
, 0);
3315 /* Cleanup Tx ports */
3316 static void mvpp2_txq_clean(struct mvpp2_port
*port
, struct mvpp2_tx_queue
*txq
)
3318 struct mvpp2_txq_pcpu
*txq_pcpu
;
3319 int delay
, pending
, cpu
;
3322 mvpp2_write(port
->priv
, MVPP2_TXQ_NUM_REG
, txq
->id
);
3323 val
= mvpp2_read(port
->priv
, MVPP2_TXQ_PREF_BUF_REG
);
3324 val
|= MVPP2_TXQ_DRAIN_EN_MASK
;
3325 mvpp2_write(port
->priv
, MVPP2_TXQ_PREF_BUF_REG
, val
);
3327 /* The napi queue has been stopped so wait for all packets
3328 * to be transmitted.
3332 if (delay
>= MVPP2_TX_PENDING_TIMEOUT_MSEC
) {
3333 netdev_warn(port
->dev
,
3334 "port %d: cleaning queue %d timed out\n",
3335 port
->id
, txq
->log_id
);
3341 pending
= mvpp2_txq_pend_desc_num_get(port
, txq
);
3344 val
&= ~MVPP2_TXQ_DRAIN_EN_MASK
;
3345 mvpp2_write(port
->priv
, MVPP2_TXQ_PREF_BUF_REG
, val
);
3347 for_each_present_cpu(cpu
) {
3348 txq_pcpu
= per_cpu_ptr(txq
->pcpu
, cpu
);
3350 /* Release all packets */
3351 mvpp2_txq_bufs_free(port
, txq
, txq_pcpu
, txq_pcpu
->count
);
3354 txq_pcpu
->count
= 0;
3355 txq_pcpu
->txq_put_index
= 0;
3356 txq_pcpu
->txq_get_index
= 0;
3360 /* Cleanup all Tx queues */
3361 static void mvpp2_cleanup_txqs(struct mvpp2_port
*port
)
3363 struct mvpp2_tx_queue
*txq
;
3367 val
= mvpp2_read(port
->priv
, MVPP2_TX_PORT_FLUSH_REG
);
3369 /* Reset Tx ports and delete Tx queues */
3370 val
|= MVPP2_TX_PORT_FLUSH_MASK(port
->id
);
3371 mvpp2_write(port
->priv
, MVPP2_TX_PORT_FLUSH_REG
, val
);
3373 for (queue
= 0; queue
< txq_number
; queue
++) {
3374 txq
= port
->txqs
[queue
];
3375 mvpp2_txq_clean(port
, txq
);
3376 mvpp2_txq_deinit(port
, txq
);
3379 mvpp2_txq_sent_counter_clear(port
);
3381 val
&= ~MVPP2_TX_PORT_FLUSH_MASK(port
->id
);
3382 mvpp2_write(port
->priv
, MVPP2_TX_PORT_FLUSH_REG
, val
);
3385 /* Cleanup all Rx queues */
3386 static void mvpp2_cleanup_rxqs(struct mvpp2_port
*port
)
3390 for (queue
= 0; queue
< rxq_number
; queue
++)
3391 mvpp2_rxq_deinit(port
, port
->rxqs
[queue
]);
3394 /* Init all Rx queues for port */
3395 static int mvpp2_setup_rxqs(struct mvpp2_port
*port
)
3399 for (queue
= 0; queue
< rxq_number
; queue
++) {
3400 err
= mvpp2_rxq_init(port
, port
->rxqs
[queue
]);
3407 mvpp2_cleanup_rxqs(port
);
3411 /* Init all tx queues for port */
3412 static int mvpp2_setup_txqs(struct mvpp2_port
*port
)
3414 struct mvpp2_tx_queue
*txq
;
3417 for (queue
= 0; queue
< txq_number
; queue
++) {
3418 txq
= port
->txqs
[queue
];
3419 err
= mvpp2_txq_init(port
, txq
);
3424 mvpp2_txq_sent_counter_clear(port
);
3428 mvpp2_cleanup_txqs(port
);
3433 static void mvpp2_link_event(struct mvpp2_port
*port
)
3435 struct phy_device
*phydev
= port
->phy_dev
;
3436 int status_change
= 0;
3440 if ((port
->speed
!= phydev
->speed
) ||
3441 (port
->duplex
!= phydev
->duplex
)) {
3444 val
= readl(port
->base
+ MVPP2_GMAC_AUTONEG_CONFIG
);
3445 val
&= ~(MVPP2_GMAC_CONFIG_MII_SPEED
|
3446 MVPP2_GMAC_CONFIG_GMII_SPEED
|
3447 MVPP2_GMAC_CONFIG_FULL_DUPLEX
|
3448 MVPP2_GMAC_AN_SPEED_EN
|
3449 MVPP2_GMAC_AN_DUPLEX_EN
);
3452 val
|= MVPP2_GMAC_CONFIG_FULL_DUPLEX
;
3454 if (phydev
->speed
== SPEED_1000
)
3455 val
|= MVPP2_GMAC_CONFIG_GMII_SPEED
;
3456 else if (phydev
->speed
== SPEED_100
)
3457 val
|= MVPP2_GMAC_CONFIG_MII_SPEED
;
3459 writel(val
, port
->base
+ MVPP2_GMAC_AUTONEG_CONFIG
);
3461 port
->duplex
= phydev
->duplex
;
3462 port
->speed
= phydev
->speed
;
3466 if (phydev
->link
!= port
->link
) {
3467 if (!phydev
->link
) {
3472 port
->link
= phydev
->link
;
3476 if (status_change
) {
3478 val
= readl(port
->base
+ MVPP2_GMAC_AUTONEG_CONFIG
);
3479 val
|= (MVPP2_GMAC_FORCE_LINK_PASS
|
3480 MVPP2_GMAC_FORCE_LINK_DOWN
);
3481 writel(val
, port
->base
+ MVPP2_GMAC_AUTONEG_CONFIG
);
3482 mvpp2_egress_enable(port
);
3483 mvpp2_ingress_enable(port
);
3485 mvpp2_ingress_disable(port
);
3486 mvpp2_egress_disable(port
);
3491 /* Main RX/TX processing routines */
3493 /* Display more error info */
3494 static void mvpp2_rx_error(struct mvpp2_port
*port
,
3495 struct mvpp2_rx_desc
*rx_desc
)
3497 u32 status
= mvpp2_rxdesc_status_get(port
, rx_desc
);
3498 size_t sz
= mvpp2_rxdesc_size_get(port
, rx_desc
);
3500 switch (status
& MVPP2_RXD_ERR_CODE_MASK
) {
3501 case MVPP2_RXD_ERR_CRC
:
3502 netdev_err(port
->dev
, "bad rx status %08x (crc error), size=%zu\n",
3505 case MVPP2_RXD_ERR_OVERRUN
:
3506 netdev_err(port
->dev
, "bad rx status %08x (overrun error), size=%zu\n",
3509 case MVPP2_RXD_ERR_RESOURCE
:
3510 netdev_err(port
->dev
, "bad rx status %08x (resource error), size=%zu\n",
3516 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
3517 static int mvpp2_rx_refill(struct mvpp2_port
*port
,
3518 struct mvpp2_bm_pool
*bm_pool
,
3519 u32 bm
, dma_addr_t dma_addr
)
3521 mvpp2_pool_refill(port
, bm
, dma_addr
, (unsigned long)dma_addr
);
3525 /* Set hw internals when starting port */
3526 static void mvpp2_start_dev(struct mvpp2_port
*port
)
3528 mvpp2_gmac_max_rx_size_set(port
);
3529 mvpp2_txp_max_tx_size_set(port
);
3531 mvpp2_port_enable(port
);
3534 /* Set hw internals when stopping port */
3535 static void mvpp2_stop_dev(struct mvpp2_port
*port
)
3537 /* Stop new packets from arriving to RXQs */
3538 mvpp2_ingress_disable(port
);
3540 mvpp2_egress_disable(port
);
3541 mvpp2_port_disable(port
);
3544 static int mvpp2_phy_connect(struct udevice
*dev
, struct mvpp2_port
*port
)
3546 struct phy_device
*phy_dev
;
3548 if (!port
->init
|| port
->link
== 0) {
3549 phy_dev
= phy_connect(port
->priv
->bus
, port
->phyaddr
, dev
,
3550 port
->phy_interface
);
3551 port
->phy_dev
= phy_dev
;
3553 netdev_err(port
->dev
, "cannot connect to phy\n");
3556 phy_dev
->supported
&= PHY_GBIT_FEATURES
;
3557 phy_dev
->advertising
= phy_dev
->supported
;
3559 port
->phy_dev
= phy_dev
;
3564 phy_config(phy_dev
);
3565 phy_startup(phy_dev
);
3566 if (!phy_dev
->link
) {
3567 printf("%s: No link\n", phy_dev
->dev
->name
);
3573 mvpp2_egress_enable(port
);
3574 mvpp2_ingress_enable(port
);
3580 static int mvpp2_open(struct udevice
*dev
, struct mvpp2_port
*port
)
3582 unsigned char mac_bcast
[ETH_ALEN
] = {
3583 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3586 err
= mvpp2_prs_mac_da_accept(port
->priv
, port
->id
, mac_bcast
, true);
3588 netdev_err(dev
, "mvpp2_prs_mac_da_accept BC failed\n");
3591 err
= mvpp2_prs_mac_da_accept(port
->priv
, port
->id
,
3592 port
->dev_addr
, true);
3594 netdev_err(dev
, "mvpp2_prs_mac_da_accept MC failed\n");
3597 err
= mvpp2_prs_def_flow(port
);
3599 netdev_err(dev
, "mvpp2_prs_def_flow failed\n");
3603 /* Allocate the Rx/Tx queues */
3604 err
= mvpp2_setup_rxqs(port
);
3606 netdev_err(port
->dev
, "cannot allocate Rx queues\n");
3610 err
= mvpp2_setup_txqs(port
);
3612 netdev_err(port
->dev
, "cannot allocate Tx queues\n");
3616 err
= mvpp2_phy_connect(dev
, port
);
3620 mvpp2_link_event(port
);
3622 mvpp2_start_dev(port
);
3627 /* No Device ops here in U-Boot */
3629 /* Driver initialization */
3631 static void mvpp2_port_power_up(struct mvpp2_port
*port
)
3633 mvpp2_port_mii_set(port
);
3634 mvpp2_port_periodic_xon_disable(port
);
3635 mvpp2_port_fc_adv_enable(port
);
3636 mvpp2_port_reset(port
);
3639 /* Initialize port HW */
3640 static int mvpp2_port_init(struct udevice
*dev
, struct mvpp2_port
*port
)
3642 struct mvpp2
*priv
= port
->priv
;
3643 struct mvpp2_txq_pcpu
*txq_pcpu
;
3644 int queue
, cpu
, err
;
3646 if (port
->first_rxq
+ rxq_number
> MVPP2_RXQ_TOTAL_NUM
)
3650 mvpp2_egress_disable(port
);
3651 mvpp2_port_disable(port
);
3653 port
->txqs
= devm_kcalloc(dev
, txq_number
, sizeof(*port
->txqs
),
3658 /* Associate physical Tx queues to this port and initialize.
3659 * The mapping is predefined.
3661 for (queue
= 0; queue
< txq_number
; queue
++) {
3662 int queue_phy_id
= mvpp2_txq_phys(port
->id
, queue
);
3663 struct mvpp2_tx_queue
*txq
;
3665 txq
= devm_kzalloc(dev
, sizeof(*txq
), GFP_KERNEL
);
3669 txq
->pcpu
= devm_kzalloc(dev
, sizeof(struct mvpp2_txq_pcpu
),
3674 txq
->id
= queue_phy_id
;
3675 txq
->log_id
= queue
;
3676 txq
->done_pkts_coal
= MVPP2_TXDONE_COAL_PKTS_THRESH
;
3677 for_each_present_cpu(cpu
) {
3678 txq_pcpu
= per_cpu_ptr(txq
->pcpu
, cpu
);
3679 txq_pcpu
->cpu
= cpu
;
3682 port
->txqs
[queue
] = txq
;
3685 port
->rxqs
= devm_kcalloc(dev
, rxq_number
, sizeof(*port
->rxqs
),
3690 /* Allocate and initialize Rx queue for this port */
3691 for (queue
= 0; queue
< rxq_number
; queue
++) {
3692 struct mvpp2_rx_queue
*rxq
;
3694 /* Map physical Rx queue to port's logical Rx queue */
3695 rxq
= devm_kzalloc(dev
, sizeof(*rxq
), GFP_KERNEL
);
3698 /* Map this Rx queue to a physical queue */
3699 rxq
->id
= port
->first_rxq
+ queue
;
3700 rxq
->port
= port
->id
;
3701 rxq
->logic_rxq
= queue
;
3703 port
->rxqs
[queue
] = rxq
;
3706 /* Configure Rx queue group interrupt for this port */
3707 mvpp2_write(priv
, MVPP2_ISR_RXQ_GROUP_REG(port
->id
), CONFIG_MV_ETH_RXQ
);
3709 /* Create Rx descriptor rings */
3710 for (queue
= 0; queue
< rxq_number
; queue
++) {
3711 struct mvpp2_rx_queue
*rxq
= port
->rxqs
[queue
];
3713 rxq
->size
= port
->rx_ring_size
;
3714 rxq
->pkts_coal
= MVPP2_RX_COAL_PKTS
;
3715 rxq
->time_coal
= MVPP2_RX_COAL_USEC
;
3718 mvpp2_ingress_disable(port
);
3720 /* Port default configuration */
3721 mvpp2_defaults_set(port
);
3723 /* Port's classifier configuration */
3724 mvpp2_cls_oversize_rxq_set(port
);
3725 mvpp2_cls_port_config(port
);
3727 /* Provide an initial Rx packet size */
3728 port
->pkt_size
= MVPP2_RX_PKT_SIZE(PKTSIZE_ALIGN
);
3730 /* Initialize pools for swf */
3731 err
= mvpp2_swf_bm_pool_init(port
);
3738 /* Ports initialization */
3739 static int mvpp2_port_probe(struct udevice
*dev
,
3740 struct mvpp2_port
*port
,
3743 int *next_first_rxq
)
3748 const char *phy_mode_str
;
3750 int priv_common_regs_num
= 2;
3753 phy_node
= fdtdec_lookup_phandle(gd
->fdt_blob
, port_node
, "phy");
3755 dev_err(&pdev
->dev
, "missing phy\n");
3759 phy_mode_str
= fdt_getprop(gd
->fdt_blob
, port_node
, "phy-mode", NULL
);
3761 phy_mode
= phy_get_interface_by_name(phy_mode_str
);
3762 if (phy_mode
== -1) {
3763 dev_err(&pdev
->dev
, "incorrect phy mode\n");
3767 id
= fdtdec_get_int(gd
->fdt_blob
, port_node
, "port-id", -1);
3769 dev_err(&pdev
->dev
, "missing port-id value\n");
3773 phyaddr
= fdtdec_get_int(gd
->fdt_blob
, phy_node
, "reg", 0);
3777 port
->first_rxq
= *next_first_rxq
;
3778 port
->phy_node
= phy_node
;
3779 port
->phy_interface
= phy_mode
;
3780 port
->phyaddr
= phyaddr
;
3782 port
->base
= (void __iomem
*)dev_get_addr_index(dev
->parent
,
3783 priv_common_regs_num
3785 if (IS_ERR(port
->base
))
3786 return PTR_ERR(port
->base
);
3788 port
->tx_ring_size
= MVPP2_MAX_TXD
;
3789 port
->rx_ring_size
= MVPP2_MAX_RXD
;
3791 err
= mvpp2_port_init(dev
, port
);
3793 dev_err(&pdev
->dev
, "failed to init port %d\n", id
);
3796 mvpp2_port_power_up(port
);
3798 /* Increment the first Rx queue number to be used by the next port */
3799 *next_first_rxq
+= CONFIG_MV_ETH_RXQ
;
3800 priv
->port_list
[id
] = port
;
3804 /* Initialize decoding windows */
3805 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info
*dram
,
3811 for (i
= 0; i
< 6; i
++) {
3812 mvpp2_write(priv
, MVPP2_WIN_BASE(i
), 0);
3813 mvpp2_write(priv
, MVPP2_WIN_SIZE(i
), 0);
3816 mvpp2_write(priv
, MVPP2_WIN_REMAP(i
), 0);
3821 for (i
= 0; i
< dram
->num_cs
; i
++) {
3822 const struct mbus_dram_window
*cs
= dram
->cs
+ i
;
3824 mvpp2_write(priv
, MVPP2_WIN_BASE(i
),
3825 (cs
->base
& 0xffff0000) | (cs
->mbus_attr
<< 8) |
3826 dram
->mbus_dram_target_id
);
3828 mvpp2_write(priv
, MVPP2_WIN_SIZE(i
),
3829 (cs
->size
- 1) & 0xffff0000);
3831 win_enable
|= (1 << i
);
3834 mvpp2_write(priv
, MVPP2_BASE_ADDR_ENABLE
, win_enable
);
3837 /* Initialize Rx FIFO's */
3838 static void mvpp2_rx_fifo_init(struct mvpp2
*priv
)
3842 for (port
= 0; port
< MVPP2_MAX_PORTS
; port
++) {
3843 mvpp2_write(priv
, MVPP2_RX_DATA_FIFO_SIZE_REG(port
),
3844 MVPP2_RX_FIFO_PORT_DATA_SIZE
);
3845 mvpp2_write(priv
, MVPP2_RX_ATTR_FIFO_SIZE_REG(port
),
3846 MVPP2_RX_FIFO_PORT_ATTR_SIZE
);
3849 mvpp2_write(priv
, MVPP2_RX_MIN_PKT_SIZE_REG
,
3850 MVPP2_RX_FIFO_PORT_MIN_PKT
);
3851 mvpp2_write(priv
, MVPP2_RX_FIFO_INIT_REG
, 0x1);
3854 /* Initialize network controller common part HW */
3855 static int mvpp2_init(struct udevice
*dev
, struct mvpp2
*priv
)
3857 const struct mbus_dram_target_info
*dram_target_info
;
3861 /* Checks for hardware constraints (U-Boot uses only one rxq) */
3862 if ((rxq_number
> MVPP2_MAX_RXQ
) || (txq_number
> MVPP2_MAX_TXQ
)) {
3863 dev_err(&pdev
->dev
, "invalid queue size parameter\n");
3867 /* MBUS windows configuration */
3868 dram_target_info
= mvebu_mbus_dram_info();
3869 if (dram_target_info
)
3870 mvpp2_conf_mbus_windows(dram_target_info
, priv
);
3872 /* Disable HW PHY polling */
3873 val
= readl(priv
->lms_base
+ MVPP2_PHY_AN_CFG0_REG
);
3874 val
|= MVPP2_PHY_AN_STOP_SMI0_MASK
;
3875 writel(val
, priv
->lms_base
+ MVPP2_PHY_AN_CFG0_REG
);
3877 /* Allocate and initialize aggregated TXQs */
3878 priv
->aggr_txqs
= devm_kcalloc(dev
, num_present_cpus(),
3879 sizeof(struct mvpp2_tx_queue
),
3881 if (!priv
->aggr_txqs
)
3884 for_each_present_cpu(i
) {
3885 priv
->aggr_txqs
[i
].id
= i
;
3886 priv
->aggr_txqs
[i
].size
= MVPP2_AGGR_TXQ_SIZE
;
3887 err
= mvpp2_aggr_txq_init(dev
, &priv
->aggr_txqs
[i
],
3888 MVPP2_AGGR_TXQ_SIZE
, i
, priv
);
3894 mvpp2_rx_fifo_init(priv
);
3896 /* Reset Rx queue group interrupt configuration */
3897 for (i
= 0; i
< MVPP2_MAX_PORTS
; i
++)
3898 mvpp2_write(priv
, MVPP2_ISR_RXQ_GROUP_REG(i
),
3901 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT
,
3902 priv
->lms_base
+ MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG
);
3904 /* Allow cache snoop when transmiting packets */
3905 mvpp2_write(priv
, MVPP2_TX_SNOOP_REG
, 0x1);
3907 /* Buffer Manager initialization */
3908 err
= mvpp2_bm_init(dev
, priv
);
3912 /* Parser default initialization */
3913 err
= mvpp2_prs_default_init(dev
, priv
);
3917 /* Classifier default initialization */
3918 mvpp2_cls_init(priv
);
3923 /* SMI / MDIO functions */
3925 static int smi_wait_ready(struct mvpp2
*priv
)
3927 u32 timeout
= MVPP2_SMI_TIMEOUT
;
3930 /* wait till the SMI is not busy */
3932 /* read smi register */
3933 smi_reg
= readl(priv
->lms_base
+ MVPP2_SMI
);
3934 if (timeout
-- == 0) {
3935 printf("Error: SMI busy timeout\n");
3938 } while (smi_reg
& MVPP2_SMI_BUSY
);
3944 * mpp2_mdio_read - miiphy_read callback function.
3946 * Returns 16bit phy register value, or 0xffff on error
3948 static int mpp2_mdio_read(struct mii_dev
*bus
, int addr
, int devad
, int reg
)
3950 struct mvpp2
*priv
= bus
->priv
;
3954 /* check parameters */
3955 if (addr
> MVPP2_PHY_ADDR_MASK
) {
3956 printf("Error: Invalid PHY address %d\n", addr
);
3960 if (reg
> MVPP2_PHY_REG_MASK
) {
3961 printf("Err: Invalid register offset %d\n", reg
);
3965 /* wait till the SMI is not busy */
3966 if (smi_wait_ready(priv
) < 0)
3969 /* fill the phy address and regiser offset and read opcode */
3970 smi_reg
= (addr
<< MVPP2_SMI_DEV_ADDR_OFFS
)
3971 | (reg
<< MVPP2_SMI_REG_ADDR_OFFS
)
3972 | MVPP2_SMI_OPCODE_READ
;
3974 /* write the smi register */
3975 writel(smi_reg
, priv
->lms_base
+ MVPP2_SMI
);
3977 /* wait till read value is ready */
3978 timeout
= MVPP2_SMI_TIMEOUT
;
3981 /* read smi register */
3982 smi_reg
= readl(priv
->lms_base
+ MVPP2_SMI
);
3983 if (timeout
-- == 0) {
3984 printf("Err: SMI read ready timeout\n");
3987 } while (!(smi_reg
& MVPP2_SMI_READ_VALID
));
3989 /* Wait for the data to update in the SMI register */
3990 for (timeout
= 0; timeout
< MVPP2_SMI_TIMEOUT
; timeout
++)
3993 return readl(priv
->lms_base
+ MVPP2_SMI
) & MVPP2_SMI_DATA_MASK
;
3997 * mpp2_mdio_write - miiphy_write callback function.
3999 * Returns 0 if write succeed, -EINVAL on bad parameters
4002 static int mpp2_mdio_write(struct mii_dev
*bus
, int addr
, int devad
, int reg
,
4005 struct mvpp2
*priv
= bus
->priv
;
4008 /* check parameters */
4009 if (addr
> MVPP2_PHY_ADDR_MASK
) {
4010 printf("Error: Invalid PHY address %d\n", addr
);
4014 if (reg
> MVPP2_PHY_REG_MASK
) {
4015 printf("Err: Invalid register offset %d\n", reg
);
4019 /* wait till the SMI is not busy */
4020 if (smi_wait_ready(priv
) < 0)
4023 /* fill the phy addr and reg offset and write opcode and data */
4024 smi_reg
= value
<< MVPP2_SMI_DATA_OFFS
;
4025 smi_reg
|= (addr
<< MVPP2_SMI_DEV_ADDR_OFFS
)
4026 | (reg
<< MVPP2_SMI_REG_ADDR_OFFS
);
4027 smi_reg
&= ~MVPP2_SMI_OPCODE_READ
;
4029 /* write the smi register */
4030 writel(smi_reg
, priv
->lms_base
+ MVPP2_SMI
);
4035 static int mvpp2_recv(struct udevice
*dev
, int flags
, uchar
**packetp
)
4037 struct mvpp2_port
*port
= dev_get_priv(dev
);
4038 struct mvpp2_rx_desc
*rx_desc
;
4039 struct mvpp2_bm_pool
*bm_pool
;
4040 dma_addr_t dma_addr
;
4042 int pool
, rx_bytes
, err
;
4044 struct mvpp2_rx_queue
*rxq
;
4045 u32 cause_rx_tx
, cause_rx
, cause_misc
;
4048 cause_rx_tx
= mvpp2_read(port
->priv
,
4049 MVPP2_ISR_RX_TX_CAUSE_REG(port
->id
));
4050 cause_rx_tx
&= ~MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK
;
4051 cause_misc
= cause_rx_tx
& MVPP2_CAUSE_MISC_SUM_MASK
;
4052 if (!cause_rx_tx
&& !cause_misc
)
4055 cause_rx
= cause_rx_tx
& MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK
;
4057 /* Process RX packets */
4058 cause_rx
|= port
->pending_cause_rx
;
4059 rxq
= mvpp2_get_rx_queue(port
, cause_rx
);
4061 /* Get number of received packets and clamp the to-do */
4062 rx_received
= mvpp2_rxq_received(port
, rxq
->id
);
4064 /* Return if no packets are received */
4068 rx_desc
= mvpp2_rxq_next_desc_get(rxq
);
4069 rx_status
= mvpp2_rxdesc_status_get(port
, rx_desc
);
4070 rx_bytes
= mvpp2_rxdesc_size_get(port
, rx_desc
);
4071 rx_bytes
-= MVPP2_MH_SIZE
;
4072 dma_addr
= mvpp2_rxdesc_dma_addr_get(port
, rx_desc
);
4074 bm
= mvpp2_bm_cookie_build(port
, rx_desc
);
4075 pool
= mvpp2_bm_cookie_pool_get(bm
);
4076 bm_pool
= &port
->priv
->bm_pools
[pool
];
4078 /* In case of an error, release the requested buffer pointer
4079 * to the Buffer Manager. This request process is controlled
4080 * by the hardware, and the information about the buffer is
4081 * comprised by the RX descriptor.
4083 if (rx_status
& MVPP2_RXD_ERR_SUMMARY
) {
4084 mvpp2_rx_error(port
, rx_desc
);
4085 /* Return the buffer to the pool */
4086 mvpp2_pool_refill(port
, bm
, dma_addr
, dma_addr
);
4090 err
= mvpp2_rx_refill(port
, bm_pool
, bm
, dma_addr
);
4092 netdev_err(port
->dev
, "failed to refill BM pools\n");
4096 /* Update Rx queue management counters */
4098 mvpp2_rxq_status_update(port
, rxq
->id
, 1, 1);
4100 /* give packet to stack - skip on first n bytes */
4101 data
= (u8
*)dma_addr
+ 2 + 32;
4107 * No cache invalidation needed here, since the rx_buffer's are
4108 * located in a uncached memory region
4116 static void mvpp2_txq_drain(struct mvpp2_port
*port
, struct mvpp2_tx_queue
*txq
,
4121 mvpp2_write(port
->priv
, MVPP2_TXQ_NUM_REG
, txq
->id
);
4122 val
= mvpp2_read(port
->priv
, MVPP2_TXQ_PREF_BUF_REG
);
4124 val
|= MVPP2_TXQ_DRAIN_EN_MASK
;
4126 val
&= ~MVPP2_TXQ_DRAIN_EN_MASK
;
4127 mvpp2_write(port
->priv
, MVPP2_TXQ_PREF_BUF_REG
, val
);
4130 static int mvpp2_send(struct udevice
*dev
, void *packet
, int length
)
4132 struct mvpp2_port
*port
= dev_get_priv(dev
);
4133 struct mvpp2_tx_queue
*txq
, *aggr_txq
;
4134 struct mvpp2_tx_desc
*tx_desc
;
4138 txq
= port
->txqs
[0];
4139 aggr_txq
= &port
->priv
->aggr_txqs
[smp_processor_id()];
4141 /* Get a descriptor for the first part of the packet */
4142 tx_desc
= mvpp2_txq_next_desc_get(aggr_txq
);
4143 mvpp2_txdesc_txq_set(port
, tx_desc
, txq
->id
);
4144 mvpp2_txdesc_size_set(port
, tx_desc
, length
);
4145 mvpp2_txdesc_offset_set(port
, tx_desc
,
4146 (dma_addr_t
)packet
& MVPP2_TX_DESC_ALIGN
);
4147 mvpp2_txdesc_dma_addr_set(port
, tx_desc
,
4148 (dma_addr_t
)packet
& ~MVPP2_TX_DESC_ALIGN
);
4149 /* First and Last descriptor */
4150 mvpp2_txdesc_cmd_set(port
, tx_desc
,
4151 MVPP2_TXD_L4_CSUM_NOT
| MVPP2_TXD_IP_CSUM_DISABLE
4152 | MVPP2_TXD_F_DESC
| MVPP2_TXD_L_DESC
);
4155 flush_dcache_range((unsigned long)packet
,
4156 (unsigned long)packet
+ ALIGN(length
, PKTALIGN
));
4158 /* Enable transmit */
4160 mvpp2_aggr_txq_pend_desc_add(port
, 1);
4162 mvpp2_write(port
->priv
, MVPP2_TXQ_NUM_REG
, txq
->id
);
4166 if (timeout
++ > 10000) {
4167 printf("timeout: packet not sent from aggregated to phys TXQ\n");
4170 tx_done
= mvpp2_txq_pend_desc_num_get(port
, txq
);
4173 /* Enable TXQ drain */
4174 mvpp2_txq_drain(port
, txq
, 1);
4178 if (timeout
++ > 10000) {
4179 printf("timeout: packet not sent\n");
4182 tx_done
= mvpp2_txq_sent_desc_proc(port
, txq
);
4185 /* Disable TXQ drain */
4186 mvpp2_txq_drain(port
, txq
, 0);
4191 static int mvpp2_start(struct udevice
*dev
)
4193 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
4194 struct mvpp2_port
*port
= dev_get_priv(dev
);
4196 /* Load current MAC address */
4197 memcpy(port
->dev_addr
, pdata
->enetaddr
, ETH_ALEN
);
4199 /* Reconfigure parser accept the original MAC address */
4200 mvpp2_prs_update_mac_da(port
, port
->dev_addr
);
4202 mvpp2_port_power_up(port
);
4204 mvpp2_open(dev
, port
);
4209 static void mvpp2_stop(struct udevice
*dev
)
4211 struct mvpp2_port
*port
= dev_get_priv(dev
);
4213 mvpp2_stop_dev(port
);
4214 mvpp2_cleanup_rxqs(port
);
4215 mvpp2_cleanup_txqs(port
);
4218 static int mvpp2_probe(struct udevice
*dev
)
4220 struct mvpp2_port
*port
= dev_get_priv(dev
);
4221 struct mvpp2
*priv
= dev_get_priv(dev
->parent
);
4224 /* Initialize network controller */
4225 err
= mvpp2_init(dev
, priv
);
4227 dev_err(&pdev
->dev
, "failed to initialize controller\n");
4231 return mvpp2_port_probe(dev
, port
, dev_of_offset(dev
), priv
,
4232 &buffer_loc
.first_rxq
);
4235 static const struct eth_ops mvpp2_ops
= {
4236 .start
= mvpp2_start
,
4242 static struct driver mvpp2_driver
= {
4245 .probe
= mvpp2_probe
,
4247 .priv_auto_alloc_size
= sizeof(struct mvpp2_port
),
4248 .platdata_auto_alloc_size
= sizeof(struct eth_pdata
),
4252 * Use a MISC device to bind the n instances (child nodes) of the
4253 * network base controller in UCLASS_ETH.
4255 static int mvpp2_base_probe(struct udevice
*dev
)
4257 struct mvpp2
*priv
= dev_get_priv(dev
);
4258 struct mii_dev
*bus
;
4263 /* Save hw-version */
4264 priv
->hw_version
= dev_get_driver_data(dev
);
4267 * U-Boot special buffer handling:
4269 * Allocate buffer area for descs and rx_buffers. This is only
4270 * done once for all interfaces. As only one interface can
4271 * be active. Make this area DMA-safe by disabling the D-cache
4274 /* Align buffer area for descs and rx_buffers to 1MiB */
4275 bd_space
= memalign(1 << MMU_SECTION_SHIFT
, BD_SPACE
);
4276 mmu_set_region_dcache_behaviour((unsigned long)bd_space
,
4277 BD_SPACE
, DCACHE_OFF
);
4279 buffer_loc
.aggr_tx_descs
= (struct mvpp2_tx_desc
*)bd_space
;
4280 size
+= MVPP2_AGGR_TXQ_SIZE
* MVPP2_DESC_ALIGNED_SIZE
;
4282 buffer_loc
.tx_descs
=
4283 (struct mvpp2_tx_desc
*)((unsigned long)bd_space
+ size
);
4284 size
+= MVPP2_MAX_TXD
* MVPP2_DESC_ALIGNED_SIZE
;
4286 buffer_loc
.rx_descs
=
4287 (struct mvpp2_rx_desc
*)((unsigned long)bd_space
+ size
);
4288 size
+= MVPP2_MAX_RXD
* MVPP2_DESC_ALIGNED_SIZE
;
4290 for (i
= 0; i
< MVPP2_BM_POOLS_NUM
; i
++) {
4291 buffer_loc
.bm_pool
[i
] =
4292 (unsigned long *)((unsigned long)bd_space
+ size
);
4293 if (priv
->hw_version
== MVPP21
)
4294 size
+= MVPP2_BM_POOL_SIZE_MAX
* 2 * sizeof(u32
);
4296 size
+= MVPP2_BM_POOL_SIZE_MAX
* 2 * sizeof(u64
);
4299 for (i
= 0; i
< MVPP2_BM_LONG_BUF_NUM
; i
++) {
4300 buffer_loc
.rx_buffer
[i
] =
4301 (unsigned long *)((unsigned long)bd_space
+ size
);
4302 size
+= RX_BUFFER_SIZE
;
4305 /* Save base addresses for later use */
4306 priv
->base
= (void *)dev_get_addr_index(dev
, 0);
4307 if (IS_ERR(priv
->base
))
4308 return PTR_ERR(priv
->base
);
4310 priv
->lms_base
= (void *)dev_get_addr_index(dev
, 1);
4311 if (IS_ERR(priv
->lms_base
))
4312 return PTR_ERR(priv
->lms_base
);
4314 /* Finally create and register the MDIO bus driver */
4317 printf("Failed to allocate MDIO bus\n");
4321 bus
->read
= mpp2_mdio_read
;
4322 bus
->write
= mpp2_mdio_write
;
4323 snprintf(bus
->name
, sizeof(bus
->name
), dev
->name
);
4324 bus
->priv
= (void *)priv
;
4327 return mdio_register(bus
);
4330 static int mvpp2_base_bind(struct udevice
*parent
)
4332 const void *blob
= gd
->fdt_blob
;
4333 int node
= dev_of_offset(parent
);
4334 struct uclass_driver
*drv
;
4335 struct udevice
*dev
;
4336 struct eth_pdata
*plat
;
4341 /* Lookup eth driver */
4342 drv
= lists_uclass_lookup(UCLASS_ETH
);
4344 puts("Cannot find eth driver\n");
4348 fdt_for_each_subnode(subnode
, blob
, node
) {
4349 /* Skip disabled ports */
4350 if (!fdtdec_get_is_enabled(blob
, subnode
))
4353 plat
= calloc(1, sizeof(*plat
));
4357 id
= fdtdec_get_int(blob
, subnode
, "port-id", -1);
4359 name
= calloc(1, 16);
4360 sprintf(name
, "mvpp2-%d", id
);
4362 /* Create child device UCLASS_ETH and bind it */
4363 device_bind(parent
, &mvpp2_driver
, name
, plat
, subnode
, &dev
);
4364 dev_set_of_offset(dev
, subnode
);
4370 static const struct udevice_id mvpp2_ids
[] = {
4372 .compatible
= "marvell,armada-375-pp2",
4378 U_BOOT_DRIVER(mvpp2_base
) = {
4379 .name
= "mvpp2_base",
4381 .of_match
= mvpp2_ids
,
4382 .bind
= mvpp2_base_bind
,
4383 .probe
= mvpp2_base_probe
,
4384 .priv_auto_alloc_size
= sizeof(struct mvpp2
),