drivers/net/npe/include/IxNpeA.h

   1 #ifndef __doxygen_HIDE  /* This file is not part of the API */
   2
   3 /**
   4  * @file    IxNpeA.h
   5  *
   6  * @date    22-Mar-2002
   7  *
   8  * @brief   Header file for the IXP400 ATM NPE API
   9  *
  10  *
  11  * @par
  12  * IXP400 SW Release version 2.0
  13  *
  14  * -- Copyright Notice --
  15  *
  16  * @par
  17  * Copyright 2001-2005, Intel Corporation.
  18  * All rights reserved.
  19  *
  20  * @par
  21  * Redistribution and use in source and binary forms, with or without
  22  * modification, are permitted provided that the following conditions
  23  * are met:
  24  * 1. Redistributions of source code must retain the above copyright
  25  *    notice, this list of conditions and the following disclaimer.
  26  * 2. Redistributions in binary form must reproduce the above copyright
  27  *    notice, this list of conditions and the following disclaimer in the
  28  *    documentation and/or other materials provided with the distribution.
  29  * 3. Neither the name of the Intel Corporation nor the names of its contributors
  30  *    may be used to endorse or promote products derived from this software
  31  *    without specific prior written permission.
  32  *
  33  * @par
  34  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
  35  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  36  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  37  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
  38  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  39  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  40  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  41  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  42  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  43  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  44  * SUCH DAMAGE.
  45  *
  46  * @par
  47  * -- End of Copyright Notice --
  48  */
  49
  50 /**
  51  * @defgroup IxNpeA IXP400 NPE-A (IxNpeA) API
  52  *
  53  * @brief The Public API for the IXP400 NPE-A
  54  *
  55  * @{
  56  */
  57
  58 #ifndef IX_NPE_A_H
  59 #define IX_NPE_A_H
  60
  61 #include "IxQMgr.h"
  62 #include "IxOsal.h"
  63 #include "IxQueueAssignments.h"
  64
  65 /* General Message Ids */
  66
  67 /* ATM Message Ids */
  68
  69 /**
  70  * @def IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_WRITE
  71  *
  72  * @brief ATM Message ID command to write the data to the offset in the
  73  * Utopia Configuration Table
  74  */
  75 #define IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_WRITE       0x20
  76
  77 /**
  78  * @def IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_LOAD
  79  *
  80  * @brief ATM Message ID command triggers the NPE to copy the Utopia
  81  * Configuration Table to the Utopia coprocessor
  82  */
  83 #define IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_LOAD        0x21
  84
  85 /**
  86  * @def IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_UPLOAD
  87  *
  88  * @brief ATM Message ID command triggers the NPE to read-back the Utopia
  89  * status registers and update the Utopia Status Table.
  90  */
  91 #define IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_UPLOAD      0x22
  92
  93 /**
  94  * @def IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_READ
  95  *
  96  * @brief ATM Message ID command to read the Utopia Status Table at the
  97  * specified offset.
  98  */
  99 #define IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_READ        0x23
 100
 101 /**
 102  * @def IX_NPE_A_MSSG_ATM_TX_ENABLE
 103  *
 104  * @brief ATM Message ID command triggers the NPE to re-enable processing
 105  * of any entries on the TxVcQ for this port.
 106  *
 107  * This command will be ignored for a port already enabled
 108  */
 109 #define IX_NPE_A_MSSG_ATM_TX_ENABLE                 0x25
 110
 111  /**
 112  * @def IX_NPE_A_MSSG_ATM_TX_DISABLE
 113  *
 114  * @brief ATM Message ID command triggers the NPE to disable processing on
 115  * this port
 116  *
 117  * This command will be ignored for a port already disabled
 118  */
 119 #define IX_NPE_A_MSSG_ATM_TX_DISABLE                0x26
 120
 121 /**
 122  * @def IX_NPE_A_MSSG_ATM_RX_ENABLE
 123  *
 124  * @brief ATM Message ID command triggers the NPE to process any received
 125  * cells for this VC according to the VC Lookup Table.
 126  *
 127  * Re-issuing this command with different contents for a VC that is not
 128  * disabled will cause unpredictable behavior.
 129  */
 130 #define IX_NPE_A_MSSG_ATM_RX_ENABLE                 0x27
 131
 132 /**
 133  * @def IX_NPE_A_MSSG_ATM_RX_DISABLE
 134  *
 135  * @brief ATM Message ID command triggers the NPE to disable processing for
 136  * this VC.
 137  *
 138  * This command will be ignored for a VC already disabled
 139  */
 140 #define IX_NPE_A_MSSG_ATM_RX_DISABLE                0x28
 141
 142 /**
 143  * @def IX_NPE_A_MSSG_ATM_STATUS_READ
 144  *
 145  * @brief ATM Message ID command to read the ATM status. The data is returned via
 146  * a response message
 147  */
 148 #define IX_NPE_A_MSSG_ATM_STATUS_READ               0x29
 149
 150 /*--------------------------------------------------------------------------
 151  * HSS Message IDs
 152  *--------------------------------------------------------------------------*/
 153
 154 /**
 155  * @def IX_NPE_A_MSSG_HSS_PORT_CONFIG_WRITE
 156  *
 157  * @brief HSS Message ID command writes the ConfigWord value to the location
 158  * in the HSS_CONFIG_TABLE specified by offset for HSS port hPort.
 159  */
 160 #define IX_NPE_A_MSSG_HSS_PORT_CONFIG_WRITE         0x40
 161
 162 /**
 163  * @def IX_NPE_A_MSSG_HSS_PORT_CONFIG_LOAD
 164  *
 165  * @brief HSS Message ID command triggers the NPE to copy the contents of the
 166  * HSS Configuration Table to the appropriate configuration registers in the
 167  * HSS coprocessor for the port specified by hPort.
 168  */
 169 #define IX_NPE_A_MSSG_HSS_PORT_CONFIG_LOAD          0x41
 170
 171 /**
 172  * @def IX_NPE_A_MSSG_HSS_PORT_ERROR_READ
 173  *
 174  * @brief HSS Message ID command triggers the NPE to return an HssErrorReadResponse
 175  * message for HSS port hPort.
 176  */
 177 #define IX_NPE_A_MSSG_HSS_PORT_ERROR_READ           0x42
 178
 179 /**
 180  * @def IX_NPE_A_MSSG_HSS_CHAN_FLOW_ENABLE
 181  *
 182  * @brief HSS Message ID command triggers the NPE to reset internal status and
 183  * enable the HssChannelized operation on the HSS port specified by hPort.
 184  */
 185 #define IX_NPE_A_MSSG_HSS_CHAN_FLOW_ENABLE          0x43
 186
 187 /**
 188  * @def IX_NPE_A_MSSG_HSS_CHAN_FLOW_DISABLE
 189  *
 190  * @brief HSS Message ID command triggers the NPE to disable the HssChannelized
 191  * operation on the HSS port specified by hPort.
 192  */
 193 #define IX_NPE_A_MSSG_HSS_CHAN_FLOW_DISABLE         0x44
 194
 195 /**
 196  * @def  IX_NPE_A_MSSG_HSS_CHAN_IDLE_PATTERN_WRITE
 197  *
 198  * @brief HSS Message ID command writes the HSSnC_IDLE_PATTERN value for HSS
 199  * port hPort. (n=hPort)
 200  */
 201 #define IX_NPE_A_MSSG_HSS_CHAN_IDLE_PATTERN_WRITE   0x45
 202
 203 /**
 204  * @def IX_NPE_A_MSSG_HSS_CHAN_NUM_CHANS_WRITE
 205  *
 206  * @brief HSS Message ID command writes the HSSnC_NUM_CHANNELS value for HSS
 207  * port hPort. (n=hPort)
 208  */
 209 #define IX_NPE_A_MSSG_HSS_CHAN_NUM_CHANS_WRITE      0x46
 210
 211 /**
 212  * @def IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_ADDR_WRITE
 213  *
 214  * @brief HSS Message ID command writes the HSSnC_RX_BUF_ADDR value for HSS
 215  * port hPort. (n=hPort)
 216  */
 217 #define IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_ADDR_WRITE    0x47
 218
 219 /**
 220  * @def IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_CFG_WRITE
 221  *
 222  * @brief HSS Message ID command  writes the HSSnC_RX_BUF_SIZEB and
 223  * HSSnC_RX_TRIG_PERIOD values for HSS port hPort.  (n=hPort)
 224  */
 225 #define IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_CFG_WRITE     0x48
 226
 227 /**
 228  * @def IX_NPE_A_MSSG_HSS_CHAN_TX_BLK_CFG_WRITE
 229  *
 230  * @brief HSS Message ID command writes the HSSnC_TX_BLK1_SIZEB,
 231  * HSSnC_TX_BLK1_SIZEW, HSSnC_TX_BLK2_SIZEB, and HSSnC_TX_BLK2_SIZEW  values
 232  * for HSS port hPort. (n=hPort)
 233  */
 234 #define IX_NPE_A_MSSG_HSS_CHAN_TX_BLK_CFG_WRITE     0x49
 235
 236 /**
 237  * @def IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_ADDR_WRITE
 238  * @brief HSS Message ID command writes the HSSnC_TX_BUF_ADDR value for HSS
 239  * port hPort. (n=hPort)
 240  */
 241 #define IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_ADDR_WRITE    0x4A
 242
 243 /**
 244  * @def IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_SIZE_WRITE
 245  *
 246  * @brief HSS Message ID command writes the HSSnC_TX_BUF_SIZEN value for HSS
 247  * port hPort. (n=hPort)
 248  */
 249 #define IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_SIZE_WRITE    0x4B
 250
 251 /**
 252  * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_ENABLE
 253  *
 254  * @brief HSS Message ID command triggers the NPE to reset internal status and
 255  * enable the HssPacketized operation for the flow specified by pPipe on
 256  * the HSS port specified by hPort.
 257  */
 258 #define IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_ENABLE      0x50
 259
 260 /**
 261  * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_DISABLE
 262  * @brief HSS Message ID command triggers the NPE to disable the HssPacketized
 263  * operation for the flow specified by pPipe on the HSS port specified by hPort.
 264  */
 265 #define IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_DISABLE     0x51
 266
 267 /**
 268  * @def IX_NPE_A_MSSG_HSS_PKT_NUM_PIPES_WRITE
 269  * @brief HSS Message ID command writes the HSSnP_NUM_PIPES value for HSS
 270  * port hPort.(n=hPort)
 271  */
 272 #define IX_NPE_A_MSSG_HSS_PKT_NUM_PIPES_WRITE       0x52
 273
 274 /**
 275  * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_FIFO_SIZEW_WRITE
 276  *
 277  * @brief HSS Message ID command writes the HSSnP_PIPEp_FIFOSIZEW value for
 278  * packet-pipe pPipe on HSS port hPort.  (n=hPort, p=pPipe)
 279  */
 280 #define IX_NPE_A_MSSG_HSS_PKT_PIPE_FIFO_SIZEW_WRITE 0x53
 281
 282 /**
 283  * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_HDLC_CFG_WRITE
 284  *
 285  * @brief HSS Message ID command writes the HSSnP_PIPEp_HDLC_RXCFG and
 286  * HSSnP_PIPEp_HDLC_TXCFG values for packet-pipe pPipe on HSS port hPort.
 287  * (n=hPort, p=pPipe)
 288  */
 289 #define IX_NPE_A_MSSG_HSS_PKT_PIPE_HDLC_CFG_WRITE   0x54
 290
 291 /**
 292  * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_IDLE_PATTERN_WRITE
 293  *
 294  * @brief HSS Message ID command writes the HSSnP_PIPEp_IDLE_PATTERN value
 295  * for packet-pipe pPipe on HSS port hPort.  (n=hPort, p=pPipe)
 296  */
 297 #define IX_NPE_A_MSSG_HSS_PKT_PIPE_IDLE_PATTERN_WRITE 0x55
 298
 299 /**
 300  * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_RX_SIZE_WRITE
 301  *
 302  * @brief HSS Message ID command writes the HSSnP_PIPEp_RXSIZEB value for
 303  * packet-pipe pPipe on HSS port hPort.  (n=hPort, p=pPipe)
 304  */
 305 #define IX_NPE_A_MSSG_HSS_PKT_PIPE_RX_SIZE_WRITE    0x56
 306
 307 /**
 308  * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_MODE_WRITE
 309  *
 310  * @brief HSS Message ID command writes the HSSnP_PIPEp_MODE value for
 311  * packet-pipe pPipe on HSS port hPort.  (n=hPort, p=pPipe)
 312  */
 313 #define IX_NPE_A_MSSG_HSS_PKT_PIPE_MODE_WRITE       0x57
 314
 315
 316
 317 /* Queue Entry Masks */
 318
 319 /*--------------------------------------------------------------------------
 320  *  ATM Descriptor Structure offsets
 321  *--------------------------------------------------------------------------*/
 322
 323 /**
 324  * @def IX_NPE_A_RXDESCRIPTOR_STATUS_OFFSET
 325  *
 326  * @brief ATM Descriptor structure offset for Receive Descriptor Status field
 327  *
 328  * It is used for descriptor error reporting.
 329  */
 330 #define IX_NPE_A_RXDESCRIPTOR_STATUS_OFFSET          0
 331
 332 /**
 333  * @def IX_NPE_A_RXDESCRIPTOR_VCID_OFFSET
 334  *
 335  * @brief ATM Descriptor structure offset for Receive Descriptor VC ID field
 336  *
 337  * It is used to hold an identifier number for this VC
 338  */
 339 #define IX_NPE_A_RXDESCRIPTOR_VCID_OFFSET            1
 340
 341 /**
 342  * @def IX_NPE_A_RXDESCRIPTOR_CURRMBUFSIZE_OFFSET
 343  *
 344  * @brief ATM Descriptor structure offset for Receive Descriptor Current Mbuf
 345  * Size field
 346  *
 347  * Number of bytes the current mbuf data buffer can hold
 348  */
 349 #define IX_NPE_A_RXDESCRIPTOR_CURRMBUFSIZE_OFFSET    2
 350
 351 /**
 352  * @def IX_NPE_A_RXDESCRIPTOR_ATMHEADER_OFFSET
 353  *
 354  * @brief ATM Descriptor structure offset for Receive Descriptor ATM Header
 355  */
 356 #define IX_NPE_A_RXDESCRIPTOR_ATMHEADER_OFFSET       4
 357
 358 /**
 359  * @def IX_NPE_A_RXDESCRIPTOR_CURRMBUFLEN_OFFSET
 360  *
 361  * @brief ATM Descriptor structure offset for Receive Descriptor Current MBuf length
 362  *
 363  *
 364  * RX - Initialized to zero.  The NPE updates this field as each cell is received and
 365  * zeroes it with every new mbuf for chaining. Will not be bigger than currBbufSize.
 366  */
 367 #define IX_NPE_A_RXDESCRIPTOR_CURRMBUFLEN_OFFSET    12
 368
 369 /**
 370  * @def IX_NPE_A_RXDESCRIPTOR_TIMELIMIT__OFFSET
 371  *
 372  * @brief ATM Descriptor structure offset for Receive Descriptor Time Limit field
 373  *
 374  * Contains the Payload Reassembly Time Limit (used for aal0_xx only)
 375  */
 376 #define IX_NPE_A_RXDESCRIPTOR_TIMELIMIT_OFFSET        14
 377
 378 /**
 379  * @def IX_NPE_A_RXDESCRIPTOR_PCURRMBUFF_OFFSET
 380  *
 381  * @brief ATM Descriptor structure offset for Receive Descriptor Current MBuf Pointer
 382  *
 383  * The current mbuf pointer of a chain of mbufs.
 384  */
 385 #define IX_NPE_A_RXDESCRIPTOR_PCURRMBUFF_OFFSET     20
 386
 387 /**
 388  * @def IX_NPE_A_RXDESCRIPTOR_PCURRMBUFDATA_OFFSET
 389  *
 390  * @brief ATM Descriptor structure offset for Receive Descriptor Current MBuf Pointer
 391  *
 392  * Pointer to the next byte to be read or next free location to be written.
 393  */
 394 #define IX_NPE_A_RXDESCRIPTOR_PCURRMBUFDATA_OFFSET  24
 395
 396 /**
 397  * @def IX_NPE_A_RXDESCRIPTOR_PNEXTMBUF_OFFSET
 398  *
 399  * @brief ATM Descriptor structure offset for Receive Descriptor Next MBuf Pointer
 400  *
 401  * Pointer to the next MBuf in a chain of MBufs.
 402  */
 403 #define IX_NPE_A_RXDESCRIPTOR_PNEXTMBUF_OFFSET      28
 404
 405 /**
 406  * @def IX_NPE_A_RXDESCRIPTOR_TOTALLENGTH_OFFSET
 407  *
 408  * @brief ATM Descriptor structure offset for Receive Descriptor Total Length
 409  *
 410  * Total number of bytes written to the chain of MBufs by the NPE
 411  */
 412 #define IX_NPE_A_RXDESCRIPTOR_TOTALLENGTH_OFFSET    32
 413
 414 /**
 415  * @def IX_NPE_A_RXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET
 416  *
 417  * @brief ATM Descriptor structure offset for Receive Descriptor AAL5 CRC Residue
 418  *
 419  * Current CRC value for a PDU
 420  */
 421 #define IX_NPE_A_RXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET 36
 422
 423 /**
 424  * @def IX_NPE_A_RXDESCRIPTOR_SIZE
 425  *
 426  * @brief ATM Descriptor structure offset for Receive Descriptor Size
 427  *
 428  * The size of the Receive descriptor
 429  */
 430 #define IX_NPE_A_RXDESCRIPTOR_SIZE                  40
 431
 432 /**
 433  * @def IX_NPE_A_TXDESCRIPTOR_PORT_OFFSET
 434  *
 435  * @brief ATM Descriptor structure offset for Transmit Descriptor Port
 436  *
 437  * Port identifier.
 438  */
 439 #define IX_NPE_A_TXDESCRIPTOR_PORT_OFFSET            0
 440
 441 /**
 442  * @def IX_NPE_A_TXDESCRIPTOR_RSVD_OFFSET
 443  *
 444  * @brief ATM Descriptor structure offset for Transmit Descriptor RSVD
 445  */
 446 #define IX_NPE_A_TXDESCRIPTOR_RSVD_OFFSET            1
 447
 448 /**
 449  * @def IX_NPE_A_TXDESCRIPTOR_CURRMBUFLEN_OFFSET
 450  *
 451  * @brief ATM Descriptor structure offset for Transmit Descriptor Current MBuf Length
 452  *
 453  * TX - Initialized by the XScale to the number of bytes in the current MBuf data buffer.
 454  * The NPE decrements this field for every transmitted cell.  Thus, when the NPE writes a
 455  * descriptor the TxDone queue, this field will equal zero.
 456  */
 457 #define IX_NPE_A_TXDESCRIPTOR_CURRMBUFLEN_OFFSET     2
 458
 459 /**
 460  * @def IX_NPE_A_TXDESCRIPTOR_ATMHEADER_OFFSET
 461  * @brief ATM Descriptor structure offset for Transmit Descriptor ATM Header
 462  */
 463 #define IX_NPE_A_TXDESCRIPTOR_ATMHEADER_OFFSET       4
 464
 465 /**
 466  * @def IX_NPE_A_TXDESCRIPTOR_PCURRMBUFF_OFFSET
 467  *
 468  * @brief ATM Descriptor structure offset for Transmit Descriptor Pointer to the current MBuf chain
 469  */
 470 #define IX_NPE_A_TXDESCRIPTOR_PCURRMBUFF_OFFSET      8
 471
 472 /**
 473  * @def IX_NPE_A_TXDESCRIPTOR_PCURRMBUFDATA_OFFSET
 474  *
 475  * @brief ATM Descriptor structure offset for Transmit Descriptor Pointer to the current MBuf Data
 476  *
 477  * Pointer to the next byte to be read or next free location to be written.
 478  */
 479 #define IX_NPE_A_TXDESCRIPTOR_PCURRMBUFDATA_OFFSET  12
 480
 481 /**
 482  * @def IX_NPE_A_TXDESCRIPTOR_PNEXTMBUF_OFFSET
 483  *
 484  * @brief ATM Descriptor structure offset for Transmit Descriptor Pointer to the Next MBuf chain
 485  */
 486 #define IX_NPE_A_TXDESCRIPTOR_PNEXTMBUF_OFFSET      16
 487
 488 /**
 489  * @def IX_NPE_A_TXDESCRIPTOR_TOTALLENGTH_OFFSET
 490  *
 491  * @brief ATM Descriptor structure offset for Transmit Descriptor Total Length
 492  *
 493  * Total number of bytes written to the chain of MBufs by the NPE
 494  */
 495 #define IX_NPE_A_TXDESCRIPTOR_TOTALLENGTH_OFFSET    20
 496
 497 /**
 498  * @def IX_NPE_A_TXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET
 499  *
 500  * @brief ATM Descriptor structure offset for Transmit Descriptor AAL5 CRC Residue
 501  *
 502  * Current CRC value for a PDU
 503  */
 504 #define IX_NPE_A_TXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET 24
 505
 506 /**
 507  * @def IX_NPE_A_TXDESCRIPTOR_SIZE
 508  *
 509  * @brief ATM Descriptor structure offset for Transmit Descriptor Size
 510  */
 511 #define IX_NPE_A_TXDESCRIPTOR_SIZE                  28
 512
 513 /**
 514  * @def IX_NPE_A_CHAIN_DESC_COUNT_MAX
 515  *
 516  * @brief Maximum number of chained MBufs that can be chained together
 517  */
 518 #define IX_NPE_A_CHAIN_DESC_COUNT_MAX            256
 519
 520 /*
 521  *  Definition of the ATM cell header
 522  *
 523  * This would most conviently be defined as the bit field shown below.
 524  * Endian portability prevents this, therefore a set of macros
 525  * are defined to access the fields within the cell header assumed to
 526  * be passed as a UINT32.
 527  *
 528  * Changes to field sizes or orders must be reflected in the offset
 529  * definitions above.
 530  *
 531  *    typedef struct
 532  *    {
 533  *       unsigned int gfc:4;
 534  *       unsigned int vpi:8;
 535  *       unsigned int vci:16;
 536  *       unsigned int pti:3;
 537  *       unsigned int clp:1;
 538  *    } IxNpeA_AtmCellHeader;
 539  *
 540  */
 541
 542 /** Mask to acess GFC */
 543 #define GFC_MASK        0xf0000000
 544
 545 /** return GFC from ATM cell header */
 546 #define IX_NPE_A_ATMCELLHEADER_GFC_GET( header ) \
 547 (((header) & GFC_MASK) >> 28)
 548
 549 /** set GFC into ATM cell header */
 550 #define IX_NPE_A_ATMCELLHEADER_GFC_SET( header,gfc ) \
 551 do { \
 552     (header) &= ~GFC_MASK; \
 553     (header) |= (((gfc) << 28) & GFC_MASK); \
 554 } while(0)
 555
 556 /** Mask to acess VPI */
 557 #define VPI_MASK        0x0ff00000
 558
 559 /** return VPI from ATM cell header */
 560 #define IX_NPE_A_ATMCELLHEADER_VPI_GET( header ) \
 561 (((header) & VPI_MASK) >> 20)
 562
 563 /** set VPI into ATM cell header */
 564 #define IX_NPE_A_ATMCELLHEADER_VPI_SET( header, vpi ) \
 565 do { \
 566     (header) &= ~VPI_MASK; \
 567     (header) |= (((vpi) << 20) & VPI_MASK); \
 568 } while(0)
 569
 570 /** Mask to acess VCI */
 571 #define VCI_MASK        0x000ffff0
 572
 573 /** return VCI from ATM cell header */
 574 #define IX_NPE_A_ATMCELLHEADER_VCI_GET( header ) \
 575 (((header) & VCI_MASK) >> 4)
 576
 577 /** set VCI into ATM cell header */
 578 #define IX_NPE_A_ATMCELLHEADER_VCI_SET( header, vci ) \
 579 do { \
 580     (header) &= ~VCI_MASK; \
 581     (header) |= (((vci) << 4) & VCI_MASK); \
 582 } while(0)
 583
 584 /** Mask to acess PTI */
 585 #define PTI_MASK        0x0000000e
 586
 587 /** return PTI from ATM cell header */
 588 #define IX_NPE_A_ATMCELLHEADER_PTI_GET( header ) \
 589 (((header) & PTI_MASK) >> 1)
 590
 591 /** set PTI into ATM cell header */
 592 #define IX_NPE_A_ATMCELLHEADER_PTI_SET( header, pti ) \
 593 do { \
 594     (header) &= ~PTI_MASK; \
 595     (header) |= (((pti) << 1) & PTI_MASK); \
 596 } while(0)
 597
 598 /** Mask to acess CLP */
 599 #define CLP_MASK        0x00000001
 600
 601 /** return CLP from ATM cell header */
 602 #define IX_NPE_A_ATMCELLHEADER_CLP_GET( header ) \
 603 ((header) & CLP_MASK)
 604
 605 /** set CLP into ATM cell header */
 606 #define IX_NPE_A_ATMCELLHEADER_CLP_SET( header, clp ) \
 607 do { \
 608     (header) &= ~CLP_MASK; \
 609     (header) |= ((clp) & CLP_MASK); \
 610 } while(0)
 611
 612
 613 /*
 614 * Definition of the Rx bitfield
 615 *
 616 * This would most conviently be defined as the bit field shown below.
 617 * Endian portability prevents this, therefore a set of macros
 618 * are defined to access the fields within the rxBitfield assumed to
 619 * be passed as a UINT32.
 620 *
 621 * Changes to field sizes or orders must be reflected in the offset
 622 * definitions above.
 623 *
 624 * Rx bitfield
 625 *    struct
 626 *    {   IX_NPEA_RXBITFIELD(
 627 *        unsigned int status:1,
 628 *        unsigned int port:7,
 629 *        unsigned int vcId:8,
 630 *        unsigned int currMbufSize:16);
 631 *    } rxBitField;
 632 *
 633 */
 634
 635 /** Mask to acess the rxBitField status */
 636 #define STATUS_MASK     0x80000000
 637
 638 /** return the rxBitField status */
 639 #define IX_NPE_A_RXBITFIELD_STATUS_GET( rxbitfield ) \
 640 (((rxbitfield) & STATUS_MASK) >> 31)
 641
 642 /** set the rxBitField status */
 643 #define IX_NPE_A_RXBITFIELD_STATUS_SET( rxbitfield, status ) \
 644 do { \
 645     (rxbitfield) &= ~STATUS_MASK; \
 646     (rxbitfield) |= (((status) << 31) & STATUS_MASK); \
 647 } while(0)
 648
 649 /** Mask to acess the rxBitField port */
 650 #define PORT_MASK       0x7f000000
 651
 652 /** return the rxBitField port */
 653 #define IX_NPE_A_RXBITFIELD_PORT_GET( rxbitfield ) \
 654 (((rxbitfield) & PORT_MASK) >> 24)
 655
 656 /** set the rxBitField port */
 657 #define IX_NPE_A_RXBITFIELD_PORT_SET( rxbitfield, port ) \
 658 do { \
 659     (rxbitfield) &= ~PORT_MASK; \
 660     (rxbitfield) |= (((port) << 24) & PORT_MASK); \
 661 } while(0)
 662
 663 /** Mask to acess the rxBitField vcId */
 664 #define VCID_MASK       0x00ff0000
 665
 666 /** return the rxBitField vcId */
 667 #define IX_NPE_A_RXBITFIELD_VCID_GET( rxbitfield ) \
 668 (((rxbitfield) & VCID_MASK) >> 16)
 669
 670 /** set the rxBitField vcId */
 671 #define IX_NPE_A_RXBITFIELD_VCID_SET( rxbitfield, vcid ) \
 672 do { \
 673     (rxbitfield) &= ~VCID_MASK; \
 674     (rxbitfield) |= (((vcid) << 16) & VCID_MASK); \
 675 } while(0)
 676
 677 /** Mask to acess the rxBitField mbuf size */
 678 #define CURRMBUFSIZE_MASK       0x0000ffff
 679
 680 /** return the rxBitField mbuf size */
 681 #define IX_NPE_A_RXBITFIELD_CURRMBUFSIZE_GET( rxbitfield ) \
 682 ((rxbitfield) & CURRMBUFSIZE_MASK)
 683
 684 /** set the rxBitField mbuf size */
 685 #define IX_NPE_A_RXBITFIELD_CURRMBUFSIZE_SET( rxbitfield, currmbufsize ) \
 686 do { \
 687     (rxbitfield) &= ~CURRMBUFSIZE_MASK; \
 688     (rxbitfield) |= ((currmbufsize) & CURRMBUFSIZE_MASK); \
 689 } while(0)
 690
 691
 692
 693 /**
 694  * @brief Tx Descriptor definition
 695  */
 696 typedef struct
 697 {
 698     UINT8 port;                         /**< Tx Port number */
 699     UINT8 aalType;                      /**< AAL Type */
 700     UINT16 currMbufLen;                 /**< mbuf length */
 701     UINT32 atmCellHeader;               /**< ATM cell header */
 702     IX_OSAL_MBUF *pCurrMbuf;            /**< pointer to mbuf */
 703     unsigned char *pCurrMbufData;       /**< Pointer to mbuf->dat */
 704     IX_OSAL_MBUF *pNextMbuf;            /**< Pointer to next mbuf */
 705     UINT32  totalLen;                   /**< Total Length */
 706     UINT32  aal5CrcResidue;             /**< AAL5 CRC Residue */
 707 } IxNpeA_TxAtmVc;
 708
 709 /* Changes to field sizes or orders must be reflected in the offset
 710  * definitions above. */
 711
 712
 713
 714
 715 /**
 716  * @brief Rx Descriptor definition
 717  */
 718 typedef struct
 719 {
 720     UINT32  rxBitField;                 /**< Received bit field */
 721     UINT32  atmCellHeader;              /**< ATM Cell Header */
 722     UINT32  rsvdWord0;                  /**< Reserved field */
 723     UINT16  currMbufLen;                /**< Mbuf Length */
 724     UINT8   timeLimit;                  /**< Payload Reassembly timeLimit (used for aal0_xx only) */
 725     UINT8   rsvdByte0;                  /**< Reserved field */
 726     UINT32  rsvdWord1;                  /**< Reserved field */
 727     IX_OSAL_MBUF *pCurrMbuf;            /**< Pointer to current mbuf */
 728     unsigned char *pCurrMbufData;       /**< Pointer to current mbuf->data */
 729     IX_OSAL_MBUF *pNextMbuf;            /**< Pointer to next mbuf */
 730     UINT32  totalLen;                   /**< Total Length */
 731     UINT32  aal5CrcResidue;             /**< AAL5 CRC Residue */
 732 } IxNpeA_RxAtmVc;
 733
 734
 735 /**
 736  * @brief NPE-A AAL Type
 737  */
 738 typedef enum
 739 {
 740     IX_NPE_A_AAL_TYPE_INVALID = 0,      /**< Invalid AAL type */
 741     IX_NPE_A_AAL_TYPE_0_48    = 0x1,    /**< AAL0 - 48 byte */
 742     IX_NPE_A_AAL_TYPE_0_52    = 0x2,    /**< AAL0 - 52 byte */
 743     IX_NPE_A_AAL_TYPE_5       = 0x5,    /**< AAL5 */
 744     IX_NPE_A_AAL_TYPE_OAM     = 0xF     /**< OAM */
 745 } IxNpeA_AalType;
 746
 747 /**
 748  * @brief NPE-A Payload format 52-bytes & 48-bytes
 749  */
 750 typedef enum
 751 {
 752     IX_NPE_A_52_BYTE_PAYLOAD = 0,       /**< 52 byte payload */
 753     IX_NPE_A_48_BYTE_PAYLOAD            /**< 48 byte payload */
 754 } IxNpeA_PayloadFormat;
 755
 756 /**
 757  * @brief  HSS Packetized NpePacket Descriptor Structure
 758  */
 759 typedef struct
 760 {
 761     UINT8   status;             /**< Status of the packet passed to the client */
 762     UINT8   errorCount;         /**< Number of errors */
 763     UINT8   chainCount;         /**< Mbuf chain count e.g. 0 - No mbuf chain */
 764     UINT8   rsvdByte0;          /**< Reserved byte to make the descriptor word align */
 765
 766     UINT16  packetLength;       /**< Packet Length */
 767     UINT16  rsvdShort0;         /**< Reserved short to make the descriptor a word align */
 768
 769     IX_OSAL_MBUF *pRootMbuf;    /**< Pointer to Root mbuf */
 770     IX_OSAL_MBUF *pNextMbuf;    /**< Pointer to next mbuf */
 771     UINT8   *pMbufData;         /**< Pointer to the current mbuf->data */
 772     UINT32  mbufLength;         /**< Current mbuf length */
 773
 774 } IxNpeA_NpePacketDescriptor;
 775
 776
 777 #endif
 778 /**
 779  *@}
 780  */
 781
 782 #endif /* __doxygen_HIDE */