drivers/net/pcnet.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de.
   4  *
   5  * This driver for AMD PCnet network controllers is derived from the
   6  * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
   7  */
   8
   9 #include <common.h>
  10 #include <cpu_func.h>
  11 #include <malloc.h>
  12 #include <net.h>
  13 #include <netdev.h>
  14 #include <asm/io.h>
  15 #include <pci.h>
  16
  17 #define PCNET_DEBUG_LEVEL       0       /* 0=off, 1=init, 2=rx/tx */
  18
  19 #define PCNET_DEBUG1(fmt,args...)       \
  20         debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args)
  21 #define PCNET_DEBUG2(fmt,args...)       \
  22         debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args)
  23
  24 /*
  25  * Set the number of Tx and Rx buffers, using Log_2(# buffers).
  26  * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
  27  * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
  28  */
  29 #define PCNET_LOG_TX_BUFFERS    0
  30 #define PCNET_LOG_RX_BUFFERS    2
  31
  32 #define TX_RING_SIZE            (1 << (PCNET_LOG_TX_BUFFERS))
  33 #define TX_RING_LEN_BITS        ((PCNET_LOG_TX_BUFFERS) << 12)
  34
  35 #define RX_RING_SIZE            (1 << (PCNET_LOG_RX_BUFFERS))
  36 #define RX_RING_LEN_BITS        ((PCNET_LOG_RX_BUFFERS) << 4)
  37
  38 #define PKT_BUF_SZ              1544
  39
  40 /* The PCNET Rx and Tx ring descriptors. */
  41 struct pcnet_rx_head {
  42         u32 base;
  43         s16 buf_length;
  44         s16 status;
  45         u32 msg_length;
  46         u32 reserved;
  47 };
  48
  49 struct pcnet_tx_head {
  50         u32 base;
  51         s16 length;
  52         s16 status;
  53         u32 misc;
  54         u32 reserved;
  55 };
  56
  57 /* The PCNET 32-Bit initialization block, described in databook. */
  58 struct pcnet_init_block {
  59         u16 mode;
  60         u16 tlen_rlen;
  61         u8 phys_addr[6];
  62         u16 reserved;
  63         u32 filter[2];
  64         /* Receive and transmit ring base, along with extra bits. */
  65         u32 rx_ring;
  66         u32 tx_ring;
  67         u32 reserved2;
  68 };
  69
  70 struct pcnet_uncached_priv {
  71         struct pcnet_rx_head rx_ring[RX_RING_SIZE];
  72         struct pcnet_tx_head tx_ring[TX_RING_SIZE];
  73         struct pcnet_init_block init_block;
  74 };
  75
  76 typedef struct pcnet_priv {
  77         struct pcnet_uncached_priv *uc;
  78         /* Receive Buffer space */
  79         unsigned char (*rx_buf)[RX_RING_SIZE][PKT_BUF_SZ + 4];
  80         int cur_rx;
  81         int cur_tx;
  82 } pcnet_priv_t;
  83
  84 static pcnet_priv_t *lp;
  85
  86 /* Offsets from base I/O address for WIO mode */
  87 #define PCNET_RDP               0x10
  88 #define PCNET_RAP               0x12
  89 #define PCNET_RESET             0x14
  90 #define PCNET_BDP               0x16
  91
  92 static u16 pcnet_read_csr(struct eth_device *dev, int index)
  93 {
  94         void __iomem *base = (void __iomem *)dev->iobase;
  95
  96         writew(index, base + PCNET_RAP);
  97         return readw(base + PCNET_RDP);
  98 }
  99
 100 static void pcnet_write_csr(struct eth_device *dev, int index, u16 val)
 101 {
 102         void __iomem *base = (void __iomem *)dev->iobase;
 103
 104         writew(index, base + PCNET_RAP);
 105         writew(val, base + PCNET_RDP);
 106 }
 107
 108 static u16 pcnet_read_bcr(struct eth_device *dev, int index)
 109 {
 110         void __iomem *base = (void __iomem *)dev->iobase;
 111
 112         writew(index, base + PCNET_RAP);
 113         return readw(base + PCNET_BDP);
 114 }
 115
 116 static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val)
 117 {
 118         void __iomem *base = (void __iomem *)dev->iobase;
 119
 120         writew(index, base + PCNET_RAP);
 121         writew(val, base + PCNET_BDP);
 122 }
 123
 124 static void pcnet_reset(struct eth_device *dev)
 125 {
 126         void __iomem *base = (void __iomem *)dev->iobase;
 127
 128         readw(base + PCNET_RESET);
 129 }
 130
 131 static int pcnet_check(struct eth_device *dev)
 132 {
 133         void __iomem *base = (void __iomem *)dev->iobase;
 134
 135         writew(88, base + PCNET_RAP);
 136         return readw(base + PCNET_RAP) == 88;
 137 }
 138
 139 static int pcnet_init (struct eth_device *dev, bd_t * bis);
 140 static int pcnet_send(struct eth_device *dev, void *packet, int length);
 141 static int pcnet_recv (struct eth_device *dev);
 142 static void pcnet_halt (struct eth_device *dev);
 143 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
 144
 145 static inline pci_addr_t pcnet_virt_to_mem(const struct eth_device *dev,
 146                                                 void *addr)
 147 {
 148         pci_dev_t devbusfn = (pci_dev_t)(unsigned long)dev->priv;
 149         void *virt_addr = addr;
 150
 151         return pci_virt_to_mem(devbusfn, virt_addr);
 152 }
 153
 154 static struct pci_device_id supported[] = {
 155         {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE},
 156         {}
 157 };
 158
 159
 160 int pcnet_initialize(bd_t *bis)
 161 {
 162         pci_dev_t devbusfn;
 163         struct eth_device *dev;
 164         u16 command, status;
 165         int dev_nr = 0;
 166         u32 bar;
 167
 168         PCNET_DEBUG1("\npcnet_initialize...\n");
 169
 170         for (dev_nr = 0;; dev_nr++) {
 171
 172                 /*
 173                  * Find the PCnet PCI device(s).
 174                  */
 175                 devbusfn = pci_find_devices(supported, dev_nr);
 176                 if (devbusfn < 0)
 177                         break;
 178
 179                 /*
 180                  * Allocate and pre-fill the device structure.
 181                  */
 182                 dev = (struct eth_device *)malloc(sizeof(*dev));
 183                 if (!dev) {
 184                         printf("pcnet: Can not allocate memory\n");
 185                         break;
 186                 }
 187                 memset(dev, 0, sizeof(*dev));
 188                 dev->priv = (void *)(unsigned long)devbusfn;
 189                 sprintf(dev->name, "pcnet#%d", dev_nr);
 190
 191                 /*
 192                  * Setup the PCI device.
 193                  */
 194                 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &bar);
 195                 dev->iobase = pci_mem_to_phys(devbusfn, bar);
 196                 dev->iobase &= ~0xf;
 197
 198                 PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%lx: ",
 199                              dev->name, devbusfn, (unsigned long)dev->iobase);
 200
 201                 command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 202                 pci_write_config_word(devbusfn, PCI_COMMAND, command);
 203                 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
 204                 if ((status & command) != command) {
 205                         printf("%s: Couldn't enable IO access or Bus Mastering\n",
 206                                dev->name);
 207                         free(dev);
 208                         continue;
 209                 }
 210
 211                 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
 212
 213                 /*
 214                  * Probe the PCnet chip.
 215                  */
 216                 if (pcnet_probe(dev, bis, dev_nr) < 0) {
 217                         free(dev);
 218                         continue;
 219                 }
 220
 221                 /*
 222                  * Setup device structure and register the driver.
 223                  */
 224                 dev->init = pcnet_init;
 225                 dev->halt = pcnet_halt;
 226                 dev->send = pcnet_send;
 227                 dev->recv = pcnet_recv;
 228
 229                 eth_register(dev);
 230         }
 231
 232         udelay(10 * 1000);
 233
 234         return dev_nr;
 235 }
 236
 237 static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr)
 238 {
 239         int chip_version;
 240         char *chipname;
 241
 242 #ifdef PCNET_HAS_PROM
 243         int i;
 244 #endif
 245
 246         /* Reset the PCnet controller */
 247         pcnet_reset(dev);
 248
 249         /* Check if register access is working */
 250         if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) {
 251                 printf("%s: CSR register access check failed\n", dev->name);
 252                 return -1;
 253         }
 254
 255         /* Identify the chip */
 256         chip_version =
 257                 pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev, 89) << 16);
 258         if ((chip_version & 0xfff) != 0x003)
 259                 return -1;
 260         chip_version = (chip_version >> 12) & 0xffff;
 261         switch (chip_version) {
 262         case 0x2621:
 263                 chipname = "PCnet/PCI II 79C970A";      /* PCI */
 264                 break;
 265         case 0x2625:
 266                 chipname = "PCnet/FAST III 79C973";     /* PCI */
 267                 break;
 268         case 0x2627:
 269                 chipname = "PCnet/FAST III 79C975";     /* PCI */
 270                 break;
 271         default:
 272                 printf("%s: PCnet version %#x not supported\n",
 273                        dev->name, chip_version);
 274                 return -1;
 275         }
 276
 277         PCNET_DEBUG1("AMD %s\n", chipname);
 278
 279 #ifdef PCNET_HAS_PROM
 280         /*
 281          * In most chips, after a chip reset, the ethernet address is read from
 282          * the station address PROM at the base address and programmed into the
 283          * "Physical Address Registers" CSR12-14.
 284          */
 285         for (i = 0; i < 3; i++) {
 286                 unsigned int val;
 287
 288                 val = pcnet_read_csr(dev, i + 12) & 0x0ffff;
 289                 /* There may be endianness issues here. */
 290                 dev->enetaddr[2 * i] = val & 0x0ff;
 291                 dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
 292         }
 293 #endif /* PCNET_HAS_PROM */
 294
 295         return 0;
 296 }
 297
 298 static int pcnet_init(struct eth_device *dev, bd_t *bis)
 299 {
 300         struct pcnet_uncached_priv *uc;
 301         int i, val;
 302         unsigned long addr;
 303
 304         PCNET_DEBUG1("%s: pcnet_init...\n", dev->name);
 305
 306         /* Switch pcnet to 32bit mode */
 307         pcnet_write_bcr(dev, 20, 2);
 308
 309         /* Set/reset autoselect bit */
 310         val = pcnet_read_bcr(dev, 2) & ~2;
 311         val |= 2;
 312         pcnet_write_bcr(dev, 2, val);
 313
 314         /* Enable auto negotiate, setup, disable fd */
 315         val = pcnet_read_bcr(dev, 32) & ~0x98;
 316         val |= 0x20;
 317         pcnet_write_bcr(dev, 32, val);
 318
 319         /*
 320          * Enable NOUFLO on supported controllers, with the transmit
 321          * start point set to the full packet. This will cause entire
 322          * packets to be buffered by the ethernet controller before
 323          * transmission, eliminating underflows which are common on
 324          * slower devices. Controllers which do not support NOUFLO will
 325          * simply be left with a larger transmit FIFO threshold.
 326          */
 327         val = pcnet_read_bcr(dev, 18);
 328         val |= 1 << 11;
 329         pcnet_write_bcr(dev, 18, val);
 330         val = pcnet_read_csr(dev, 80);
 331         val |= 0x3 << 10;
 332         pcnet_write_csr(dev, 80, val);
 333
 334         /*
 335          * We only maintain one structure because the drivers will never
 336          * be used concurrently. In 32bit mode the RX and TX ring entries
 337          * must be aligned on 16-byte boundaries.
 338          */
 339         if (lp == NULL) {
 340                 addr = (unsigned long)malloc(sizeof(pcnet_priv_t) + 0x10);
 341                 addr = (addr + 0xf) & ~0xf;
 342                 lp = (pcnet_priv_t *)addr;
 343
 344                 addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
 345                                                sizeof(*lp->uc));
 346                 flush_dcache_range(addr, addr + sizeof(*lp->uc));
 347                 addr = (unsigned long)map_physmem(addr,
 348                                 roundup(sizeof(*lp->uc), ARCH_DMA_MINALIGN),
 349                                 MAP_NOCACHE);
 350                 lp->uc = (struct pcnet_uncached_priv *)addr;
 351
 352                 addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
 353                                                sizeof(*lp->rx_buf));
 354                 flush_dcache_range(addr, addr + sizeof(*lp->rx_buf));
 355                 lp->rx_buf = (void *)addr;
 356         }
 357
 358         uc = lp->uc;
 359
 360         uc->init_block.mode = cpu_to_le16(0x0000);
 361         uc->init_block.filter[0] = 0x00000000;
 362         uc->init_block.filter[1] = 0x00000000;
 363
 364         /*
 365          * Initialize the Rx ring.
 366          */
 367         lp->cur_rx = 0;
 368         for (i = 0; i < RX_RING_SIZE; i++) {
 369                 addr = pcnet_virt_to_mem(dev, (*lp->rx_buf)[i]);
 370                 uc->rx_ring[i].base = cpu_to_le32(addr);
 371                 uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
 372                 uc->rx_ring[i].status = cpu_to_le16(0x8000);
 373                 PCNET_DEBUG1
 374                         ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
 375                          uc->rx_ring[i].base, uc->rx_ring[i].buf_length,
 376                          uc->rx_ring[i].status);
 377         }
 378
 379         /*
 380          * Initialize the Tx ring. The Tx buffer address is filled in as
 381          * needed, but we do need to clear the upper ownership bit.
 382          */
 383         lp->cur_tx = 0;
 384         for (i = 0; i < TX_RING_SIZE; i++) {
 385                 uc->tx_ring[i].base = 0;
 386                 uc->tx_ring[i].status = 0;
 387         }
 388
 389         /*
 390          * Setup Init Block.
 391          */
 392         PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block);
 393
 394         for (i = 0; i < 6; i++) {
 395                 lp->uc->init_block.phys_addr[i] = dev->enetaddr[i];
 396                 PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]);
 397         }
 398
 399         uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
 400                                                RX_RING_LEN_BITS);
 401         addr = pcnet_virt_to_mem(dev, uc->rx_ring);
 402         uc->init_block.rx_ring = cpu_to_le32(addr);
 403         addr = pcnet_virt_to_mem(dev, uc->tx_ring);
 404         uc->init_block.tx_ring = cpu_to_le32(addr);
 405
 406         PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
 407                      uc->init_block.tlen_rlen,
 408                      uc->init_block.rx_ring, uc->init_block.tx_ring);
 409
 410         /*
 411          * Tell the controller where the Init Block is located.
 412          */
 413         barrier();
 414         addr = pcnet_virt_to_mem(dev, &lp->uc->init_block);
 415         pcnet_write_csr(dev, 1, addr & 0xffff);
 416         pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff);
 417
 418         pcnet_write_csr(dev, 4, 0x0915);
 419         pcnet_write_csr(dev, 0, 0x0001);        /* start */
 420
 421         /* Wait for Init Done bit */
 422         for (i = 10000; i > 0; i--) {
 423                 if (pcnet_read_csr(dev, 0) & 0x0100)
 424                         break;
 425                 udelay(10);
 426         }
 427         if (i <= 0) {
 428                 printf("%s: TIMEOUT: controller init failed\n", dev->name);
 429                 pcnet_reset(dev);
 430                 return -1;
 431         }
 432
 433         /*
 434          * Finally start network controller operation.
 435          */
 436         pcnet_write_csr(dev, 0, 0x0002);
 437
 438         return 0;
 439 }
 440
 441 static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
 442 {
 443         int i, status;
 444         u32 addr;
 445         struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx];
 446
 447         PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
 448                      packet);
 449
 450         flush_dcache_range((unsigned long)packet,
 451                            (unsigned long)packet + pkt_len);
 452
 453         /* Wait for completion by testing the OWN bit */
 454         for (i = 1000; i > 0; i--) {
 455                 status = readw(&entry->status);
 456                 if ((status & 0x8000) == 0)
 457                         break;
 458                 udelay(100);
 459                 PCNET_DEBUG2(".");
 460         }
 461         if (i <= 0) {
 462                 printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
 463                        dev->name, lp->cur_tx, status);
 464                 pkt_len = 0;
 465                 goto failure;
 466         }
 467
 468         /*
 469          * Setup Tx ring. Caution: the write order is important here,
 470          * set the status with the "ownership" bits last.
 471          */
 472         addr = pcnet_virt_to_mem(dev, packet);
 473         writew(-pkt_len, &entry->length);
 474         writel(0, &entry->misc);
 475         writel(addr, &entry->base);
 476         writew(0x8300, &entry->status);
 477
 478         /* Trigger an immediate send poll. */
 479         pcnet_write_csr(dev, 0, 0x0008);
 480
 481       failure:
 482         if (++lp->cur_tx >= TX_RING_SIZE)
 483                 lp->cur_tx = 0;
 484
 485         PCNET_DEBUG2("done\n");
 486         return pkt_len;
 487 }
 488
 489 static int pcnet_recv (struct eth_device *dev)
 490 {
 491         struct pcnet_rx_head *entry;
 492         unsigned char *buf;
 493         int pkt_len = 0;
 494         u16 status, err_status;
 495
 496         while (1) {
 497                 entry = &lp->uc->rx_ring[lp->cur_rx];
 498                 /*
 499                  * If we own the next entry, it's a new packet. Send it up.
 500                  */
 501                 status = readw(&entry->status);
 502                 if ((status & 0x8000) != 0)
 503                         break;
 504                 err_status = status >> 8;
 505
 506                 if (err_status != 0x03) {       /* There was an error. */
 507                         printf("%s: Rx%d", dev->name, lp->cur_rx);
 508                         PCNET_DEBUG1(" (status=0x%x)", err_status);
 509                         if (err_status & 0x20)
 510                                 printf(" Frame");
 511                         if (err_status & 0x10)
 512                                 printf(" Overflow");
 513                         if (err_status & 0x08)
 514                                 printf(" CRC");
 515                         if (err_status & 0x04)
 516                                 printf(" Fifo");
 517                         printf(" Error\n");
 518                         status &= 0x03ff;
 519
 520                 } else {
 521                         pkt_len = (readl(&entry->msg_length) & 0xfff) - 4;
 522                         if (pkt_len < 60) {
 523                                 printf("%s: Rx%d: invalid packet length %d\n",
 524                                        dev->name, lp->cur_rx, pkt_len);
 525                         } else {
 526                                 buf = (*lp->rx_buf)[lp->cur_rx];
 527                                 invalidate_dcache_range((unsigned long)buf,
 528                                         (unsigned long)buf + pkt_len);
 529                                 net_process_received_packet(buf, pkt_len);
 530                                 PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
 531                                              lp->cur_rx, pkt_len, buf);
 532                         }
 533                 }
 534
 535                 status |= 0x8000;
 536                 writew(status, &entry->status);
 537
 538                 if (++lp->cur_rx >= RX_RING_SIZE)
 539                         lp->cur_rx = 0;
 540         }
 541         return pkt_len;
 542 }
 543
 544 static void pcnet_halt(struct eth_device *dev)
 545 {
 546         int i;
 547
 548         PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name);
 549
 550         /* Reset the PCnet controller */
 551         pcnet_reset(dev);
 552
 553         /* Wait for Stop bit */
 554         for (i = 1000; i > 0; i--) {
 555                 if (pcnet_read_csr(dev, 0) & 0x4)
 556                         break;
 557                 udelay(10);
 558         }
 559         if (i <= 0)
 560                 printf("%s: TIMEOUT: controller reset failed\n", dev->name);
 561 }