4 * SPDX-License-Identifier: GPL-2.0+
6 * Copyright 2010-2011 Freescale Semiconductor, Inc.
13 #define PHY_AUTONEGOTIATE_TIMEOUT 5000
15 /* 88E1011 PHY Status Register */
16 #define MIIM_88E1xxx_PHY_STATUS 0x11
17 #define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000
18 #define MIIM_88E1xxx_PHYSTAT_GBIT 0x8000
19 #define MIIM_88E1xxx_PHYSTAT_100 0x4000
20 #define MIIM_88E1xxx_PHYSTAT_DUPLEX 0x2000
21 #define MIIM_88E1xxx_PHYSTAT_SPDDONE 0x0800
22 #define MIIM_88E1xxx_PHYSTAT_LINK 0x0400
24 #define MIIM_88E1xxx_PHY_SCR 0x10
25 #define MIIM_88E1xxx_PHY_MDI_X_AUTO 0x0060
27 /* 88E1111 PHY LED Control Register */
28 #define MIIM_88E1111_PHY_LED_CONTROL 24
29 #define MIIM_88E1111_PHY_LED_DIRECT 0x4100
30 #define MIIM_88E1111_PHY_LED_COMBINE 0x411C
32 /* 88E1111 Extended PHY Specific Control Register */
33 #define MIIM_88E1111_PHY_EXT_CR 0x14
34 #define MIIM_88E1111_RX_DELAY 0x80
35 #define MIIM_88E1111_TX_DELAY 0x2
37 /* 88E1111 Extended PHY Specific Status Register */
38 #define MIIM_88E1111_PHY_EXT_SR 0x1b
39 #define MIIM_88E1111_HWCFG_MODE_MASK 0xf
40 #define MIIM_88E1111_HWCFG_MODE_COPPER_RGMII 0xb
41 #define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII 0x3
42 #define MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK 0x4
43 #define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI 0x9
44 #define MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO 0x8000
45 #define MIIM_88E1111_HWCFG_FIBER_COPPER_RES 0x2000
47 #define MIIM_88E1111_COPPER 0
48 #define MIIM_88E1111_FIBER 1
50 /* 88E1118 PHY defines */
51 #define MIIM_88E1118_PHY_PAGE 22
52 #define MIIM_88E1118_PHY_LED_PAGE 3
54 /* 88E1121 PHY LED Control Register */
55 #define MIIM_88E1121_PHY_LED_CTRL 16
56 #define MIIM_88E1121_PHY_LED_PAGE 3
57 #define MIIM_88E1121_PHY_LED_DEF 0x0030
59 /* 88E1121 PHY IRQ Enable/Status Register */
60 #define MIIM_88E1121_PHY_IRQ_EN 18
61 #define MIIM_88E1121_PHY_IRQ_STATUS 19
63 #define MIIM_88E1121_PHY_PAGE 22
65 /* 88E1145 Extended PHY Specific Control Register */
66 #define MIIM_88E1145_PHY_EXT_CR 20
67 #define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
68 #define MIIM_M88E1145_RGMII_TX_DELAY 0x0002
70 #define MIIM_88E1145_PHY_LED_CONTROL 24
71 #define MIIM_88E1145_PHY_LED_DIRECT 0x4100
73 #define MIIM_88E1145_PHY_PAGE 29
74 #define MIIM_88E1145_PHY_CAL_OV 30
76 #define MIIM_88E1149_PHY_PAGE 29
78 /* 88E1310 PHY defines */
79 #define MIIM_88E1310_PHY_LED_CTRL 16
80 #define MIIM_88E1310_PHY_IRQ_EN 18
81 #define MIIM_88E1310_PHY_RGMII_CTRL 21
82 #define MIIM_88E1310_PHY_PAGE 22
84 /* Marvell 88E1011S */
85 static int m88e1011s_config(struct phy_device
*phydev
)
87 /* Reset and configure the PHY */
88 phy_write(phydev
, MDIO_DEVAD_NONE
, MII_BMCR
, BMCR_RESET
);
90 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1d, 0x1f);
91 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1e, 0x200c);
92 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1d, 0x5);
93 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1e, 0);
94 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1e, 0x100);
96 phy_write(phydev
, MDIO_DEVAD_NONE
, MII_BMCR
, BMCR_RESET
);
98 genphy_config_aneg(phydev
);
103 /* Parse the 88E1011's status register for speed and duplex
106 static uint
m88e1xxx_parse_status(struct phy_device
*phydev
)
109 unsigned int mii_reg
;
111 mii_reg
= phy_read(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1xxx_PHY_STATUS
);
113 if ((mii_reg
& MIIM_88E1xxx_PHYSTAT_LINK
) &&
114 !(mii_reg
& MIIM_88E1xxx_PHYSTAT_SPDDONE
)) {
117 puts("Waiting for PHY realtime link");
118 while (!(mii_reg
& MIIM_88E1xxx_PHYSTAT_SPDDONE
)) {
119 /* Timeout reached ? */
120 if (i
> PHY_AUTONEGOTIATE_TIMEOUT
) {
121 puts(" TIMEOUT !\n");
126 if ((i
++ % 1000) == 0)
129 mii_reg
= phy_read(phydev
, MDIO_DEVAD_NONE
,
130 MIIM_88E1xxx_PHY_STATUS
);
133 udelay(500000); /* another 500 ms (results in faster booting) */
135 if (mii_reg
& MIIM_88E1xxx_PHYSTAT_LINK
)
141 if (mii_reg
& MIIM_88E1xxx_PHYSTAT_DUPLEX
)
142 phydev
->duplex
= DUPLEX_FULL
;
144 phydev
->duplex
= DUPLEX_HALF
;
146 speed
= mii_reg
& MIIM_88E1xxx_PHYSTAT_SPEED
;
149 case MIIM_88E1xxx_PHYSTAT_GBIT
:
150 phydev
->speed
= SPEED_1000
;
152 case MIIM_88E1xxx_PHYSTAT_100
:
153 phydev
->speed
= SPEED_100
;
156 phydev
->speed
= SPEED_10
;
163 static int m88e1011s_startup(struct phy_device
*phydev
)
165 genphy_update_link(phydev
);
166 m88e1xxx_parse_status(phydev
);
171 /* Marvell 88E1111S */
172 static int m88e1111s_config(struct phy_device
*phydev
)
176 if ((phydev
->interface
== PHY_INTERFACE_MODE_RGMII
) ||
177 (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_ID
) ||
178 (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_RXID
) ||
179 (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_TXID
)) {
180 reg
= phy_read(phydev
,
181 MDIO_DEVAD_NONE
, MIIM_88E1111_PHY_EXT_CR
);
182 if ((phydev
->interface
== PHY_INTERFACE_MODE_RGMII
) ||
183 (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_ID
)) {
184 reg
|= (MIIM_88E1111_RX_DELAY
| MIIM_88E1111_TX_DELAY
);
185 } else if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_RXID
) {
186 reg
&= ~MIIM_88E1111_TX_DELAY
;
187 reg
|= MIIM_88E1111_RX_DELAY
;
188 } else if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_TXID
) {
189 reg
&= ~MIIM_88E1111_RX_DELAY
;
190 reg
|= MIIM_88E1111_TX_DELAY
;
194 MDIO_DEVAD_NONE
, MIIM_88E1111_PHY_EXT_CR
, reg
);
196 reg
= phy_read(phydev
,
197 MDIO_DEVAD_NONE
, MIIM_88E1111_PHY_EXT_SR
);
199 reg
&= ~(MIIM_88E1111_HWCFG_MODE_MASK
);
201 if (reg
& MIIM_88E1111_HWCFG_FIBER_COPPER_RES
)
202 reg
|= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII
;
204 reg
|= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII
;
207 MDIO_DEVAD_NONE
, MIIM_88E1111_PHY_EXT_SR
, reg
);
210 if (phydev
->interface
== PHY_INTERFACE_MODE_SGMII
) {
211 reg
= phy_read(phydev
,
212 MDIO_DEVAD_NONE
, MIIM_88E1111_PHY_EXT_SR
);
214 reg
&= ~(MIIM_88E1111_HWCFG_MODE_MASK
);
215 reg
|= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK
;
216 reg
|= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO
;
218 phy_write(phydev
, MDIO_DEVAD_NONE
,
219 MIIM_88E1111_PHY_EXT_SR
, reg
);
222 if (phydev
->interface
== PHY_INTERFACE_MODE_RTBI
) {
223 reg
= phy_read(phydev
,
224 MDIO_DEVAD_NONE
, MIIM_88E1111_PHY_EXT_CR
);
225 reg
|= (MIIM_88E1111_RX_DELAY
| MIIM_88E1111_TX_DELAY
);
227 MDIO_DEVAD_NONE
, MIIM_88E1111_PHY_EXT_CR
, reg
);
229 reg
= phy_read(phydev
, MDIO_DEVAD_NONE
,
230 MIIM_88E1111_PHY_EXT_SR
);
231 reg
&= ~(MIIM_88E1111_HWCFG_MODE_MASK
|
232 MIIM_88E1111_HWCFG_FIBER_COPPER_RES
);
233 reg
|= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO
;
234 phy_write(phydev
, MDIO_DEVAD_NONE
,
235 MIIM_88E1111_PHY_EXT_SR
, reg
);
240 reg
= phy_read(phydev
, MDIO_DEVAD_NONE
,
241 MIIM_88E1111_PHY_EXT_SR
);
242 reg
&= ~(MIIM_88E1111_HWCFG_MODE_MASK
|
243 MIIM_88E1111_HWCFG_FIBER_COPPER_RES
);
244 reg
|= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI
|
245 MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO
;
246 phy_write(phydev
, MDIO_DEVAD_NONE
,
247 MIIM_88E1111_PHY_EXT_SR
, reg
);
253 genphy_config_aneg(phydev
);
261 * m88e1518_phy_writebits - write bits to a register
263 void m88e1518_phy_writebits(struct phy_device
*phydev
,
264 u8 reg_num
, u16 offset
, u16 len
, u16 data
)
268 if ((len
+ offset
) >= 16)
269 mask
= 0 - (1 << offset
);
271 mask
= (1 << (len
+ offset
)) - (1 << offset
);
273 reg
= phy_read(phydev
, MDIO_DEVAD_NONE
, reg_num
);
276 reg
|= data
<< offset
;
278 phy_write(phydev
, MDIO_DEVAD_NONE
, reg_num
, reg
);
281 static int m88e1518_config(struct phy_device
*phydev
)
284 * As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512
285 * /88E1514 Rev A0, Errata Section 3.1
288 /* EEE initialization */
289 phy_write(phydev
, MDIO_DEVAD_NONE
, 22, 0x00ff);
290 phy_write(phydev
, MDIO_DEVAD_NONE
, 17, 0x214B);
291 phy_write(phydev
, MDIO_DEVAD_NONE
, 16, 0x2144);
292 phy_write(phydev
, MDIO_DEVAD_NONE
, 17, 0x0C28);
293 phy_write(phydev
, MDIO_DEVAD_NONE
, 16, 0x2146);
294 phy_write(phydev
, MDIO_DEVAD_NONE
, 17, 0xB233);
295 phy_write(phydev
, MDIO_DEVAD_NONE
, 16, 0x214D);
296 phy_write(phydev
, MDIO_DEVAD_NONE
, 17, 0xCC0C);
297 phy_write(phydev
, MDIO_DEVAD_NONE
, 16, 0x2159);
298 phy_write(phydev
, MDIO_DEVAD_NONE
, 22, 0x0000);
300 /* SGMII-to-Copper mode initialization */
301 if (phydev
->interface
== PHY_INTERFACE_MODE_SGMII
) {
303 phy_write(phydev
, MDIO_DEVAD_NONE
, 22, 18);
305 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
306 m88e1518_phy_writebits(phydev
, 20, 0, 3, 1);
308 /* PHY reset is necessary after changing MODE[2:0] */
309 m88e1518_phy_writebits(phydev
, 20, 15, 1, 1);
311 /* Reset page selection */
312 phy_write(phydev
, MDIO_DEVAD_NONE
, 22, 0);
317 return m88e1111s_config(phydev
);
320 /* Marvell 88E1510 */
321 static int m88e1510_config(struct phy_device
*phydev
)
324 phy_write(phydev
, MDIO_DEVAD_NONE
, 22, 3);
326 /* Enable INTn output on LED[2] */
327 m88e1518_phy_writebits(phydev
, 18, 7, 1, 1);
330 m88e1518_phy_writebits(phydev
, 16, 0, 4, 3); /* LED[0]:0011 (ACT) */
331 m88e1518_phy_writebits(phydev
, 16, 4, 4, 6); /* LED[1]:0110 (LINK) */
333 /* Reset page selection */
334 phy_write(phydev
, MDIO_DEVAD_NONE
, 22, 0);
336 return m88e1518_config(phydev
);
339 /* Marvell 88E1118 */
340 static int m88e1118_config(struct phy_device
*phydev
)
342 /* Change Page Number */
343 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1118_PHY_PAGE
, 0x0002);
344 /* Delay RGMII TX and RX */
345 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x15, 0x1070);
346 /* Change Page Number */
347 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1118_PHY_PAGE
, 0x0003);
348 /* Adjust LED control */
349 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x10, 0x021e);
350 /* Change Page Number */
351 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1118_PHY_PAGE
, 0x0000);
353 genphy_config_aneg(phydev
);
360 static int m88e1118_startup(struct phy_device
*phydev
)
362 /* Change Page Number */
363 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1118_PHY_PAGE
, 0x0000);
365 genphy_update_link(phydev
);
366 m88e1xxx_parse_status(phydev
);
371 /* Marvell 88E1121R */
372 static int m88e1121_config(struct phy_device
*phydev
)
376 /* Configure the PHY */
377 genphy_config_aneg(phydev
);
379 /* Switch the page to access the led register */
380 pg
= phy_read(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1121_PHY_PAGE
);
381 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1121_PHY_PAGE
,
382 MIIM_88E1121_PHY_LED_PAGE
);
384 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1121_PHY_LED_CTRL
,
385 MIIM_88E1121_PHY_LED_DEF
);
386 /* Restore the page pointer */
387 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1121_PHY_PAGE
, pg
);
389 /* Disable IRQs and de-assert interrupt */
390 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1121_PHY_IRQ_EN
, 0);
391 phy_read(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1121_PHY_IRQ_STATUS
);
396 /* Marvell 88E1145 */
397 static int m88e1145_config(struct phy_device
*phydev
)
402 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1145_PHY_PAGE
, 0x001b);
403 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1145_PHY_CAL_OV
, 0x418f);
404 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1145_PHY_PAGE
, 0x0016);
405 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1145_PHY_CAL_OV
, 0xa2da);
407 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1xxx_PHY_SCR
,
408 MIIM_88E1xxx_PHY_MDI_X_AUTO
);
410 reg
= phy_read(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1145_PHY_EXT_CR
);
411 if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_ID
)
412 reg
|= MIIM_M88E1145_RGMII_RX_DELAY
|
413 MIIM_M88E1145_RGMII_TX_DELAY
;
414 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1145_PHY_EXT_CR
, reg
);
416 genphy_config_aneg(phydev
);
423 static int m88e1145_startup(struct phy_device
*phydev
)
425 genphy_update_link(phydev
);
426 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1145_PHY_LED_CONTROL
,
427 MIIM_88E1145_PHY_LED_DIRECT
);
428 m88e1xxx_parse_status(phydev
);
433 /* Marvell 88E1149S */
434 static int m88e1149_config(struct phy_device
*phydev
)
436 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1149_PHY_PAGE
, 0x1f);
437 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1e, 0x200c);
438 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1149_PHY_PAGE
, 0x5);
439 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1e, 0x0);
440 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1e, 0x100);
442 genphy_config_aneg(phydev
);
449 /* Marvell 88E1310 */
450 static int m88e1310_config(struct phy_device
*phydev
)
454 /* LED link and activity */
455 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1310_PHY_PAGE
, 0x0003);
456 reg
= phy_read(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1310_PHY_LED_CTRL
);
457 reg
= (reg
& ~0xf) | 0x1;
458 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1310_PHY_LED_CTRL
, reg
);
460 /* Set LED2/INT to INT mode, low active */
461 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1310_PHY_PAGE
, 0x0003);
462 reg
= phy_read(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1310_PHY_IRQ_EN
);
463 reg
= (reg
& 0x77ff) | 0x0880;
464 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1310_PHY_IRQ_EN
, reg
);
466 /* Set RGMII delay */
467 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1310_PHY_PAGE
, 0x0002);
468 reg
= phy_read(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1310_PHY_RGMII_CTRL
);
470 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1310_PHY_RGMII_CTRL
, reg
);
472 /* Ensure to return to page 0 */
473 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_88E1310_PHY_PAGE
, 0x0000);
475 genphy_config_aneg(phydev
);
481 static struct phy_driver M88E1011S_driver
= {
482 .name
= "Marvell 88E1011S",
485 .features
= PHY_GBIT_FEATURES
,
486 .config
= &m88e1011s_config
,
487 .startup
= &m88e1011s_startup
,
488 .shutdown
= &genphy_shutdown
,
491 static struct phy_driver M88E1111S_driver
= {
492 .name
= "Marvell 88E1111S",
495 .features
= PHY_GBIT_FEATURES
,
496 .config
= &m88e1111s_config
,
497 .startup
= &m88e1011s_startup
,
498 .shutdown
= &genphy_shutdown
,
501 static struct phy_driver M88E1118_driver
= {
502 .name
= "Marvell 88E1118",
505 .features
= PHY_GBIT_FEATURES
,
506 .config
= &m88e1118_config
,
507 .startup
= &m88e1118_startup
,
508 .shutdown
= &genphy_shutdown
,
511 static struct phy_driver M88E1118R_driver
= {
512 .name
= "Marvell 88E1118R",
515 .features
= PHY_GBIT_FEATURES
,
516 .config
= &m88e1118_config
,
517 .startup
= &m88e1118_startup
,
518 .shutdown
= &genphy_shutdown
,
521 static struct phy_driver M88E1121R_driver
= {
522 .name
= "Marvell 88E1121R",
525 .features
= PHY_GBIT_FEATURES
,
526 .config
= &m88e1121_config
,
527 .startup
= &genphy_startup
,
528 .shutdown
= &genphy_shutdown
,
531 static struct phy_driver M88E1145_driver
= {
532 .name
= "Marvell 88E1145",
535 .features
= PHY_GBIT_FEATURES
,
536 .config
= &m88e1145_config
,
537 .startup
= &m88e1145_startup
,
538 .shutdown
= &genphy_shutdown
,
541 static struct phy_driver M88E1149S_driver
= {
542 .name
= "Marvell 88E1149S",
545 .features
= PHY_GBIT_FEATURES
,
546 .config
= &m88e1149_config
,
547 .startup
= &m88e1011s_startup
,
548 .shutdown
= &genphy_shutdown
,
551 static struct phy_driver M88E1510_driver
= {
552 .name
= "Marvell 88E1510",
555 .features
= PHY_GBIT_FEATURES
,
556 .config
= &m88e1510_config
,
557 .startup
= &m88e1011s_startup
,
558 .shutdown
= &genphy_shutdown
,
561 static struct phy_driver M88E1518_driver
= {
562 .name
= "Marvell 88E1518",
565 .features
= PHY_GBIT_FEATURES
,
566 .config
= &m88e1518_config
,
567 .startup
= &m88e1011s_startup
,
568 .shutdown
= &genphy_shutdown
,
571 static struct phy_driver M88E1310_driver
= {
572 .name
= "Marvell 88E1310",
575 .features
= PHY_GBIT_FEATURES
,
576 .config
= &m88e1310_config
,
577 .startup
= &m88e1011s_startup
,
578 .shutdown
= &genphy_shutdown
,
581 int phy_marvell_init(void)
583 phy_register(&M88E1310_driver
);
584 phy_register(&M88E1149S_driver
);
585 phy_register(&M88E1145_driver
);
586 phy_register(&M88E1121R_driver
);
587 phy_register(&M88E1118_driver
);
588 phy_register(&M88E1118R_driver
);
589 phy_register(&M88E1111S_driver
);
590 phy_register(&M88E1011S_driver
);
591 phy_register(&M88E1510_driver
);
592 phy_register(&M88E1518_driver
);