drivers/net/phy/marvell10g.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Marvell 10G 88x3310 PHY driver
   4  *
   5  * Based upon the ID registers, this PHY appears to be a mixture of IPs
   6  * from two different companies.
   7  *
   8  * There appears to be several different data paths through the PHY which
   9  * are automatically managed by the PHY.  The following has been determined
  10  * via observation and experimentation for a setup using single-lane Serdes:
  11  *
  12  *       SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
  13  *  10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
  14  *  10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
  15  *
  16  * With XAUI, observation shows:
  17  *
  18  *        XAUI PHYXS -- <appropriate PCS as above>
  19  *
  20  * and no switching of the host interface mode occurs.
  21  *
  22  * If both the fiber and copper ports are connected, the first to gain
  23  * link takes priority and the other port is completely locked out.
  24  */
  25 #include <linux/ctype.h>
  26 #include <linux/delay.h>
  27 #include <linux/hwmon.h>
  28 #include <linux/marvell_phy.h>
  29 #include <linux/phy.h>
  30 #include <linux/sfp.h>
  31
  32 #define MV_PHY_ALASKA_NBT_QUIRK_MASK    0xfffffffe
  33 #define MV_PHY_ALASKA_NBT_QUIRK_REV     (MARVELL_PHY_ID_88X3310 | 0xa)
  34
  35 enum {
  36         MV_PMA_BOOT             = 0xc050,
  37         MV_PMA_BOOT_FATAL       = BIT(0),
  38
  39         MV_PCS_BASE_T           = 0x0000,
  40         MV_PCS_BASE_R           = 0x1000,
  41         MV_PCS_1000BASEX        = 0x2000,
  42
  43         MV_PCS_CSCR1            = 0x8000,
  44         MV_PCS_CSCR1_ED_MASK    = 0x0300,
  45         MV_PCS_CSCR1_ED_OFF     = 0x0000,
  46         MV_PCS_CSCR1_ED_RX      = 0x0200,
  47         MV_PCS_CSCR1_ED_NLP     = 0x0300,
  48         MV_PCS_CSCR1_MDIX_MASK  = 0x0060,
  49         MV_PCS_CSCR1_MDIX_MDI   = 0x0000,
  50         MV_PCS_CSCR1_MDIX_MDIX  = 0x0020,
  51         MV_PCS_CSCR1_MDIX_AUTO  = 0x0060,
  52
  53         MV_PCS_CSSR1            = 0x8008,
  54         MV_PCS_CSSR1_SPD1_MASK  = 0xc000,
  55         MV_PCS_CSSR1_SPD1_SPD2  = 0xc000,
  56         MV_PCS_CSSR1_SPD1_1000  = 0x8000,
  57         MV_PCS_CSSR1_SPD1_100   = 0x4000,
  58         MV_PCS_CSSR1_SPD1_10    = 0x0000,
  59         MV_PCS_CSSR1_DUPLEX_FULL= BIT(13),
  60         MV_PCS_CSSR1_RESOLVED   = BIT(11),
  61         MV_PCS_CSSR1_MDIX       = BIT(6),
  62         MV_PCS_CSSR1_SPD2_MASK  = 0x000c,
  63         MV_PCS_CSSR1_SPD2_5000  = 0x0008,
  64         MV_PCS_CSSR1_SPD2_2500  = 0x0004,
  65         MV_PCS_CSSR1_SPD2_10000 = 0x0000,
  66
  67         /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
  68          * registers appear to set themselves to the 0x800X when AN is
  69          * restarted, but status registers appear readable from either.
  70          */
  71         MV_AN_CTRL1000          = 0x8000, /* 1000base-T control register */
  72         MV_AN_STAT1000          = 0x8001, /* 1000base-T status register */
  73
  74         /* Vendor2 MMD registers */
  75         MV_V2_PORT_CTRL         = 0xf001,
  76         MV_V2_PORT_CTRL_PWRDOWN = 0x0800,
  77         MV_V2_TEMP_CTRL         = 0xf08a,
  78         MV_V2_TEMP_CTRL_MASK    = 0xc000,
  79         MV_V2_TEMP_CTRL_SAMPLE  = 0x0000,
  80         MV_V2_TEMP_CTRL_DISABLE = 0xc000,
  81         MV_V2_TEMP              = 0xf08c,
  82         MV_V2_TEMP_UNKNOWN      = 0x9600, /* unknown function */
  83 };
  84
  85 struct mv3310_priv {
  86         struct device *hwmon_dev;
  87         char *hwmon_name;
  88 };
  89
  90 #ifdef CONFIG_HWMON
  91 static umode_t mv3310_hwmon_is_visible(const void *data,
  92                                        enum hwmon_sensor_types type,
  93                                        u32 attr, int channel)
  94 {
  95         if (type == hwmon_chip && attr == hwmon_chip_update_interval)
  96                 return 0444;
  97         if (type == hwmon_temp && attr == hwmon_temp_input)
  98                 return 0444;
  99         return 0;
 100 }
 101
 102 static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
 103                              u32 attr, int channel, long *value)
 104 {
 105         struct phy_device *phydev = dev_get_drvdata(dev);
 106         int temp;
 107
 108         if (type == hwmon_chip && attr == hwmon_chip_update_interval) {
 109                 *value = MSEC_PER_SEC;
 110                 return 0;
 111         }
 112
 113         if (type == hwmon_temp && attr == hwmon_temp_input) {
 114                 temp = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP);
 115                 if (temp < 0)
 116                         return temp;
 117
 118                 *value = ((temp & 0xff) - 75) * 1000;
 119
 120                 return 0;
 121         }
 122
 123         return -EOPNOTSUPP;
 124 }
 125
 126 static const struct hwmon_ops mv3310_hwmon_ops = {
 127         .is_visible = mv3310_hwmon_is_visible,
 128         .read = mv3310_hwmon_read,
 129 };
 130
 131 static u32 mv3310_hwmon_chip_config[] = {
 132         HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL,
 133         0,
 134 };
 135
 136 static const struct hwmon_channel_info mv3310_hwmon_chip = {
 137         .type = hwmon_chip,
 138         .config = mv3310_hwmon_chip_config,
 139 };
 140
 141 static u32 mv3310_hwmon_temp_config[] = {
 142         HWMON_T_INPUT,
 143         0,
 144 };
 145
 146 static const struct hwmon_channel_info mv3310_hwmon_temp = {
 147         .type = hwmon_temp,
 148         .config = mv3310_hwmon_temp_config,
 149 };
 150
 151 static const struct hwmon_channel_info *mv3310_hwmon_info[] = {
 152         &mv3310_hwmon_chip,
 153         &mv3310_hwmon_temp,
 154         NULL,
 155 };
 156
 157 static const struct hwmon_chip_info mv3310_hwmon_chip_info = {
 158         .ops = &mv3310_hwmon_ops,
 159         .info = mv3310_hwmon_info,
 160 };
 161
 162 static int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
 163 {
 164         u16 val;
 165         int ret;
 166
 167         ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP,
 168                             MV_V2_TEMP_UNKNOWN);
 169         if (ret < 0)
 170                 return ret;
 171
 172         val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE;
 173
 174         return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL,
 175                               MV_V2_TEMP_CTRL_MASK, val);
 176 }
 177
 178 static void mv3310_hwmon_disable(void *data)
 179 {
 180         struct phy_device *phydev = data;
 181
 182         mv3310_hwmon_config(phydev, false);
 183 }
 184
 185 static int mv3310_hwmon_probe(struct phy_device *phydev)
 186 {
 187         struct device *dev = &phydev->mdio.dev;
 188         struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
 189         int i, j, ret;
 190
 191         priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
 192         if (!priv->hwmon_name)
 193                 return -ENODEV;
 194
 195         for (i = j = 0; priv->hwmon_name[i]; i++) {
 196                 if (isalnum(priv->hwmon_name[i])) {
 197                         if (i != j)
 198                                 priv->hwmon_name[j] = priv->hwmon_name[i];
 199                         j++;
 200                 }
 201         }
 202         priv->hwmon_name[j] = '\0';
 203
 204         ret = mv3310_hwmon_config(phydev, true);
 205         if (ret)
 206                 return ret;
 207
 208         ret = devm_add_action_or_reset(dev, mv3310_hwmon_disable, phydev);
 209         if (ret)
 210                 return ret;
 211
 212         priv->hwmon_dev = devm_hwmon_device_register_with_info(dev,
 213                                 priv->hwmon_name, phydev,
 214                                 &mv3310_hwmon_chip_info, NULL);
 215
 216         return PTR_ERR_OR_ZERO(priv->hwmon_dev);
 217 }
 218 #else
 219 static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
 220 {
 221         return 0;
 222 }
 223
 224 static int mv3310_hwmon_probe(struct phy_device *phydev)
 225 {
 226         return 0;
 227 }
 228 #endif
 229
 230 static int mv3310_power_down(struct phy_device *phydev)
 231 {
 232         return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
 233                                 MV_V2_PORT_CTRL_PWRDOWN);
 234 }
 235
 236 static int mv3310_power_up(struct phy_device *phydev)
 237 {
 238         return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
 239                                   MV_V2_PORT_CTRL_PWRDOWN);
 240 }
 241
 242 static int mv3310_reset(struct phy_device *phydev, u32 unit)
 243 {
 244         int val, err;
 245
 246         err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1,
 247                              MDIO_CTRL1_RESET, MDIO_CTRL1_RESET);
 248         if (err < 0)
 249                 return err;
 250
 251         return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS,
 252                                          unit + MDIO_CTRL1, val,
 253                                          !(val & MDIO_CTRL1_RESET),
 254                                          5000, 100000, true);
 255 }
 256
 257 static int mv3310_get_edpd(struct phy_device *phydev, u16 *edpd)
 258 {
 259         int val;
 260
 261         val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1);
 262         if (val < 0)
 263                 return val;
 264
 265         switch (val & MV_PCS_CSCR1_ED_MASK) {
 266         case MV_PCS_CSCR1_ED_NLP:
 267                 *edpd = 1000;
 268                 break;
 269         case MV_PCS_CSCR1_ED_RX:
 270                 *edpd = ETHTOOL_PHY_EDPD_NO_TX;
 271                 break;
 272         default:
 273                 *edpd = ETHTOOL_PHY_EDPD_DISABLE;
 274                 break;
 275         }
 276         return 0;
 277 }
 278
 279 static int mv3310_set_edpd(struct phy_device *phydev, u16 edpd)
 280 {
 281         u16 val;
 282         int err;
 283
 284         switch (edpd) {
 285         case 1000:
 286         case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS:
 287                 val = MV_PCS_CSCR1_ED_NLP;
 288                 break;
 289
 290         case ETHTOOL_PHY_EDPD_NO_TX:
 291                 val = MV_PCS_CSCR1_ED_RX;
 292                 break;
 293
 294         case ETHTOOL_PHY_EDPD_DISABLE:
 295                 val = MV_PCS_CSCR1_ED_OFF;
 296                 break;
 297
 298         default:
 299                 return -EINVAL;
 300         }
 301
 302         err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
 303                                      MV_PCS_CSCR1_ED_MASK, val);
 304         if (err > 0)
 305                 err = mv3310_reset(phydev, MV_PCS_BASE_T);
 306
 307         return err;
 308 }
 309
 310 static int mv3310_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
 311 {
 312         struct phy_device *phydev = upstream;
 313         __ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, };
 314         phy_interface_t iface;
 315
 316         sfp_parse_support(phydev->sfp_bus, id, support);
 317         iface = sfp_select_interface(phydev->sfp_bus, support);
 318
 319         if (iface != PHY_INTERFACE_MODE_10GBASER) {
 320                 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
 321                 return -EINVAL;
 322         }
 323         return 0;
 324 }
 325
 326 static const struct sfp_upstream_ops mv3310_sfp_ops = {
 327         .attach = phy_sfp_attach,
 328         .detach = phy_sfp_detach,
 329         .module_insert = mv3310_sfp_insert,
 330 };
 331
 332 static int mv3310_probe(struct phy_device *phydev)
 333 {
 334         struct mv3310_priv *priv;
 335         u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
 336         int ret;
 337
 338         if (!phydev->is_c45 ||
 339             (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
 340                 return -ENODEV;
 341
 342         ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT);
 343         if (ret < 0)
 344                 return ret;
 345
 346         if (ret & MV_PMA_BOOT_FATAL) {
 347                 dev_warn(&phydev->mdio.dev,
 348                          "PHY failed to boot firmware, status=%04x\n", ret);
 349                 return -ENODEV;
 350         }
 351
 352         priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
 353         if (!priv)
 354                 return -ENOMEM;
 355
 356         dev_set_drvdata(&phydev->mdio.dev, priv);
 357
 358         /* Powering down the port when not in use saves about 600mW */
 359         ret = mv3310_power_down(phydev);
 360         if (ret)
 361                 return ret;
 362
 363         ret = mv3310_hwmon_probe(phydev);
 364         if (ret)
 365                 return ret;
 366
 367         return phy_sfp_probe(phydev, &mv3310_sfp_ops);
 368 }
 369
 370 static int mv3310_suspend(struct phy_device *phydev)
 371 {
 372         return mv3310_power_down(phydev);
 373 }
 374
 375 static int mv3310_resume(struct phy_device *phydev)
 376 {
 377         int ret;
 378
 379         ret = mv3310_power_up(phydev);
 380         if (ret)
 381                 return ret;
 382
 383         return mv3310_hwmon_config(phydev, true);
 384 }
 385
 386 /* Some PHYs in the Alaska family such as the 88X3310 and the 88E2010
 387  * don't set bit 14 in PMA Extended Abilities (1.11), although they do
 388  * support 2.5GBASET and 5GBASET. For these models, we can still read their
 389  * 2.5G/5G extended abilities register (1.21). We detect these models based on
 390  * the PMA device identifier, with a mask matching models known to have this
 391  * issue
 392  */
 393 static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev)
 394 {
 395         if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD))
 396                 return false;
 397
 398         /* Only some revisions of the 88X3310 family PMA seem to be impacted */
 399         return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
 400                 MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV;
 401 }
 402
 403 static int mv3310_config_init(struct phy_device *phydev)
 404 {
 405         int err;
 406
 407         /* Check that the PHY interface type is compatible */
 408         if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
 409             phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
 410             phydev->interface != PHY_INTERFACE_MODE_XAUI &&
 411             phydev->interface != PHY_INTERFACE_MODE_RXAUI &&
 412             phydev->interface != PHY_INTERFACE_MODE_10GBASER)
 413                 return -ENODEV;
 414
 415         phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
 416
 417         /* Power up so reset works */
 418         err = mv3310_power_up(phydev);
 419         if (err)
 420                 return err;
 421
 422         /* Enable EDPD mode - saving 600mW */
 423         return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
 424 }
 425
 426 static int mv3310_get_features(struct phy_device *phydev)
 427 {
 428         int ret, val;
 429
 430         ret = genphy_c45_pma_read_abilities(phydev);
 431         if (ret)
 432                 return ret;
 433
 434         if (mv3310_has_pma_ngbaset_quirk(phydev)) {
 435                 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
 436                                    MDIO_PMA_NG_EXTABLE);
 437                 if (val < 0)
 438                         return val;
 439
 440                 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
 441                                  phydev->supported,
 442                                  val & MDIO_PMA_NG_EXTABLE_2_5GBT);
 443
 444                 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
 445                                  phydev->supported,
 446                                  val & MDIO_PMA_NG_EXTABLE_5GBT);
 447         }
 448
 449         return 0;
 450 }
 451
 452 static int mv3310_config_mdix(struct phy_device *phydev)
 453 {
 454         u16 val;
 455         int err;
 456
 457         switch (phydev->mdix_ctrl) {
 458         case ETH_TP_MDI_AUTO:
 459                 val = MV_PCS_CSCR1_MDIX_AUTO;
 460                 break;
 461         case ETH_TP_MDI_X:
 462                 val = MV_PCS_CSCR1_MDIX_MDIX;
 463                 break;
 464         case ETH_TP_MDI:
 465                 val = MV_PCS_CSCR1_MDIX_MDI;
 466                 break;
 467         default:
 468                 return -EINVAL;
 469         }
 470
 471         err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
 472                                      MV_PCS_CSCR1_MDIX_MASK, val);
 473         if (err > 0)
 474                 err = mv3310_reset(phydev, MV_PCS_BASE_T);
 475
 476         return err;
 477 }
 478
 479 static int mv3310_config_aneg(struct phy_device *phydev)
 480 {
 481         bool changed = false;
 482         u16 reg;
 483         int ret;
 484
 485         ret = mv3310_config_mdix(phydev);
 486         if (ret < 0)
 487                 return ret;
 488
 489         if (phydev->autoneg == AUTONEG_DISABLE)
 490                 return genphy_c45_pma_setup_forced(phydev);
 491
 492         ret = genphy_c45_an_config_aneg(phydev);
 493         if (ret < 0)
 494                 return ret;
 495         if (ret > 0)
 496                 changed = true;
 497
 498         /* Clause 45 has no standardized support for 1000BaseT, therefore
 499          * use vendor registers for this mode.
 500          */
 501         reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
 502         ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
 503                              ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg);
 504         if (ret < 0)
 505                 return ret;
 506         if (ret > 0)
 507                 changed = true;
 508
 509         return genphy_c45_check_and_restart_aneg(phydev, changed);
 510 }
 511
 512 static int mv3310_aneg_done(struct phy_device *phydev)
 513 {
 514         int val;
 515
 516         val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
 517         if (val < 0)
 518                 return val;
 519
 520         if (val & MDIO_STAT1_LSTATUS)
 521                 return 1;
 522
 523         return genphy_c45_aneg_done(phydev);
 524 }
 525
 526 static void mv3310_update_interface(struct phy_device *phydev)
 527 {
 528         if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
 529              phydev->interface == PHY_INTERFACE_MODE_2500BASEX ||
 530              phydev->interface == PHY_INTERFACE_MODE_10GBASER) &&
 531             phydev->link) {
 532                 /* The PHY automatically switches its serdes interface (and
 533                  * active PHYXS instance) between Cisco SGMII, 10GBase-R and
 534                  * 2500BaseX modes according to the speed.  Florian suggests
 535                  * setting phydev->interface to communicate this to the MAC.
 536                  * Only do this if we are already in one of the above modes.
 537                  */
 538                 switch (phydev->speed) {
 539                 case SPEED_10000:
 540                         phydev->interface = PHY_INTERFACE_MODE_10GBASER;
 541                         break;
 542                 case SPEED_2500:
 543                         phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
 544                         break;
 545                 case SPEED_1000:
 546                 case SPEED_100:
 547                 case SPEED_10:
 548                         phydev->interface = PHY_INTERFACE_MODE_SGMII;
 549                         break;
 550                 default:
 551                         break;
 552                 }
 553         }
 554 }
 555
 556 /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */
 557 static int mv3310_read_status_10gbaser(struct phy_device *phydev)
 558 {
 559         phydev->link = 1;
 560         phydev->speed = SPEED_10000;
 561         phydev->duplex = DUPLEX_FULL;
 562
 563         return 0;
 564 }
 565
 566 static int mv3310_read_status_copper(struct phy_device *phydev)
 567 {
 568         int cssr1, speed, val;
 569
 570         val = genphy_c45_read_link(phydev);
 571         if (val < 0)
 572                 return val;
 573
 574         val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
 575         if (val < 0)
 576                 return val;
 577
 578         cssr1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSSR1);
 579         if (cssr1 < 0)
 580                 return val;
 581
 582         /* If the link settings are not resolved, mark the link down */
 583         if (!(cssr1 & MV_PCS_CSSR1_RESOLVED)) {
 584                 phydev->link = 0;
 585                 return 0;
 586         }
 587
 588         /* Read the copper link settings */
 589         speed = cssr1 & MV_PCS_CSSR1_SPD1_MASK;
 590         if (speed == MV_PCS_CSSR1_SPD1_SPD2)
 591                 speed |= cssr1 & MV_PCS_CSSR1_SPD2_MASK;
 592
 593         switch (speed) {
 594         case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_10000:
 595                 phydev->speed = SPEED_10000;
 596                 break;
 597
 598         case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_5000:
 599                 phydev->speed = SPEED_5000;
 600                 break;
 601
 602         case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_2500:
 603                 phydev->speed = SPEED_2500;
 604                 break;
 605
 606         case MV_PCS_CSSR1_SPD1_1000:
 607                 phydev->speed = SPEED_1000;
 608                 break;
 609
 610         case MV_PCS_CSSR1_SPD1_100:
 611                 phydev->speed = SPEED_100;
 612                 break;
 613
 614         case MV_PCS_CSSR1_SPD1_10:
 615                 phydev->speed = SPEED_10;
 616                 break;
 617         }
 618
 619         phydev->duplex = cssr1 & MV_PCS_CSSR1_DUPLEX_FULL ?
 620                          DUPLEX_FULL : DUPLEX_HALF;
 621         phydev->mdix = cssr1 & MV_PCS_CSSR1_MDIX ?
 622                        ETH_TP_MDI_X : ETH_TP_MDI;
 623
 624         if (val & MDIO_AN_STAT1_COMPLETE) {
 625                 val = genphy_c45_read_lpa(phydev);
 626                 if (val < 0)
 627                         return val;
 628
 629                 /* Read the link partner's 1G advertisement */
 630                 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000);
 631                 if (val < 0)
 632                         return val;
 633
 634                 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
 635
 636                 /* Update the pause status */
 637                 phy_resolve_aneg_pause(phydev);
 638         }
 639
 640         return 0;
 641 }
 642
 643 static int mv3310_read_status(struct phy_device *phydev)
 644 {
 645         int err, val;
 646
 647         phydev->speed = SPEED_UNKNOWN;
 648         phydev->duplex = DUPLEX_UNKNOWN;
 649         linkmode_zero(phydev->lp_advertising);
 650         phydev->link = 0;
 651         phydev->pause = 0;
 652         phydev->asym_pause = 0;
 653         phydev->mdix = ETH_TP_MDI_INVALID;
 654
 655         val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
 656         if (val < 0)
 657                 return val;
 658
 659         if (val & MDIO_STAT1_LSTATUS)
 660                 err = mv3310_read_status_10gbaser(phydev);
 661         else
 662                 err = mv3310_read_status_copper(phydev);
 663         if (err < 0)
 664                 return err;
 665
 666         if (phydev->link)
 667                 mv3310_update_interface(phydev);
 668
 669         return 0;
 670 }
 671
 672 static int mv3310_get_tunable(struct phy_device *phydev,
 673                               struct ethtool_tunable *tuna, void *data)
 674 {
 675         switch (tuna->id) {
 676         case ETHTOOL_PHY_EDPD:
 677                 return mv3310_get_edpd(phydev, data);
 678         default:
 679                 return -EOPNOTSUPP;
 680         }
 681 }
 682
 683 static int mv3310_set_tunable(struct phy_device *phydev,
 684                               struct ethtool_tunable *tuna, const void *data)
 685 {
 686         switch (tuna->id) {
 687         case ETHTOOL_PHY_EDPD:
 688                 return mv3310_set_edpd(phydev, *(u16 *)data);
 689         default:
 690                 return -EOPNOTSUPP;
 691         }
 692 }
 693
 694 static struct phy_driver mv3310_drivers[] = {
 695         {
 696                 .phy_id         = MARVELL_PHY_ID_88X3310,
 697                 .phy_id_mask    = MARVELL_PHY_ID_MASK,
 698                 .name           = "mv88x3310",
 699                 .get_features   = mv3310_get_features,
 700                 .soft_reset     = genphy_no_soft_reset,
 701                 .config_init    = mv3310_config_init,
 702                 .probe          = mv3310_probe,
 703                 .suspend        = mv3310_suspend,
 704                 .resume         = mv3310_resume,
 705                 .config_aneg    = mv3310_config_aneg,
 706                 .aneg_done      = mv3310_aneg_done,
 707                 .read_status    = mv3310_read_status,
 708                 .get_tunable    = mv3310_get_tunable,
 709                 .set_tunable    = mv3310_set_tunable,
 710         },
 711         {
 712                 .phy_id         = MARVELL_PHY_ID_88E2110,
 713                 .phy_id_mask    = MARVELL_PHY_ID_MASK,
 714                 .name           = "mv88x2110",
 715                 .probe          = mv3310_probe,
 716                 .suspend        = mv3310_suspend,
 717                 .resume         = mv3310_resume,
 718                 .soft_reset     = genphy_no_soft_reset,
 719                 .config_init    = mv3310_config_init,
 720                 .config_aneg    = mv3310_config_aneg,
 721                 .aneg_done      = mv3310_aneg_done,
 722                 .read_status    = mv3310_read_status,
 723                 .get_tunable    = mv3310_get_tunable,
 724                 .set_tunable    = mv3310_set_tunable,
 725         },
 726 };
 727
 728 module_phy_driver(mv3310_drivers);
 729
 730 static struct mdio_device_id __maybe_unused mv3310_tbl[] = {
 731         { MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_MASK },
 732         { MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK },
 733         { },
 734 };
 735 MODULE_DEVICE_TABLE(mdio, mv3310_tbl);
 736 MODULE_DESCRIPTION("Marvell Alaska X 10Gigabit Ethernet PHY driver (MV88X3310)");
 737 MODULE_LICENSE("GPL");