drivers/net/phy/micrel.c

   1 /*
   2  * Micrel PHY drivers
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  *
   6  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   7  * author Andy Fleming
   8  * (C) 2012 NetModule AG, David Andrey, added KSZ9031
   9  */
  10 #include <config.h>
  11 #include <common.h>
  12 #include <dm.h>
  13 #include <errno.h>
  14 #include <fdtdec.h>
  15 #include <micrel.h>
  16 #include <phy.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 static struct phy_driver KSZ804_driver = {
  21         .name = "Micrel KSZ804",
  22         .uid = 0x221510,
  23         .mask = 0xfffff0,
  24         .features = PHY_BASIC_FEATURES,
  25         .config = &genphy_config,
  26         .startup = &genphy_startup,
  27         .shutdown = &genphy_shutdown,
  28 };
  29
  30 static struct phy_driver KSZ8031_driver = {
  31         .name = "Micrel KSZ8021/KSZ8031",
  32         .uid = 0x221550,
  33         .mask = 0xfffff0,
  34         .features = PHY_BASIC_FEATURES,
  35         .config = &genphy_config,
  36         .startup = &genphy_startup,
  37         .shutdown = &genphy_shutdown,
  38 };
  39
  40 /**
  41  * KSZ8051
  42  */
  43 #define MII_KSZ8051_PHY_OMSO                    0x16
  44 #define MII_KSZ8051_PHY_OMSO_NAND_TREE_ON       (1 << 5)
  45
  46 static int ksz8051_config(struct phy_device *phydev)
  47 {
  48         unsigned val;
  49
  50         /* Disable NAND-tree */
  51         val = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO);
  52         val &= ~MII_KSZ8051_PHY_OMSO_NAND_TREE_ON;
  53         phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO, val);
  54
  55         return genphy_config(phydev);
  56 }
  57
  58 static struct phy_driver KSZ8051_driver = {
  59         .name = "Micrel KSZ8051",
  60         .uid = 0x221550,
  61         .mask = 0xfffff0,
  62         .features = PHY_BASIC_FEATURES,
  63         .config = &ksz8051_config,
  64         .startup = &genphy_startup,
  65         .shutdown = &genphy_shutdown,
  66 };
  67
  68 static struct phy_driver KSZ8081_driver = {
  69         .name = "Micrel KSZ8081",
  70         .uid = 0x221560,
  71         .mask = 0xfffff0,
  72         .features = PHY_BASIC_FEATURES,
  73         .config = &genphy_config,
  74         .startup = &genphy_startup,
  75         .shutdown = &genphy_shutdown,
  76 };
  77
  78 /**
  79  * KSZ8895
  80  */
  81
  82 static unsigned short smireg_to_phy(unsigned short reg)
  83 {
  84         return ((reg & 0xc0) >> 3) + 0x06 + ((reg & 0x20) >> 5);
  85 }
  86
  87 static unsigned short smireg_to_reg(unsigned short reg)
  88 {
  89         return reg & 0x1F;
  90 }
  91
  92 static void ksz8895_write_smireg(struct phy_device *phydev, int smireg, int val)
  93 {
  94         phydev->bus->write(phydev->bus, smireg_to_phy(smireg), MDIO_DEVAD_NONE,
  95                                                 smireg_to_reg(smireg), val);
  96 }
  97
  98 #if 0
  99 static int ksz8895_read_smireg(struct phy_device *phydev, int smireg)
 100 {
 101         return phydev->bus->read(phydev->bus, smireg_to_phy(smireg),
 102                                         MDIO_DEVAD_NONE, smireg_to_reg(smireg));
 103 }
 104 #endif
 105
 106 int ksz8895_config(struct phy_device *phydev)
 107 {
 108         /* we are connected directly to the switch without
 109          * dedicated PHY. SCONF1 == 001 */
 110         phydev->link = 1;
 111         phydev->duplex = DUPLEX_FULL;
 112         phydev->speed = SPEED_100;
 113
 114         /* Force the switch to start */
 115         ksz8895_write_smireg(phydev, 1, 1);
 116
 117         return 0;
 118 }
 119
 120 static int ksz8895_startup(struct phy_device *phydev)
 121 {
 122         return 0;
 123 }
 124
 125 static struct phy_driver ksz8895_driver = {
 126         .name = "Micrel KSZ8895/KSZ8864",
 127         .uid  = 0x221450,
 128         .mask = 0xffffe1,
 129         .features = PHY_BASIC_FEATURES,
 130         .config   = &ksz8895_config,
 131         .startup  = &ksz8895_startup,
 132         .shutdown = &genphy_shutdown,
 133 };
 134
 135 #ifndef CONFIG_PHY_MICREL_KSZ9021
 136 /*
 137  * I can't believe Micrel used the exact same part number
 138  * for the KSZ9021. Shame Micrel, Shame!
 139  */
 140 static struct phy_driver KS8721_driver = {
 141         .name = "Micrel KS8721BL",
 142         .uid = 0x221610,
 143         .mask = 0xfffff0,
 144         .features = PHY_BASIC_FEATURES,
 145         .config = &genphy_config,
 146         .startup = &genphy_startup,
 147         .shutdown = &genphy_shutdown,
 148 };
 149 #endif
 150
 151
 152 /*
 153  * KSZ9021 - KSZ9031 common
 154  */
 155
 156 #define MII_KSZ90xx_PHY_CTL             0x1f
 157 #define MIIM_KSZ90xx_PHYCTL_1000        (1 << 6)
 158 #define MIIM_KSZ90xx_PHYCTL_100         (1 << 5)
 159 #define MIIM_KSZ90xx_PHYCTL_10          (1 << 4)
 160 #define MIIM_KSZ90xx_PHYCTL_DUPLEX      (1 << 3)
 161
 162 static int ksz90xx_startup(struct phy_device *phydev)
 163 {
 164         unsigned phy_ctl;
 165         genphy_update_link(phydev);
 166         phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL);
 167
 168         if (phy_ctl & MIIM_KSZ90xx_PHYCTL_DUPLEX)
 169                 phydev->duplex = DUPLEX_FULL;
 170         else
 171                 phydev->duplex = DUPLEX_HALF;
 172
 173         if (phy_ctl & MIIM_KSZ90xx_PHYCTL_1000)
 174                 phydev->speed = SPEED_1000;
 175         else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_100)
 176                 phydev->speed = SPEED_100;
 177         else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_10)
 178                 phydev->speed = SPEED_10;
 179         return 0;
 180 }
 181
 182 /* Common OF config bits for KSZ9021 and KSZ9031 */
 183 #if defined(CONFIG_PHY_MICREL_KSZ9021) || defined(CONFIG_PHY_MICREL_KSZ9031)
 184 #ifdef CONFIG_DM_ETH
 185 struct ksz90x1_reg_field {
 186         const char      *name;
 187         const u8        size;   /* Size of the bitfield, in bits */
 188         const u8        off;    /* Offset from bit 0 */
 189         const u8        dflt;   /* Default value */
 190 };
 191
 192 struct ksz90x1_ofcfg {
 193         const u16                       reg;
 194         const u16                       devad;
 195         const struct ksz90x1_reg_field  *grp;
 196         const u16                       grpsz;
 197 };
 198
 199 static const struct ksz90x1_reg_field ksz90x1_rxd_grp[] = {
 200         { "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 },
 201         { "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 }
 202 };
 203
 204 static const struct ksz90x1_reg_field ksz90x1_txd_grp[] = {
 205         { "txd0-skew-ps", 4, 0, 0x7 }, { "txd1-skew-ps", 4, 4, 0x7 },
 206         { "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 },
 207 };
 208
 209 static int ksz90x1_of_config_group(struct phy_device *phydev,
 210                                    struct ksz90x1_ofcfg *ofcfg)
 211 {
 212         struct udevice *dev = phydev->dev;
 213         struct phy_driver *drv = phydev->drv;
 214         const int ps_to_regval = 200;
 215         int val[4];
 216         int i, changed = 0, offset, max;
 217         u16 regval = 0;
 218
 219         if (!drv || !drv->writeext)
 220                 return -EOPNOTSUPP;
 221
 222         for (i = 0; i < ofcfg->grpsz; i++) {
 223                 val[i] = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
 224                                          ofcfg->grp[i].name, -1);
 225                 offset = ofcfg->grp[i].off;
 226                 if (val[i] == -1) {
 227                         /* Default register value for KSZ9021 */
 228                         regval |= ofcfg->grp[i].dflt << offset;
 229                 } else {
 230                         changed = 1;    /* Value was changed in OF */
 231                         /* Calculate the register value and fix corner cases */
 232                         if (val[i] > ps_to_regval * 0xf) {
 233                                 max = (1 << ofcfg->grp[i].size) - 1;
 234                                 regval |= max << offset;
 235                         } else {
 236                                 regval |= (val[i] / ps_to_regval) << offset;
 237                         }
 238                 }
 239         }
 240
 241         if (!changed)
 242                 return 0;
 243
 244         return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval);
 245 }
 246 #endif
 247 #endif
 248
 249 #ifdef CONFIG_PHY_MICREL_KSZ9021
 250 /*
 251  * KSZ9021
 252  */
 253
 254 /* PHY Registers */
 255 #define MII_KSZ9021_EXTENDED_CTRL       0x0b
 256 #define MII_KSZ9021_EXTENDED_DATAW      0x0c
 257 #define MII_KSZ9021_EXTENDED_DATAR      0x0d
 258
 259 #define CTRL1000_PREFER_MASTER          (1 << 10)
 260 #define CTRL1000_CONFIG_MASTER          (1 << 11)
 261 #define CTRL1000_MANUAL_CONFIG          (1 << 12)
 262
 263 #ifdef CONFIG_DM_ETH
 264 static const struct ksz90x1_reg_field ksz9021_clk_grp[] = {
 265         { "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 },
 266         { "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 },
 267 };
 268
 269 static int ksz9021_of_config(struct phy_device *phydev)
 270 {
 271         struct ksz90x1_ofcfg ofcfg[] = {
 272                 { MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0, ksz90x1_rxd_grp, 4 },
 273                 { MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0, ksz90x1_txd_grp, 4 },
 274                 { MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0, ksz9021_clk_grp, 4 },
 275         };
 276         int i, ret = 0;
 277
 278         for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
 279                 ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
 280                 if (ret)
 281                         return ret;
 282
 283         return 0;
 284 }
 285 #else
 286 static int ksz9021_of_config(struct phy_device *phydev)
 287 {
 288         return 0;
 289 }
 290 #endif
 291
 292 int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val)
 293 {
 294         /* extended registers */
 295         phy_write(phydev, MDIO_DEVAD_NONE,
 296                 MII_KSZ9021_EXTENDED_CTRL, regnum | 0x8000);
 297         return phy_write(phydev, MDIO_DEVAD_NONE,
 298                 MII_KSZ9021_EXTENDED_DATAW, val);
 299 }
 300
 301 int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum)
 302 {
 303         /* extended registers */
 304         phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum);
 305         return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR);
 306 }
 307
 308
 309 static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr,
 310                               int regnum)
 311 {
 312         return ksz9021_phy_extended_read(phydev, regnum);
 313 }
 314
 315 static int ksz9021_phy_extwrite(struct phy_device *phydev, int addr,
 316                                int devaddr, int regnum, u16 val)
 317 {
 318         return ksz9021_phy_extended_write(phydev, regnum, val);
 319 }
 320
 321 /* Micrel ksz9021 */
 322 static int ksz9021_config(struct phy_device *phydev)
 323 {
 324         unsigned ctrl1000 = 0;
 325         const unsigned master = CTRL1000_PREFER_MASTER |
 326                         CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG;
 327         unsigned features = phydev->drv->features;
 328         int ret;
 329
 330         ret = ksz9021_of_config(phydev);
 331         if (ret)
 332                 return ret;
 333
 334         if (getenv("disable_giga"))
 335                 features &= ~(SUPPORTED_1000baseT_Half |
 336                                 SUPPORTED_1000baseT_Full);
 337         /* force master mode for 1000BaseT due to chip errata */
 338         if (features & SUPPORTED_1000baseT_Half)
 339                 ctrl1000 |= ADVERTISE_1000HALF | master;
 340         if (features & SUPPORTED_1000baseT_Full)
 341                 ctrl1000 |= ADVERTISE_1000FULL | master;
 342         phydev->advertising = phydev->supported = features;
 343         phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000);
 344         genphy_config_aneg(phydev);
 345         genphy_restart_aneg(phydev);
 346         return 0;
 347 }
 348
 349 static struct phy_driver ksz9021_driver = {
 350         .name = "Micrel ksz9021",
 351         .uid  = 0x221610,
 352         .mask = 0xfffff0,
 353         .features = PHY_GBIT_FEATURES,
 354         .config = &ksz9021_config,
 355         .startup = &ksz90xx_startup,
 356         .shutdown = &genphy_shutdown,
 357         .writeext = &ksz9021_phy_extwrite,
 358         .readext = &ksz9021_phy_extread,
 359 };
 360 #endif
 361
 362 /**
 363  * KSZ9031
 364  */
 365 /* PHY Registers */
 366 #define MII_KSZ9031_MMD_ACCES_CTRL      0x0d
 367 #define MII_KSZ9031_MMD_REG_DATA        0x0e
 368
 369 #ifdef CONFIG_DM_ETH
 370 static const struct ksz90x1_reg_field ksz9031_ctl_grp[] =
 371         { { "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 } };
 372 static const struct ksz90x1_reg_field ksz9031_clk_grp[] =
 373         { { "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf } };
 374
 375 static int ksz9031_of_config(struct phy_device *phydev)
 376 {
 377         struct ksz90x1_ofcfg ofcfg[] = {
 378                 { MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 },
 379                 { MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
 380                 { MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
 381                 { MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 },
 382         };
 383         int i, ret = 0;
 384
 385         for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
 386                 ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
 387                 if (ret)
 388                         return ret;
 389
 390         return 0;
 391 }
 392 #else
 393 static int ksz9031_of_config(struct phy_device *phydev)
 394 {
 395         return 0;
 396 }
 397 #endif
 398
 399 /* Accessors to extended registers*/
 400 int ksz9031_phy_extended_write(struct phy_device *phydev,
 401                                int devaddr, int regnum, u16 mode, u16 val)
 402 {
 403         /*select register addr for mmd*/
 404         phy_write(phydev, MDIO_DEVAD_NONE,
 405                   MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
 406         /*select register for mmd*/
 407         phy_write(phydev, MDIO_DEVAD_NONE,
 408                   MII_KSZ9031_MMD_REG_DATA, regnum);
 409         /*setup mode*/
 410         phy_write(phydev, MDIO_DEVAD_NONE,
 411                   MII_KSZ9031_MMD_ACCES_CTRL, (mode | devaddr));
 412         /*write the value*/
 413         return  phy_write(phydev, MDIO_DEVAD_NONE,
 414                 MII_KSZ9031_MMD_REG_DATA, val);
 415 }
 416
 417 int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
 418                               int regnum, u16 mode)
 419 {
 420         phy_write(phydev, MDIO_DEVAD_NONE,
 421                   MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
 422         phy_write(phydev, MDIO_DEVAD_NONE,
 423                   MII_KSZ9031_MMD_REG_DATA, regnum);
 424         phy_write(phydev, MDIO_DEVAD_NONE,
 425                   MII_KSZ9031_MMD_ACCES_CTRL, (devaddr | mode));
 426         return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9031_MMD_REG_DATA);
 427 }
 428
 429 static int ksz9031_phy_extread(struct phy_device *phydev, int addr, int devaddr,
 430                                int regnum)
 431 {
 432         return ksz9031_phy_extended_read(phydev, devaddr, regnum,
 433                                          MII_KSZ9031_MOD_DATA_NO_POST_INC);
 434 };
 435
 436 static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
 437                                 int devaddr, int regnum, u16 val)
 438 {
 439         return ksz9031_phy_extended_write(phydev, devaddr, regnum,
 440                                          MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
 441 };
 442
 443 static int ksz9031_config(struct phy_device *phydev)
 444 {
 445         int ret;
 446         ret = ksz9031_of_config(phydev);
 447         if (ret)
 448                 return ret;
 449         return genphy_config(phydev);
 450 }
 451
 452 static struct phy_driver ksz9031_driver = {
 453         .name = "Micrel ksz9031",
 454         .uid  = 0x221620,
 455         .mask = 0xfffff0,
 456         .features = PHY_GBIT_FEATURES,
 457         .config   = &ksz9031_config,
 458         .startup  = &ksz90xx_startup,
 459         .shutdown = &genphy_shutdown,
 460         .writeext = &ksz9031_phy_extwrite,
 461         .readext = &ksz9031_phy_extread,
 462 };
 463
 464 int phy_micrel_init(void)
 465 {
 466         phy_register(&KSZ804_driver);
 467         phy_register(&KSZ8031_driver);
 468         phy_register(&KSZ8051_driver);
 469         phy_register(&KSZ8081_driver);
 470 #ifdef CONFIG_PHY_MICREL_KSZ9021
 471         phy_register(&ksz9021_driver);
 472 #else
 473         phy_register(&KS8721_driver);
 474 #endif
 475         phy_register(&ksz9031_driver);
 476         phy_register(&ksz8895_driver);
 477         return 0;
 478 }