2 * National Semiconductor PHY drivers
4 * SPDX-License-Identifier: GPL-2.0+
6 * Copyright 2010-2011 Freescale Semiconductor, Inc.
13 #define DP83630_PHY_PAGESEL_REG 0x13
14 #define DP83630_PHY_PTP_COC_REG 0x14
15 #define DP83630_PHY_PTP_CLKOUT_EN (1<<15)
16 #define DP83630_PHY_RBR_REG 0x17
18 static int dp83630_config(struct phy_device
*phydev
)
22 phy_write(phydev
, MDIO_DEVAD_NONE
, MII_BMCR
, BMCR_RESET
);
23 phy_write(phydev
, MDIO_DEVAD_NONE
, DP83630_PHY_PAGESEL_REG
, 0x6);
24 ptp_coc_reg
= phy_read(phydev
, MDIO_DEVAD_NONE
,
25 DP83630_PHY_PTP_COC_REG
);
26 ptp_coc_reg
&= ~DP83630_PHY_PTP_CLKOUT_EN
;
27 phy_write(phydev
, MDIO_DEVAD_NONE
, DP83630_PHY_PTP_COC_REG
,
29 phy_write(phydev
, MDIO_DEVAD_NONE
, DP83630_PHY_PAGESEL_REG
, 0);
31 genphy_config_aneg(phydev
);
36 static struct phy_driver DP83630_driver
= {
37 .name
= "NatSemi DP83630",
40 .features
= PHY_BASIC_FEATURES
,
41 .config
= &dp83630_config
,
42 .startup
= &genphy_startup
,
43 .shutdown
= &genphy_shutdown
,
47 /* DP83865 Link and Auto-Neg Status Register */
48 #define MIIM_DP83865_LANR 0x11
49 #define MIIM_DP83865_SPD_MASK 0x0018
50 #define MIIM_DP83865_SPD_1000 0x0010
51 #define MIIM_DP83865_SPD_100 0x0008
52 #define MIIM_DP83865_DPX_FULL 0x0002
56 static int dp838xx_config(struct phy_device
*phydev
)
58 phy_write(phydev
, MDIO_DEVAD_NONE
, MII_BMCR
, BMCR_RESET
);
59 genphy_config_aneg(phydev
);
64 static int dp83865_parse_status(struct phy_device
*phydev
)
68 mii_reg
= phy_read(phydev
, MDIO_DEVAD_NONE
, MIIM_DP83865_LANR
);
70 switch (mii_reg
& MIIM_DP83865_SPD_MASK
) {
72 case MIIM_DP83865_SPD_1000
:
73 phydev
->speed
= SPEED_1000
;
76 case MIIM_DP83865_SPD_100
:
77 phydev
->speed
= SPEED_100
;
81 phydev
->speed
= SPEED_10
;
86 if (mii_reg
& MIIM_DP83865_DPX_FULL
)
87 phydev
->duplex
= DUPLEX_FULL
;
89 phydev
->duplex
= DUPLEX_HALF
;
94 static int dp83865_startup(struct phy_device
*phydev
)
96 genphy_update_link(phydev
);
97 dp83865_parse_status(phydev
);
103 static struct phy_driver DP83865_driver
= {
104 .name
= "NatSemi DP83865",
107 .features
= PHY_GBIT_FEATURES
,
108 .config
= &dp838xx_config
,
109 .startup
= &dp83865_startup
,
110 .shutdown
= &genphy_shutdown
,
113 /* NatSemi DP83848 */
114 static int dp83848_parse_status(struct phy_device
*phydev
)
118 mii_reg
= phy_read(phydev
, MDIO_DEVAD_NONE
, MII_BMSR
);
120 if(mii_reg
& (BMSR_100FULL
| BMSR_100HALF
)) {
121 phydev
->speed
= SPEED_100
;
123 phydev
->speed
= SPEED_10
;
126 if (mii_reg
& (BMSR_10FULL
| BMSR_100FULL
)) {
127 phydev
->duplex
= DUPLEX_FULL
;
129 phydev
->duplex
= DUPLEX_HALF
;
135 static int dp83848_startup(struct phy_device
*phydev
)
137 genphy_update_link(phydev
);
138 dp83848_parse_status(phydev
);
143 static struct phy_driver DP83848_driver
= {
144 .name
= "NatSemi DP83848",
147 .features
= PHY_BASIC_FEATURES
,
148 .config
= &dp838xx_config
,
149 .startup
= &dp83848_startup
,
150 .shutdown
= &genphy_shutdown
,
153 int phy_natsemi_init(void)
155 phy_register(&DP83630_driver
);
156 phy_register(&DP83865_driver
);
157 phy_register(&DP83848_driver
);