drivers/net/pic32_eth.h

   1 /*
   2  * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  *
   6  */
   7
   8 #ifndef __MICROCHIP_PIC32_ETH_H_
   9 #define __MICROCHIP_PIC32_ETH_H_
  10
  11 #include <mach/pic32.h>
  12
  13 /* Ethernet */
  14 struct pic32_ectl_regs {
  15         struct pic32_reg_atomic con1; /* 0x00 */
  16         struct pic32_reg_atomic con2; /* 0x10 */
  17         struct pic32_reg_atomic txst; /* 0x20 */
  18         struct pic32_reg_atomic rxst; /* 0x30 */
  19         struct pic32_reg_atomic ht0;  /* 0x40 */
  20         struct pic32_reg_atomic ht1;  /* 0x50 */
  21         struct pic32_reg_atomic pmm0; /* 0x60 */
  22         struct pic32_reg_atomic pmm1; /* 0x70 */
  23         struct pic32_reg_atomic pmcs; /* 0x80 */
  24         struct pic32_reg_atomic pmo;  /* 0x90 */
  25         struct pic32_reg_atomic rxfc; /* 0xa0 */
  26         struct pic32_reg_atomic rxwm; /* 0xb0 */
  27         struct pic32_reg_atomic ien;  /* 0xc0 */
  28         struct pic32_reg_atomic irq;  /* 0xd0 */
  29         struct pic32_reg_atomic stat; /* 0xe0 */
  30 };
  31
  32 struct pic32_mii_regs {
  33         struct pic32_reg_atomic mcfg; /* 0x280 */
  34         struct pic32_reg_atomic mcmd; /* 0x290 */
  35         struct pic32_reg_atomic madr; /* 0x2a0 */
  36         struct pic32_reg_atomic mwtd; /* 0x2b0 */
  37         struct pic32_reg_atomic mrdd; /* 0x2c0 */
  38         struct pic32_reg_atomic mind; /* 0x2d0 */
  39 };
  40
  41 struct pic32_emac_regs {
  42         struct pic32_reg_atomic cfg1; /* 0x200*/
  43         struct pic32_reg_atomic cfg2; /* 0x210*/
  44         struct pic32_reg_atomic ipgt; /* 0x220*/
  45         struct pic32_reg_atomic ipgr; /* 0x230*/
  46         struct pic32_reg_atomic clrt; /* 0x240*/
  47         struct pic32_reg_atomic maxf; /* 0x250*/
  48         struct pic32_reg_atomic supp; /* 0x260*/
  49         struct pic32_reg_atomic test; /* 0x270*/
  50         struct pic32_mii_regs mii;    /* 0x280 - 0x2d0 */
  51         struct pic32_reg_atomic res1; /* 0x2e0 */
  52         struct pic32_reg_atomic res2; /* 0x2f0 */
  53         struct pic32_reg_atomic sa0;  /* 0x300 */
  54         struct pic32_reg_atomic sa1;  /* 0x310 */
  55         struct pic32_reg_atomic sa2;  /* 0x320 */
  56 };
  57
  58 /* ETHCON1 Reg field */
  59 #define ETHCON_BUFCDEC          BIT(0)
  60 #define ETHCON_RXEN             BIT(8)
  61 #define ETHCON_TXRTS            BIT(9)
  62 #define ETHCON_ON               BIT(15)
  63
  64 /* ETHCON2 Reg field */
  65 #define ETHCON_RXBUFSZ          0x7f
  66 #define ETHCON_RXBUFSZ_SHFT     0x4
  67
  68 /* ETHSTAT Reg field */
  69 #define ETHSTAT_BUSY            BIT(7)
  70 #define ETHSTAT_BUFCNT          0x00ff0000
  71
  72 /* ETHRXFC Register fields */
  73 #define ETHRXFC_BCEN            BIT(0)
  74 #define ETHRXFC_MCEN            BIT(1)
  75 #define ETHRXFC_UCEN            BIT(3)
  76 #define ETHRXFC_RUNTEN          BIT(4)
  77 #define ETHRXFC_CRCOKEN         BIT(5)
  78
  79 /* EMAC1CFG1 register offset */
  80 #define PIC32_EMAC1CFG1         0x0200
  81
  82 /* EMAC1CFG1 register fields */
  83 #define EMAC_RXENABLE           BIT(0)
  84 #define EMAC_RXPAUSE            BIT(2)
  85 #define EMAC_TXPAUSE            BIT(3)
  86 #define EMAC_SOFTRESET          BIT(15)
  87
  88 /* EMAC1CFG2 register fields */
  89 #define EMAC_FULLDUP            BIT(0)
  90 #define EMAC_LENGTHCK           BIT(1)
  91 #define EMAC_CRCENABLE          BIT(4)
  92 #define EMAC_PADENABLE          BIT(5)
  93 #define EMAC_AUTOPAD            BIT(7)
  94 #define EMAC_EXCESS             BIT(14)
  95
  96 /* EMAC1IPGT register magic */
  97 #define FULLDUP_GAP_TIME        0x15
  98 #define HALFDUP_GAP_TIME        0x12
  99
 100 /* EMAC1SUPP register fields */
 101 #define EMAC_RMII_SPD100        BIT(8)
 102 #define EMAC_RMII_RESET         BIT(11)
 103
 104 /* MII Management Configuration Register */
 105 #define MIIMCFG_RSTMGMT         BIT(15)
 106 #define MIIMCFG_CLKSEL_DIV40    0x0020  /* 100Mhz / 40 */
 107
 108 /* MII Management Command Register */
 109 #define MIIMCMD_READ            BIT(0)
 110 #define MIIMCMD_SCAN            BIT(1)
 111
 112 /* MII Management Address Register */
 113 #define MIIMADD_REGADDR         0x1f
 114 #define MIIMADD_REGADDR_SHIFT   0
 115 #define MIIMADD_PHYADDR_SHIFT   8
 116
 117 /* MII Management Indicator Register */
 118 #define MIIMIND_BUSY            BIT(0)
 119 #define MIIMIND_NOTVALID        BIT(2)
 120 #define MIIMIND_LINKFAIL        BIT(3)
 121
 122 /* Packet Descriptor */
 123 /* Received Packet Status */
 124 #define _RSV1_PKT_CSUM          0xffff
 125 #define _RSV2_CRC_ERR           BIT(20)
 126 #define _RSV2_LEN_ERR           BIT(21)
 127 #define _RSV2_RX_OK             BIT(23)
 128 #define _RSV2_RX_COUNT          0xffff
 129
 130 #define RSV_RX_CSUM(__rsv1)     ((__rsv1) & _RSV1_PKT_CSUM)
 131 #define RSV_RX_COUNT(__rsv2)    ((__rsv2) & _RSV2_RX_COUNT)
 132 #define RSV_RX_OK(__rsv2)       ((__rsv2) & _RSV2_RX_OK)
 133 #define RSV_CRC_ERR(__rsv2)     ((__rsv2) & _RSV2_CRC_ERR)
 134
 135 /* Ethernet Hardware Descriptor Header bits */
 136 #define EDH_EOWN                BIT(7)
 137 #define EDH_NPV                 BIT(8)
 138 #define EDH_STICKY              BIT(9)
 139 #define _EDH_BCOUNT             0x07ff0000
 140 #define EDH_EOP                 BIT(30)
 141 #define EDH_SOP                 BIT(31)
 142 #define EDH_BCOUNT_SHIFT        16
 143 #define EDH_BCOUNT(len)         ((len) << EDH_BCOUNT_SHIFT)
 144
 145 /* Ethernet Hardware Descriptors
 146  * ref: PIC32 Family Reference Manual Table 35-7
 147  * This structure represents the layout of the DMA
 148  * memory shared between the CPU and the Ethernet
 149  * controller.
 150  */
 151 /* TX/RX DMA descriptor */
 152 struct eth_dma_desc {
 153         u32 hdr;        /* header */
 154         u32 data_buff;  /* data buffer address */
 155         u32 stat1;      /* transmit/receive packet status */
 156         u32 stat2;      /* transmit/receive packet status */
 157         u32 next_ed;    /* next descriptor */
 158 };
 159
 160 #define PIC32_MDIO_NAME "PIC32_EMAC"
 161
 162 int pic32_mdio_init(const char *name, ulong ioaddr);
 163
 164 #endif /* __MICROCHIP_PIC32_ETH_H_*/