3 * This file is driver for Renesas Ethernet AVB.
5 * Copyright (C) 2015-2017 Renesas Electronics Corporation
7 * Based on the SuperH Ethernet driver.
9 * SPDX-License-Identifier: GPL-2.0+
18 #include <linux/mii.h>
24 #define RAVB_REG_CCC 0x000
25 #define RAVB_REG_DBAT 0x004
26 #define RAVB_REG_CSR 0x00C
27 #define RAVB_REG_APSR 0x08C
28 #define RAVB_REG_RCR 0x090
29 #define RAVB_REG_TGC 0x300
30 #define RAVB_REG_TCCR 0x304
31 #define RAVB_REG_RIC0 0x360
32 #define RAVB_REG_RIC1 0x368
33 #define RAVB_REG_RIC2 0x370
34 #define RAVB_REG_TIC 0x378
35 #define RAVB_REG_ECMR 0x500
36 #define RAVB_REG_RFLR 0x508
37 #define RAVB_REG_ECSIPR 0x518
38 #define RAVB_REG_PIR 0x520
39 #define RAVB_REG_GECMR 0x5b0
40 #define RAVB_REG_MAHR 0x5c0
41 #define RAVB_REG_MALR 0x5c8
43 #define CCC_OPC_CONFIG BIT(0)
44 #define CCC_OPC_OPERATION BIT(1)
45 #define CCC_BOC BIT(20)
47 #define CSR_OPS 0x0000000F
48 #define CSR_OPS_CONFIG BIT(1)
50 #define TCCR_TSRQ0 BIT(0)
52 #define RFLR_RFL_MIN 0x05EE
54 #define PIR_MDI BIT(3)
55 #define PIR_MDO BIT(2)
56 #define PIR_MMD BIT(1)
57 #define PIR_MDC BIT(0)
59 #define ECMR_TRCCM BIT(26)
60 #define ECMR_RZPF BIT(20)
61 #define ECMR_PFR BIT(18)
62 #define ECMR_RXF BIT(17)
63 #define ECMR_RE BIT(6)
64 #define ECMR_TE BIT(5)
65 #define ECMR_DM BIT(1)
66 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_PFR | ECMR_RXF)
69 #define RAVB_NUM_BASE_DESC 16
70 #define RAVB_NUM_TX_DESC 8
71 #define RAVB_NUM_RX_DESC 8
73 #define RAVB_TX_QUEUE_OFFSET 0
74 #define RAVB_RX_QUEUE_OFFSET 4
76 #define RAVB_DESC_DT(n) ((n) << 28)
77 #define RAVB_DESC_DT_FSINGLE RAVB_DESC_DT(0x7)
78 #define RAVB_DESC_DT_LINKFIX RAVB_DESC_DT(0x9)
79 #define RAVB_DESC_DT_EOS RAVB_DESC_DT(0xa)
80 #define RAVB_DESC_DT_FEMPTY RAVB_DESC_DT(0xc)
81 #define RAVB_DESC_DT_EEMPTY RAVB_DESC_DT(0x3)
82 #define RAVB_DESC_DT_MASK RAVB_DESC_DT(0xf)
84 #define RAVB_DESC_DS(n) (((n) & 0xfff) << 0)
85 #define RAVB_DESC_DS_MASK 0xfff
87 #define RAVB_RX_DESC_MSC_MC BIT(23)
88 #define RAVB_RX_DESC_MSC_CEEF BIT(22)
89 #define RAVB_RX_DESC_MSC_CRL BIT(21)
90 #define RAVB_RX_DESC_MSC_FRE BIT(20)
91 #define RAVB_RX_DESC_MSC_RTLF BIT(19)
92 #define RAVB_RX_DESC_MSC_RTSF BIT(18)
93 #define RAVB_RX_DESC_MSC_RFE BIT(17)
94 #define RAVB_RX_DESC_MSC_CRC BIT(16)
95 #define RAVB_RX_DESC_MSC_MASK (0xff << 16)
97 #define RAVB_RX_DESC_MSC_RX_ERR_MASK \
98 (RAVB_RX_DESC_MSC_CRC | RAVB_RX_DESC_MSC_RFE | RAVB_RX_DESC_MSC_RTLF | \
99 RAVB_RX_DESC_MSC_RTSF | RAVB_RX_DESC_MSC_CEEF)
101 #define RAVB_TX_TIMEOUT_MS 1000
109 struct ravb_desc data
;
110 struct ravb_desc link
;
112 u8 packet
[PKTSIZE_ALIGN
];
116 struct ravb_desc base_desc
[RAVB_NUM_BASE_DESC
];
117 struct ravb_desc tx_desc
[RAVB_NUM_TX_DESC
];
118 struct ravb_rxdesc rx_desc
[RAVB_NUM_RX_DESC
];
122 struct phy_device
*phydev
;
124 void __iomem
*iobase
;
126 struct gpio_desc reset_gpio
;
129 static inline void ravb_flush_dcache(u32 addr
, u32 len
)
131 flush_dcache_range(addr
, addr
+ len
);
134 static inline void ravb_invalidate_dcache(u32 addr
, u32 len
)
136 u32 start
= addr
& ~((uintptr_t)ARCH_DMA_MINALIGN
- 1);
137 u32 end
= roundup(addr
+ len
, ARCH_DMA_MINALIGN
);
138 invalidate_dcache_range(start
, end
);
141 static int ravb_send(struct udevice
*dev
, void *packet
, int len
)
143 struct ravb_priv
*eth
= dev_get_priv(dev
);
144 struct ravb_desc
*desc
= ð
->tx_desc
[eth
->tx_desc_idx
];
147 /* Update TX descriptor */
148 ravb_flush_dcache((uintptr_t)packet
, len
);
149 memset(desc
, 0x0, sizeof(*desc
));
150 desc
->ctrl
= RAVB_DESC_DT_FSINGLE
| RAVB_DESC_DS(len
);
151 desc
->dptr
= (uintptr_t)packet
;
152 ravb_flush_dcache((uintptr_t)desc
, sizeof(*desc
));
154 /* Restart the transmitter if disabled */
155 if (!(readl(eth
->iobase
+ RAVB_REG_TCCR
) & TCCR_TSRQ0
))
156 setbits_le32(eth
->iobase
+ RAVB_REG_TCCR
, TCCR_TSRQ0
);
158 /* Wait until packet is transmitted */
159 start
= get_timer(0);
160 while (get_timer(start
) < RAVB_TX_TIMEOUT_MS
) {
161 ravb_invalidate_dcache((uintptr_t)desc
, sizeof(*desc
));
162 if ((desc
->ctrl
& RAVB_DESC_DT_MASK
) != RAVB_DESC_DT_FSINGLE
)
167 if (get_timer(start
) >= RAVB_TX_TIMEOUT_MS
)
170 eth
->tx_desc_idx
= (eth
->tx_desc_idx
+ 1) % (RAVB_NUM_TX_DESC
- 1);
174 static int ravb_recv(struct udevice
*dev
, int flags
, uchar
**packetp
)
176 struct ravb_priv
*eth
= dev_get_priv(dev
);
177 struct ravb_rxdesc
*desc
= ð
->rx_desc
[eth
->rx_desc_idx
];
181 /* Check if the rx descriptor is ready */
182 ravb_invalidate_dcache((uintptr_t)desc
, sizeof(*desc
));
183 if ((desc
->data
.ctrl
& RAVB_DESC_DT_MASK
) == RAVB_DESC_DT_FEMPTY
)
186 /* Check for errors */
187 if (desc
->data
.ctrl
& RAVB_RX_DESC_MSC_RX_ERR_MASK
) {
188 desc
->data
.ctrl
&= ~RAVB_RX_DESC_MSC_MASK
;
192 len
= desc
->data
.ctrl
& RAVB_DESC_DS_MASK
;
193 packet
= (u8
*)(uintptr_t)desc
->data
.dptr
;
194 ravb_invalidate_dcache((uintptr_t)packet
, len
);
200 static int ravb_free_pkt(struct udevice
*dev
, uchar
*packet
, int length
)
202 struct ravb_priv
*eth
= dev_get_priv(dev
);
203 struct ravb_rxdesc
*desc
= ð
->rx_desc
[eth
->rx_desc_idx
];
205 /* Make current descriptor available again */
206 desc
->data
.ctrl
= RAVB_DESC_DT_FEMPTY
| RAVB_DESC_DS(PKTSIZE_ALIGN
);
207 ravb_flush_dcache((uintptr_t)desc
, sizeof(*desc
));
209 /* Point to the next descriptor */
210 eth
->rx_desc_idx
= (eth
->rx_desc_idx
+ 1) % RAVB_NUM_RX_DESC
;
211 desc
= ð
->rx_desc
[eth
->rx_desc_idx
];
212 ravb_invalidate_dcache((uintptr_t)desc
, sizeof(*desc
));
217 static int ravb_reset(struct udevice
*dev
)
219 struct ravb_priv
*eth
= dev_get_priv(dev
);
221 /* Set config mode */
222 writel(CCC_OPC_CONFIG
, eth
->iobase
+ RAVB_REG_CCC
);
224 /* Check the operating mode is changed to the config mode. */
225 return wait_for_bit_le32(eth
->iobase
+ RAVB_REG_CSR
,
226 CSR_OPS_CONFIG
, true, 100, true);
229 static void ravb_base_desc_init(struct ravb_priv
*eth
)
231 const u32 desc_size
= RAVB_NUM_BASE_DESC
* sizeof(struct ravb_desc
);
234 /* Initialize all descriptors */
235 memset(eth
->base_desc
, 0x0, desc_size
);
237 for (i
= 0; i
< RAVB_NUM_BASE_DESC
; i
++)
238 eth
->base_desc
[i
].ctrl
= RAVB_DESC_DT_EOS
;
240 ravb_flush_dcache((uintptr_t)eth
->base_desc
, desc_size
);
242 /* Register the descriptor base address table */
243 writel((uintptr_t)eth
->base_desc
, eth
->iobase
+ RAVB_REG_DBAT
);
246 static void ravb_tx_desc_init(struct ravb_priv
*eth
)
248 const u32 desc_size
= RAVB_NUM_TX_DESC
* sizeof(struct ravb_desc
);
251 /* Initialize all descriptors */
252 memset(eth
->tx_desc
, 0x0, desc_size
);
253 eth
->tx_desc_idx
= 0;
255 for (i
= 0; i
< RAVB_NUM_TX_DESC
; i
++)
256 eth
->tx_desc
[i
].ctrl
= RAVB_DESC_DT_EEMPTY
;
258 /* Mark the end of the descriptors */
259 eth
->tx_desc
[RAVB_NUM_TX_DESC
- 1].ctrl
= RAVB_DESC_DT_LINKFIX
;
260 eth
->tx_desc
[RAVB_NUM_TX_DESC
- 1].dptr
= (uintptr_t)eth
->tx_desc
;
261 ravb_flush_dcache((uintptr_t)eth
->tx_desc
, desc_size
);
263 /* Point the controller to the TX descriptor list. */
264 eth
->base_desc
[RAVB_TX_QUEUE_OFFSET
].ctrl
= RAVB_DESC_DT_LINKFIX
;
265 eth
->base_desc
[RAVB_TX_QUEUE_OFFSET
].dptr
= (uintptr_t)eth
->tx_desc
;
266 ravb_flush_dcache((uintptr_t)ð
->base_desc
[RAVB_TX_QUEUE_OFFSET
],
267 sizeof(struct ravb_desc
));
270 static void ravb_rx_desc_init(struct ravb_priv
*eth
)
272 const u32 desc_size
= RAVB_NUM_RX_DESC
* sizeof(struct ravb_rxdesc
);
275 /* Initialize all descriptors */
276 memset(eth
->rx_desc
, 0x0, desc_size
);
277 eth
->rx_desc_idx
= 0;
279 for (i
= 0; i
< RAVB_NUM_RX_DESC
; i
++) {
280 eth
->rx_desc
[i
].data
.ctrl
= RAVB_DESC_DT_EEMPTY
|
281 RAVB_DESC_DS(PKTSIZE_ALIGN
);
282 eth
->rx_desc
[i
].data
.dptr
= (uintptr_t)eth
->rx_desc
[i
].packet
;
284 eth
->rx_desc
[i
].link
.ctrl
= RAVB_DESC_DT_LINKFIX
;
285 eth
->rx_desc
[i
].link
.dptr
= (uintptr_t)ð
->rx_desc
[i
+ 1];
288 /* Mark the end of the descriptors */
289 eth
->rx_desc
[RAVB_NUM_RX_DESC
- 1].link
.ctrl
= RAVB_DESC_DT_LINKFIX
;
290 eth
->rx_desc
[RAVB_NUM_RX_DESC
- 1].link
.dptr
= (uintptr_t)eth
->rx_desc
;
291 ravb_flush_dcache((uintptr_t)eth
->rx_desc
, desc_size
);
293 /* Point the controller to the rx descriptor list */
294 eth
->base_desc
[RAVB_RX_QUEUE_OFFSET
].ctrl
= RAVB_DESC_DT_LINKFIX
;
295 eth
->base_desc
[RAVB_RX_QUEUE_OFFSET
].dptr
= (uintptr_t)eth
->rx_desc
;
296 ravb_flush_dcache((uintptr_t)ð
->base_desc
[RAVB_RX_QUEUE_OFFSET
],
297 sizeof(struct ravb_desc
));
300 static int ravb_phy_config(struct udevice
*dev
)
302 struct ravb_priv
*eth
= dev_get_priv(dev
);
303 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
304 struct phy_device
*phydev
;
305 int mask
= 0xffffffff, reg
;
307 if (dm_gpio_is_valid(ð
->reset_gpio
)) {
308 dm_gpio_set_value(ð
->reset_gpio
, 1);
310 dm_gpio_set_value(ð
->reset_gpio
, 0);
314 phydev
= phy_find_by_mask(eth
->bus
, mask
, pdata
->phy_interface
);
318 phy_connect_dev(phydev
, dev
);
320 eth
->phydev
= phydev
;
322 /* 10BASE is not supported for Ethernet AVB MAC */
323 phydev
->supported
&= ~(SUPPORTED_10baseT_Full
324 | SUPPORTED_10baseT_Half
);
325 if (pdata
->max_speed
!= 1000) {
326 phydev
->supported
&= ~(SUPPORTED_1000baseT_Half
327 | SUPPORTED_1000baseT_Full
);
328 reg
= phy_read(phydev
, -1, MII_CTRL1000
);
329 reg
&= ~(BIT(9) | BIT(8));
330 phy_write(phydev
, -1, MII_CTRL1000
, reg
);
338 /* Set Mac address */
339 static int ravb_write_hwaddr(struct udevice
*dev
)
341 struct ravb_priv
*eth
= dev_get_priv(dev
);
342 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
343 unsigned char *mac
= pdata
->enetaddr
;
345 writel((mac
[0] << 24) | (mac
[1] << 16) | (mac
[2] << 8) | mac
[3],
346 eth
->iobase
+ RAVB_REG_MAHR
);
348 writel((mac
[4] << 8) | mac
[5], eth
->iobase
+ RAVB_REG_MALR
);
353 /* E-MAC init function */
354 static int ravb_mac_init(struct ravb_priv
*eth
)
356 /* Disable MAC Interrupt */
357 writel(0, eth
->iobase
+ RAVB_REG_ECSIPR
);
359 /* Recv frame limit set register */
360 writel(RFLR_RFL_MIN
, eth
->iobase
+ RAVB_REG_RFLR
);
365 /* AVB-DMAC init function */
366 static int ravb_dmac_init(struct udevice
*dev
)
368 struct ravb_priv
*eth
= dev_get_priv(dev
);
369 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
372 /* Set CONFIG mode */
373 ret
= ravb_reset(dev
);
377 /* Disable all interrupts */
378 writel(0, eth
->iobase
+ RAVB_REG_RIC0
);
379 writel(0, eth
->iobase
+ RAVB_REG_RIC1
);
380 writel(0, eth
->iobase
+ RAVB_REG_RIC2
);
381 writel(0, eth
->iobase
+ RAVB_REG_TIC
);
383 /* Set little endian */
384 clrbits_le32(eth
->iobase
+ RAVB_REG_CCC
, CCC_BOC
);
387 writel(0x18000001, eth
->iobase
+ RAVB_REG_RCR
);
390 writel(0x00222210, eth
->iobase
+ RAVB_REG_TGC
);
393 if (pdata
->max_speed
== 1000)
394 writel(BIT(14), eth
->iobase
+ RAVB_REG_APSR
);
399 static int ravb_config(struct udevice
*dev
)
401 struct ravb_priv
*eth
= dev_get_priv(dev
);
402 struct phy_device
*phy
;
403 u32 mask
= ECMR_CHG_DM
| ECMR_RE
| ECMR_TE
;
406 /* Configure AVB-DMAC register */
409 /* Configure E-MAC registers */
411 ravb_write_hwaddr(dev
);
414 ret
= ravb_phy_config(dev
);
420 ret
= phy_startup(phy
);
424 /* Set the transfer speed */
425 if (phy
->speed
== 100)
426 writel(0, eth
->iobase
+ RAVB_REG_GECMR
);
427 else if (phy
->speed
== 1000)
428 writel(1, eth
->iobase
+ RAVB_REG_GECMR
);
430 /* Check if full duplex mode is supported by the phy */
434 writel(mask
, eth
->iobase
+ RAVB_REG_ECMR
);
436 phy
->drv
->writeext(phy
, -1, 0x02, 0x08, (0x0f << 5) | 0x19);
441 static int ravb_start(struct udevice
*dev
)
443 struct ravb_priv
*eth
= dev_get_priv(dev
);
446 ret
= clk_enable(ð
->clk
);
450 ret
= ravb_reset(dev
);
454 ravb_base_desc_init(eth
);
455 ravb_tx_desc_init(eth
);
456 ravb_rx_desc_init(eth
);
458 ret
= ravb_config(dev
);
462 /* Setting the control will start the AVB-DMAC process. */
463 writel(CCC_OPC_OPERATION
, eth
->iobase
+ RAVB_REG_CCC
);
468 clk_disable(ð
->clk
);
472 static void ravb_stop(struct udevice
*dev
)
474 struct ravb_priv
*eth
= dev_get_priv(dev
);
477 clk_disable(ð
->clk
);
480 static int ravb_probe(struct udevice
*dev
)
482 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
483 struct ravb_priv
*eth
= dev_get_priv(dev
);
484 struct mii_dev
*mdiodev
;
485 void __iomem
*iobase
;
488 iobase
= map_physmem(pdata
->iobase
, 0x1000, MAP_NOCACHE
);
489 eth
->iobase
= iobase
;
491 ret
= clk_get_by_index(dev
, 0, ð
->clk
);
495 gpio_request_by_name(dev
, "reset-gpios", 0, ð
->reset_gpio
,
498 mdiodev
= mdio_alloc();
504 mdiodev
->read
= bb_miiphy_read
;
505 mdiodev
->write
= bb_miiphy_write
;
506 bb_miiphy_buses
[0].priv
= eth
;
507 snprintf(mdiodev
->name
, sizeof(mdiodev
->name
), dev
->name
);
509 ret
= mdio_register(mdiodev
);
511 goto err_mdio_register
;
513 eth
->bus
= miiphy_get_dev_by_name(dev
->name
);
520 unmap_physmem(eth
->iobase
, MAP_NOCACHE
);
524 static int ravb_remove(struct udevice
*dev
)
526 struct ravb_priv
*eth
= dev_get_priv(dev
);
529 mdio_unregister(eth
->bus
);
531 if (dm_gpio_is_valid(ð
->reset_gpio
))
532 dm_gpio_free(dev
, ð
->reset_gpio
);
533 unmap_physmem(eth
->iobase
, MAP_NOCACHE
);
538 int ravb_bb_init(struct bb_miiphy_bus
*bus
)
543 int ravb_bb_mdio_active(struct bb_miiphy_bus
*bus
)
545 struct ravb_priv
*eth
= bus
->priv
;
547 setbits_le32(eth
->iobase
+ RAVB_REG_PIR
, PIR_MMD
);
552 int ravb_bb_mdio_tristate(struct bb_miiphy_bus
*bus
)
554 struct ravb_priv
*eth
= bus
->priv
;
556 clrbits_le32(eth
->iobase
+ RAVB_REG_PIR
, PIR_MMD
);
561 int ravb_bb_set_mdio(struct bb_miiphy_bus
*bus
, int v
)
563 struct ravb_priv
*eth
= bus
->priv
;
566 setbits_le32(eth
->iobase
+ RAVB_REG_PIR
, PIR_MDO
);
568 clrbits_le32(eth
->iobase
+ RAVB_REG_PIR
, PIR_MDO
);
573 int ravb_bb_get_mdio(struct bb_miiphy_bus
*bus
, int *v
)
575 struct ravb_priv
*eth
= bus
->priv
;
577 *v
= (readl(eth
->iobase
+ RAVB_REG_PIR
) & PIR_MDI
) >> 3;
582 int ravb_bb_set_mdc(struct bb_miiphy_bus
*bus
, int v
)
584 struct ravb_priv
*eth
= bus
->priv
;
587 setbits_le32(eth
->iobase
+ RAVB_REG_PIR
, PIR_MDC
);
589 clrbits_le32(eth
->iobase
+ RAVB_REG_PIR
, PIR_MDC
);
594 int ravb_bb_delay(struct bb_miiphy_bus
*bus
)
601 struct bb_miiphy_bus bb_miiphy_buses
[] = {
604 .init
= ravb_bb_init
,
605 .mdio_active
= ravb_bb_mdio_active
,
606 .mdio_tristate
= ravb_bb_mdio_tristate
,
607 .set_mdio
= ravb_bb_set_mdio
,
608 .get_mdio
= ravb_bb_get_mdio
,
609 .set_mdc
= ravb_bb_set_mdc
,
610 .delay
= ravb_bb_delay
,
613 int bb_miiphy_buses_num
= ARRAY_SIZE(bb_miiphy_buses
);
615 static const struct eth_ops ravb_ops
= {
619 .free_pkt
= ravb_free_pkt
,
621 .write_hwaddr
= ravb_write_hwaddr
,
624 int ravb_ofdata_to_platdata(struct udevice
*dev
)
626 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
627 const char *phy_mode
;
631 pdata
->iobase
= devfdt_get_addr(dev
);
632 pdata
->phy_interface
= -1;
633 phy_mode
= fdt_getprop(gd
->fdt_blob
, dev_of_offset(dev
), "phy-mode",
636 pdata
->phy_interface
= phy_get_interface_by_name(phy_mode
);
637 if (pdata
->phy_interface
== -1) {
638 debug("%s: Invalid PHY interface '%s'\n", __func__
, phy_mode
);
642 pdata
->max_speed
= 1000;
643 cell
= fdt_getprop(gd
->fdt_blob
, dev_of_offset(dev
), "max-speed", NULL
);
645 pdata
->max_speed
= fdt32_to_cpu(*cell
);
647 sprintf(bb_miiphy_buses
[0].name
, dev
->name
);
652 static const struct udevice_id ravb_ids
[] = {
653 { .compatible
= "renesas,etheravb-r8a7795" },
654 { .compatible
= "renesas,etheravb-r8a7796" },
655 { .compatible
= "renesas,etheravb-r8a77970" },
656 { .compatible
= "renesas,etheravb-r8a77995" },
657 { .compatible
= "renesas,etheravb-rcar-gen3" },
661 U_BOOT_DRIVER(eth_ravb
) = {
664 .of_match
= ravb_ids
,
665 .ofdata_to_platdata
= ravb_ofdata_to_platdata
,
667 .remove
= ravb_remove
,
669 .priv_auto_alloc_size
= sizeof(struct ravb_priv
),
670 .platdata_auto_alloc_size
= sizeof(struct eth_pdata
),
671 .flags
= DM_FLAG_ALLOC_PRIV_DMA
,