]>
git.ipfire.org Git - thirdparty/u-boot.git/blob - drivers/net/rtl8169.c
2 * rtl8169.c : U-Boot driver for the RealTek RTL8169
4 * Masami Komiya (mkomiya@sonare.it)
6 * Most part is taken from r8169.c of etherboot
10 /**************************************************************************
11 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
12 * Written 2003 by Timothy Legge <tlegge@rogers.com>
14 * SPDX-License-Identifier: GPL-2.0+
16 * Portions of this code based on:
17 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver
18 * for Linux kernel 2.4.x.
20 * Written 2002 ShuChen <shuchen@realtek.com.tw>
21 * See Linux Driver for full information
23 * Linux Driver Version 1.27a, 10.02.2002
26 * Jean Chen of RealTek Semiconductor Corp. for
27 * providing the evaluation NIC used to develop
28 * this driver. RealTek's support for Etherboot
34 * v1.0 11-26-2003 timlegge Initial port of Linux driver
35 * v1.5 01-17-2004 timlegge Initial driver output cleanup
37 * Indent Options: indent -kr -i8
38 ***************************************************************************/
40 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
41 * Modified to use le32_to_cpu and cpu_to_le32 properly
51 #undef DEBUG_RTL8169_TX
52 #undef DEBUG_RTL8169_RX
54 #define drv_version "v1.5"
55 #define drv_date "01-17-2004"
59 /* Condensed operations for readability. */
60 #define currticks() get_timer(0)
64 static int media
[MAX_UNITS
] = { -1, -1, -1, -1, -1, -1, -1, -1 };
66 /* MAC address length*/
67 #define MAC_ADDR_LEN 6
69 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
70 #define MAX_ETH_FRAME_SIZE 1536
72 #define TX_FIFO_THRESH 256 /* In bytes */
74 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
75 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
76 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
77 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
78 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */
79 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
81 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */
82 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */
83 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
84 #define RX_BUF_LEN 8192
86 #define RTL_MIN_IO_SIZE 0x80
87 #define TX_TIMEOUT (6*HZ)
89 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
90 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
91 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
92 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
93 #define RTL_R8(reg) readb (ioaddr + (reg))
94 #define RTL_R16(reg) readw (ioaddr + (reg))
95 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
97 #define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE
98 #define ETH_ALEN MAC_ADDR_LEN
101 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, (pci_addr_t)a)
102 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, (phys_addr_t)a)
104 enum RTL8169_registers
{
105 MAC0
= 0, /* Ethernet hardware address. */
106 MAR0
= 8, /* Multicast filter. */
107 TxDescStartAddrLow
= 0x20,
108 TxDescStartAddrHigh
= 0x24,
109 TxHDescStartAddrLow
= 0x28,
110 TxHDescStartAddrHigh
= 0x2c,
135 RxDescStartAddrLow
= 0xE4,
136 RxDescStartAddrHigh
= 0xE8,
139 FuncEventMask
= 0xF4,
140 FuncPresetState
= 0xF8,
141 FuncForceEvent
= 0xFC,
144 enum RTL8169_register_content
{
145 /*InterruptStatusBits */
149 TxDescUnavail
= 0x80,
172 Cfg9346_Unlock
= 0xC0,
177 AcceptBroadcast
= 0x08,
178 AcceptMulticast
= 0x04,
180 AcceptAllPhys
= 0x01,
187 TxInterFrameGapShift
= 24,
188 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
190 /*rtl8169_PHYstatus */
200 /*GIGABIT_PHY_registers */
203 PHY_AUTO_NEGO_REG
= 4,
204 PHY_1000_CTRL_REG
= 9,
206 /*GIGABIT_PHY_REG_BIT */
207 PHY_Restart_Auto_Nego
= 0x0200,
208 PHY_Enable_Auto_Nego
= 0x1000,
210 /* PHY_STAT_REG = 1; */
211 PHY_Auto_Nego_Comp
= 0x0020,
213 /* PHY_AUTO_NEGO_REG = 4; */
214 PHY_Cap_10_Half
= 0x0020,
215 PHY_Cap_10_Full
= 0x0040,
216 PHY_Cap_100_Half
= 0x0080,
217 PHY_Cap_100_Full
= 0x0100,
219 /* PHY_1000_CTRL_REG = 9; */
220 PHY_Cap_1000_Full
= 0x0200,
232 TBILinkOK
= 0x02000000,
237 u8 version
; /* depend on RTL8169 docs */
238 u32 RxConfigMask
; /* should clear the bits supported by this chip */
239 } rtl_chip_info
[] = {
240 {"RTL-8169", 0x00, 0xff7e1880,},
241 {"RTL-8169", 0x04, 0xff7e1880,},
242 {"RTL-8169", 0x00, 0xff7e1880,},
243 {"RTL-8169s/8110s", 0x02, 0xff7e1880,},
244 {"RTL-8169s/8110s", 0x04, 0xff7e1880,},
245 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,},
246 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,},
247 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,},
248 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,},
249 {"RTL-8101e", 0x34, 0xff7e1880,},
250 {"RTL-8100e", 0x32, 0xff7e1880,},
253 enum _DescStatusBit
{
274 /* Define the TX Descriptor */
275 static u8 tx_ring
[NUM_TX_DESC
* sizeof(struct TxDesc
) + 256];
276 /* __attribute__ ((aligned(256))); */
278 /* Create a static buffer of size RX_BUF_SZ for each
279 TX Descriptor. All descriptors point to a
280 part of this buffer */
281 static unsigned char txb
[NUM_TX_DESC
* RX_BUF_SIZE
];
283 /* Define the RX Descriptor */
284 static u8 rx_ring
[NUM_RX_DESC
* sizeof(struct TxDesc
) + 256];
285 /* __attribute__ ((aligned(256))); */
287 /* Create a static buffer of size RX_BUF_SZ for each
288 RX Descriptor All descriptors point to a
289 part of this buffer */
290 static unsigned char rxb
[NUM_RX_DESC
* RX_BUF_SIZE
];
292 struct rtl8169_private
{
293 void *mmio_addr
; /* memory map physical address */
295 unsigned long cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
296 unsigned long cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
297 unsigned long dirty_tx
;
298 unsigned char *TxDescArrays
; /* Index of Tx Descriptor buffer */
299 unsigned char *RxDescArrays
; /* Index of Rx Descriptor buffer */
300 struct TxDesc
*TxDescArray
; /* Index of 256-alignment Tx Descriptor buffer */
301 struct RxDesc
*RxDescArray
; /* Index of 256-alignment Rx Descriptor buffer */
302 unsigned char *RxBufferRings
; /* Index of Rx Buffer */
303 unsigned char *RxBufferRing
[NUM_RX_DESC
]; /* Index of Rx Buffer array */
304 unsigned char *Tx_skbuff
[NUM_TX_DESC
];
307 static struct rtl8169_private
*tpc
;
309 static const u16 rtl8169_intr_mask
=
310 SYSErr
| PCSTimeout
| RxUnderrun
| RxOverflow
| RxFIFOOver
| TxErr
|
312 static const unsigned int rtl8169_rx_config
=
313 (RX_FIFO_THRESH
<< RxCfgFIFOShift
) | (RX_DMA_BURST
<< RxCfgDMAShift
);
315 static struct pci_device_id supported
[] = {
316 {PCI_VENDOR_ID_REALTEK
, 0x8167},
317 {PCI_VENDOR_ID_REALTEK
, 0x8169},
321 void mdio_write(int RegAddr
, int value
)
325 RTL_W32(PHYAR
, 0x80000000 | (RegAddr
& 0xFF) << 16 | value
);
328 for (i
= 2000; i
> 0; i
--) {
329 /* Check if the RTL8169 has completed writing to the specified MII register */
330 if (!(RTL_R32(PHYAR
) & 0x80000000)) {
338 int mdio_read(int RegAddr
)
342 RTL_W32(PHYAR
, 0x0 | (RegAddr
& 0xFF) << 16);
345 for (i
= 2000; i
> 0; i
--) {
346 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
347 if (RTL_R32(PHYAR
) & 0x80000000) {
348 value
= (int) (RTL_R32(PHYAR
) & 0xFFFF);
357 static int rtl8169_init_board(struct eth_device
*dev
)
363 printf ("%s\n", __FUNCTION__
);
365 ioaddr
= dev
->iobase
;
367 /* Soft reset the chip. */
368 RTL_W8(ChipCmd
, CmdReset
);
370 /* Check that the chip has finished the reset. */
371 for (i
= 1000; i
> 0; i
--)
372 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
377 /* identify chip attached to board */
378 tmp
= RTL_R32(TxConfig
);
379 tmp
= ((tmp
& 0x7c000000) + ((tmp
& 0x00800000) << 2)) >> 24;
381 for (i
= ARRAY_SIZE(rtl_chip_info
) - 1; i
>= 0; i
--){
382 if (tmp
== rtl_chip_info
[i
].version
) {
388 /* if unknown chip, assume array element #0, original RTL-8169 in this case */
389 printf("PCI device %s: unknown chip version, assuming RTL-8169\n", dev
->name
);
390 printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig
));
397 /**************************************************************************
398 RECV - Receive a frame
399 ***************************************************************************/
400 static int rtl_recv(struct eth_device
*dev
)
402 /* return true if there's an ethernet packet ready to read */
403 /* nic->packet should contain data on return */
404 /* nic->packetlen should contain length of data */
408 #ifdef DEBUG_RTL8169_RX
409 printf ("%s\n", __FUNCTION__
);
411 ioaddr
= dev
->iobase
;
413 cur_rx
= tpc
->cur_rx
;
414 flush_cache((unsigned long)&tpc
->RxDescArray
[cur_rx
],
415 sizeof(struct RxDesc
));
416 if ((le32_to_cpu(tpc
->RxDescArray
[cur_rx
].status
) & OWNbit
) == 0) {
417 if (!(le32_to_cpu(tpc
->RxDescArray
[cur_rx
].status
) & RxRES
)) {
418 unsigned char rxdata
[RX_BUF_LEN
];
419 length
= (int) (le32_to_cpu(tpc
->RxDescArray
[cur_rx
].
420 status
) & 0x00001FFF) - 4;
422 memcpy(rxdata
, tpc
->RxBufferRing
[cur_rx
], length
);
423 NetReceive(rxdata
, length
);
425 if (cur_rx
== NUM_RX_DESC
- 1)
426 tpc
->RxDescArray
[cur_rx
].status
=
427 cpu_to_le32((OWNbit
| EORbit
) + RX_BUF_SIZE
);
429 tpc
->RxDescArray
[cur_rx
].status
=
430 cpu_to_le32(OWNbit
+ RX_BUF_SIZE
);
431 tpc
->RxDescArray
[cur_rx
].buf_addr
=
432 cpu_to_le32(bus_to_phys(tpc
->RxBufferRing
[cur_rx
]));
433 flush_cache((unsigned long)tpc
->RxBufferRing
[cur_rx
],
438 cur_rx
= (cur_rx
+ 1) % NUM_RX_DESC
;
439 tpc
->cur_rx
= cur_rx
;
443 ushort sts
= RTL_R8(IntrStatus
);
444 RTL_W8(IntrStatus
, sts
& ~(TxErr
| RxErr
| SYSErr
));
445 udelay(100); /* wait */
447 tpc
->cur_rx
= cur_rx
;
448 return (0); /* initially as this is called to flush the input */
452 /**************************************************************************
453 SEND - Transmit a frame
454 ***************************************************************************/
455 static int rtl_send(struct eth_device
*dev
, void *packet
, int length
)
457 /* send the packet to destination */
461 int entry
= tpc
->cur_tx
% NUM_TX_DESC
;
465 #ifdef DEBUG_RTL8169_TX
466 int stime
= currticks();
467 printf ("%s\n", __FUNCTION__
);
468 printf("sending %d bytes\n", len
);
471 ioaddr
= dev
->iobase
;
473 /* point to the current txb incase multiple tx_rings are used */
474 ptxb
= tpc
->Tx_skbuff
[entry
* MAX_ETH_FRAME_SIZE
];
475 memcpy(ptxb
, (char *)packet
, (int)length
);
476 flush_cache((unsigned long)ptxb
, length
);
478 while (len
< ETH_ZLEN
)
481 tpc
->TxDescArray
[entry
].buf_Haddr
= 0;
482 tpc
->TxDescArray
[entry
].buf_addr
= cpu_to_le32(bus_to_phys(ptxb
));
483 if (entry
!= (NUM_TX_DESC
- 1)) {
484 tpc
->TxDescArray
[entry
].status
=
485 cpu_to_le32((OWNbit
| FSbit
| LSbit
) |
486 ((len
> ETH_ZLEN
) ? len
: ETH_ZLEN
));
488 tpc
->TxDescArray
[entry
].status
=
489 cpu_to_le32((OWNbit
| EORbit
| FSbit
| LSbit
) |
490 ((len
> ETH_ZLEN
) ? len
: ETH_ZLEN
));
492 RTL_W8(TxPoll
, 0x40); /* set polling bit */
495 to
= currticks() + TX_TIMEOUT
;
497 flush_cache((unsigned long)&tpc
->TxDescArray
[entry
],
498 sizeof(struct TxDesc
));
499 } while ((le32_to_cpu(tpc
->TxDescArray
[entry
].status
) & OWNbit
)
500 && (currticks() < to
)); /* wait */
502 if (currticks() >= to
) {
503 #ifdef DEBUG_RTL8169_TX
504 puts ("tx timeout/error\n");
505 printf ("%s elapsed time : %d\n", __FUNCTION__
, currticks()-stime
);
509 #ifdef DEBUG_RTL8169_TX
514 /* Delay to make net console (nc) work properly */
519 static void rtl8169_set_rx_mode(struct eth_device
*dev
)
521 u32 mc_filter
[2]; /* Multicast hash filter */
526 printf ("%s\n", __FUNCTION__
);
530 /* Too many to filter perfectly -- accept all multicasts. */
531 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
532 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
534 tmp
= rtl8169_rx_config
| rx_mode
| (RTL_R32(RxConfig
) &
535 rtl_chip_info
[tpc
->chipset
].RxConfigMask
);
537 RTL_W32(RxConfig
, tmp
);
538 RTL_W32(MAR0
+ 0, mc_filter
[0]);
539 RTL_W32(MAR0
+ 4, mc_filter
[1]);
542 static void rtl8169_hw_start(struct eth_device
*dev
)
547 int stime
= currticks();
548 printf ("%s\n", __FUNCTION__
);
552 /* Soft reset the chip. */
553 RTL_W8(ChipCmd
, CmdReset
);
555 /* Check that the chip has finished the reset. */
556 for (i
= 1000; i
> 0; i
--) {
557 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
564 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
566 /* RTL-8169sb/8110sb or previous version */
567 if (tpc
->chipset
<= 5)
568 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
570 RTL_W8(EarlyTxThres
, EarlyTxThld
);
572 /* For gigabit rtl8169 */
573 RTL_W16(RxMaxSize
, RxPacketMaxSize
);
575 /* Set Rx Config register */
576 i
= rtl8169_rx_config
| (RTL_R32(RxConfig
) &
577 rtl_chip_info
[tpc
->chipset
].RxConfigMask
);
578 RTL_W32(RxConfig
, i
);
580 /* Set DMA burst size and Interframe Gap Time */
581 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
582 (InterFrameGap
<< TxInterFrameGapShift
));
587 RTL_W32(TxDescStartAddrLow
, bus_to_phys(tpc
->TxDescArray
));
588 RTL_W32(TxDescStartAddrHigh
, (unsigned long)0);
589 RTL_W32(RxDescStartAddrLow
, bus_to_phys(tpc
->RxDescArray
));
590 RTL_W32(RxDescStartAddrHigh
, (unsigned long)0);
592 /* RTL-8169sc/8110sc or later version */
593 if (tpc
->chipset
> 5)
594 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
596 RTL_W8(Cfg9346
, Cfg9346_Lock
);
599 RTL_W32(RxMissed
, 0);
601 rtl8169_set_rx_mode(dev
);
603 /* no early-rx interrupts */
604 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
607 printf ("%s elapsed time : %d\n", __FUNCTION__
, currticks()-stime
);
611 static void rtl8169_init_ring(struct eth_device
*dev
)
616 int stime
= currticks();
617 printf ("%s\n", __FUNCTION__
);
623 memset(tpc
->TxDescArray
, 0x0, NUM_TX_DESC
* sizeof(struct TxDesc
));
624 memset(tpc
->RxDescArray
, 0x0, NUM_RX_DESC
* sizeof(struct RxDesc
));
626 for (i
= 0; i
< NUM_TX_DESC
; i
++) {
627 tpc
->Tx_skbuff
[i
] = &txb
[i
];
630 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
631 if (i
== (NUM_RX_DESC
- 1))
632 tpc
->RxDescArray
[i
].status
=
633 cpu_to_le32((OWNbit
| EORbit
) + RX_BUF_SIZE
);
635 tpc
->RxDescArray
[i
].status
=
636 cpu_to_le32(OWNbit
+ RX_BUF_SIZE
);
638 tpc
->RxBufferRing
[i
] = &rxb
[i
* RX_BUF_SIZE
];
639 tpc
->RxDescArray
[i
].buf_addr
=
640 cpu_to_le32(bus_to_phys(tpc
->RxBufferRing
[i
]));
641 flush_cache((unsigned long)tpc
->RxBufferRing
[i
], RX_BUF_SIZE
);
645 printf ("%s elapsed time : %d\n", __FUNCTION__
, currticks()-stime
);
649 /**************************************************************************
650 RESET - Finish setting up the ethernet interface
651 ***************************************************************************/
652 static int rtl_reset(struct eth_device
*dev
, bd_t
*bis
)
657 int stime
= currticks();
658 printf ("%s\n", __FUNCTION__
);
661 tpc
->TxDescArrays
= tx_ring
;
662 /* Tx Desscriptor needs 256 bytes alignment; */
663 tpc
->TxDescArray
= (struct TxDesc
*) ((unsigned long)(tpc
->TxDescArrays
+
666 tpc
->RxDescArrays
= rx_ring
;
667 /* Rx Desscriptor needs 256 bytes alignment; */
668 tpc
->RxDescArray
= (struct RxDesc
*) ((unsigned long)(tpc
->RxDescArrays
+
671 rtl8169_init_ring(dev
);
672 rtl8169_hw_start(dev
);
673 /* Construct a perfect filter frame with the mac address as first match
674 * and broadcast for all others */
675 for (i
= 0; i
< 192; i
++)
678 txb
[0] = dev
->enetaddr
[0];
679 txb
[1] = dev
->enetaddr
[1];
680 txb
[2] = dev
->enetaddr
[2];
681 txb
[3] = dev
->enetaddr
[3];
682 txb
[4] = dev
->enetaddr
[4];
683 txb
[5] = dev
->enetaddr
[5];
686 printf ("%s elapsed time : %d\n", __FUNCTION__
, currticks()-stime
);
691 /**************************************************************************
692 HALT - Turn off ethernet interface
693 ***************************************************************************/
694 static void rtl_halt(struct eth_device
*dev
)
699 printf ("%s\n", __FUNCTION__
);
702 ioaddr
= dev
->iobase
;
704 /* Stop the chip's Tx and Rx DMA processes. */
705 RTL_W8(ChipCmd
, 0x00);
707 /* Disable interrupts by clearing the interrupt mask. */
708 RTL_W16(IntrMask
, 0x0000);
710 RTL_W32(RxMissed
, 0);
712 tpc
->TxDescArrays
= NULL
;
713 tpc
->RxDescArrays
= NULL
;
714 tpc
->TxDescArray
= NULL
;
715 tpc
->RxDescArray
= NULL
;
716 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
717 tpc
->RxBufferRing
[i
] = NULL
;
721 /**************************************************************************
722 INIT - Look for an adapter, this routine's visible to the outside
723 ***************************************************************************/
725 #define board_found 1
727 static int rtl_init(struct eth_device
*dev
, bd_t
*bis
)
729 static int board_idx
= -1;
731 int option
= -1, Cap10_100
= 0, Cap1000
= 0;
734 printf ("%s\n", __FUNCTION__
);
737 ioaddr
= dev
->iobase
;
741 /* point to private storage */
744 rc
= rtl8169_init_board(dev
);
748 /* Get MAC address. FIXME: read EEPROM */
749 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
750 dev
->enetaddr
[i
] = RTL_R8(MAC0
+ i
);
753 printf("chipset = %d\n", tpc
->chipset
);
754 printf("MAC Address");
755 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
756 printf(":%02x", dev
->enetaddr
[i
]);
761 /* Print out some hardware info */
762 printf("%s: at ioaddr 0x%x\n", dev
->name
, ioaddr
);
765 /* if TBI is not endbled */
766 if (!(RTL_R8(PHYstatus
) & TBI_Enable
)) {
767 int val
= mdio_read(PHY_AUTO_NEGO_REG
);
769 option
= (board_idx
>= MAX_UNITS
) ? 0 : media
[board_idx
];
770 /* Force RTL8169 in 10/100/1000 Full/Half mode. */
773 printf("%s: Force-mode Enabled.\n", dev
->name
);
775 Cap10_100
= 0, Cap1000
= 0;
778 Cap10_100
= PHY_Cap_10_Half
;
779 Cap1000
= PHY_Cap_Null
;
782 Cap10_100
= PHY_Cap_10_Full
;
783 Cap1000
= PHY_Cap_Null
;
786 Cap10_100
= PHY_Cap_100_Half
;
787 Cap1000
= PHY_Cap_Null
;
790 Cap10_100
= PHY_Cap_100_Full
;
791 Cap1000
= PHY_Cap_Null
;
794 Cap10_100
= PHY_Cap_Null
;
795 Cap1000
= PHY_Cap_1000_Full
;
800 mdio_write(PHY_AUTO_NEGO_REG
, Cap10_100
| (val
& 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
801 mdio_write(PHY_1000_CTRL_REG
, Cap1000
);
804 printf("%s: Auto-negotiation Enabled.\n",
807 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
808 mdio_write(PHY_AUTO_NEGO_REG
,
809 PHY_Cap_10_Half
| PHY_Cap_10_Full
|
810 PHY_Cap_100_Half
| PHY_Cap_100_Full
|
813 /* enable 1000 Full Mode */
814 mdio_write(PHY_1000_CTRL_REG
, PHY_Cap_1000_Full
);
818 /* Enable auto-negotiation and restart auto-nigotiation */
819 mdio_write(PHY_CTRL_REG
,
820 PHY_Enable_Auto_Nego
| PHY_Restart_Auto_Nego
);
823 /* wait for auto-negotiation process */
824 for (i
= 10000; i
> 0; i
--) {
825 /* check if auto-negotiation complete */
826 if (mdio_read(PHY_STAT_REG
) & PHY_Auto_Nego_Comp
) {
828 option
= RTL_R8(PHYstatus
);
829 if (option
& _1000bpsF
) {
831 printf("%s: 1000Mbps Full-duplex operation.\n",
836 printf("%s: %sMbps %s-duplex operation.\n",
838 (option
& _100bps
) ? "100" :
840 (option
& FullDup
) ? "Full" :
848 } /* end for-loop to wait for auto-negotiation process */
854 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
856 (RTL_R32(TBICSR
) & TBILinkOK
) ? "OK" : "Failed");
863 int rtl8169_initialize(bd_t
*bis
)
867 struct eth_device
*dev
;
873 if ((devno
= pci_find_devices(supported
, idx
++)) < 0)
876 pci_read_config_dword(devno
, PCI_BASE_ADDRESS_1
, &iobase
);
879 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase
);
881 dev
= (struct eth_device
*)malloc(sizeof *dev
);
883 printf("Can not allocate memory of rtl8169\n");
887 memset(dev
, 0, sizeof(*dev
));
888 sprintf (dev
->name
, "RTL8169#%d", card_number
);
890 dev
->priv
= (void *) devno
;
891 dev
->iobase
= (int)pci_mem_to_phys(devno
, iobase
);
893 dev
->init
= rtl_reset
;
894 dev
->halt
= rtl_halt
;
895 dev
->send
= rtl_send
;
896 dev
->recv
= rtl_recv
;