1 // SPDX-License-Identifier: GPL-2.0+
3 * rtl8169.c : U-Boot driver for the RealTek RTL8169
5 * Masami Komiya (mkomiya@sonare.it)
7 * Most part is taken from r8169.c of etherboot
11 /**************************************************************************
12 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
13 * Written 2003 by Timothy Legge <tlegge@rogers.com>
15 * Portions of this code based on:
16 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver
17 * for Linux kernel 2.4.x.
19 * Written 2002 ShuChen <shuchen@realtek.com.tw>
20 * See Linux Driver for full information
22 * Linux Driver Version 1.27a, 10.02.2002
25 * Jean Chen of RealTek Semiconductor Corp. for
26 * providing the evaluation NIC used to develop
27 * this driver. RealTek's support for Etherboot
33 * v1.0 11-26-2003 timlegge Initial port of Linux driver
34 * v1.5 01-17-2004 timlegge Initial driver output cleanup
36 * Indent Options: indent -kr -i8
37 ***************************************************************************/
39 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
40 * Modified to use le32_to_cpu and cpu_to_le32 properly
52 #include <asm/cache.h>
57 #undef DEBUG_RTL8169_TX
58 #undef DEBUG_RTL8169_RX
60 #define drv_version "v1.5"
61 #define drv_date "01-17-2004"
63 static unsigned long ioaddr
;
65 /* Condensed operations for readability. */
66 #define currticks() get_timer(0)
70 static int media
[MAX_UNITS
] = { -1, -1, -1, -1, -1, -1, -1, -1 };
72 /* MAC address length*/
73 #define MAC_ADDR_LEN 6
75 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
76 #define MAX_ETH_FRAME_SIZE 1536
78 #define TX_FIFO_THRESH 256 /* In bytes */
80 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
81 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
82 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
83 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
84 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */
85 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
87 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */
88 #ifdef CONFIG_SYS_RX_ETH_BUFFER
89 #define NUM_RX_DESC CONFIG_SYS_RX_ETH_BUFFER
91 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */
93 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
94 #define RX_BUF_LEN 8192
96 #define RTL_MIN_IO_SIZE 0x80
97 #define TX_TIMEOUT (6*HZ)
99 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
100 #define RTL_W8(reg, val8) writeb((val8), ioaddr + (reg))
101 #define RTL_W16(reg, val16) writew((val16), ioaddr + (reg))
102 #define RTL_W32(reg, val32) writel((val32), ioaddr + (reg))
103 #define RTL_R8(reg) readb(ioaddr + (reg))
104 #define RTL_R16(reg) readw(ioaddr + (reg))
105 #define RTL_R32(reg) readl(ioaddr + (reg))
107 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)(unsigned long)dev->priv, \
108 (pci_addr_t)(unsigned long)a)
109 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)(unsigned long)dev->priv, \
112 enum RTL8169_registers
{
113 MAC0
= 0, /* Ethernet hardware address. */
114 MAR0
= 8, /* Multicast filter. */
115 TxDescStartAddrLow
= 0x20,
116 TxDescStartAddrHigh
= 0x24,
117 TxHDescStartAddrLow
= 0x28,
118 TxHDescStartAddrHigh
= 0x2c,
143 RxDescStartAddrLow
= 0xE4,
144 RxDescStartAddrHigh
= 0xE8,
147 FuncEventMask
= 0xF4,
148 FuncPresetState
= 0xF8,
149 FuncForceEvent
= 0xFC,
152 enum RTL8169_register_content
{
153 /*InterruptStatusBits */
157 TxDescUnavail
= 0x80,
180 Cfg9346_Unlock
= 0xC0,
185 AcceptBroadcast
= 0x08,
186 AcceptMulticast
= 0x04,
188 AcceptAllPhys
= 0x01,
195 TxInterFrameGapShift
= 24,
196 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
198 /*rtl8169_PHYstatus */
208 /*GIGABIT_PHY_registers */
211 PHY_AUTO_NEGO_REG
= 4,
212 PHY_1000_CTRL_REG
= 9,
214 /*GIGABIT_PHY_REG_BIT */
215 PHY_Restart_Auto_Nego
= 0x0200,
216 PHY_Enable_Auto_Nego
= 0x1000,
218 /* PHY_STAT_REG = 1; */
219 PHY_Auto_Nego_Comp
= 0x0020,
221 /* PHY_AUTO_NEGO_REG = 4; */
222 PHY_Cap_10_Half
= 0x0020,
223 PHY_Cap_10_Full
= 0x0040,
224 PHY_Cap_100_Half
= 0x0080,
225 PHY_Cap_100_Full
= 0x0100,
227 /* PHY_1000_CTRL_REG = 9; */
228 PHY_Cap_1000_Full
= 0x0200,
240 TBILinkOK
= 0x02000000,
245 u8 version
; /* depend on RTL8169 docs */
246 u32 RxConfigMask
; /* should clear the bits supported by this chip */
247 } rtl_chip_info
[] = {
248 {"RTL-8169", 0x00, 0xff7e1880,},
249 {"RTL-8169", 0x04, 0xff7e1880,},
250 {"RTL-8169", 0x00, 0xff7e1880,},
251 {"RTL-8169s/8110s", 0x02, 0xff7e1880,},
252 {"RTL-8169s/8110s", 0x04, 0xff7e1880,},
253 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,},
254 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,},
255 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,},
256 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,},
257 {"RTL-8168c/8111c", 0x3c, 0xff7e1880,},
258 {"RTL-8168d/8111d", 0x28, 0xff7e1880,},
259 {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,},
260 {"RTL-8168/8111g", 0x4c, 0xff7e1880,},
261 {"RTL-8101e", 0x34, 0xff7e1880,},
262 {"RTL-8100e", 0x32, 0xff7e1880,},
263 {"RTL-8168h/8111h", 0x54, 0xff7e1880,},
266 enum _DescStatusBit
{
287 static unsigned char rxdata
[RX_BUF_LEN
];
289 #define RTL8169_DESC_SIZE 16
291 #if ARCH_DMA_MINALIGN > 256
292 # define RTL8169_ALIGN ARCH_DMA_MINALIGN
294 # define RTL8169_ALIGN 256
298 * Warn if the cache-line size is larger than the descriptor size. In such
299 * cases the driver will likely fail because the CPU needs to flush the cache
300 * when requeuing RX buffers, therefore descriptors written by the hardware
303 * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
304 * the driver to allocate descriptors from a pool of non-cached memory.
306 #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN
307 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
308 !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
309 #warning cache-line size is larger than descriptor size
314 * Create a static buffer of size RX_BUF_SZ for each TX Descriptor. All
315 * descriptors point to a part of this buffer.
317 DEFINE_ALIGN_BUFFER(u8
, txb
, NUM_TX_DESC
* RX_BUF_SIZE
, RTL8169_ALIGN
);
320 * Create a static buffer of size RX_BUF_SZ for each RX Descriptor. All
321 * descriptors point to a part of this buffer.
323 DEFINE_ALIGN_BUFFER(u8
, rxb
, NUM_RX_DESC
* RX_BUF_SIZE
, RTL8169_ALIGN
);
325 struct rtl8169_private
{
327 void *mmio_addr
; /* memory map physical address */
329 unsigned long cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
330 unsigned long cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
331 unsigned long dirty_tx
;
332 struct TxDesc
*TxDescArray
; /* Index of 256-alignment Tx Descriptor buffer */
333 struct RxDesc
*RxDescArray
; /* Index of 256-alignment Rx Descriptor buffer */
334 unsigned char *RxBufferRings
; /* Index of Rx Buffer */
335 unsigned char *RxBufferRing
[NUM_RX_DESC
]; /* Index of Rx Buffer array */
336 unsigned char *Tx_skbuff
[NUM_TX_DESC
];
339 static struct rtl8169_private
*tpc
;
341 static const unsigned int rtl8169_rx_config
=
342 (RX_FIFO_THRESH
<< RxCfgFIFOShift
) | (RX_DMA_BURST
<< RxCfgDMAShift
);
344 static struct pci_device_id supported
[] = {
345 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167) },
346 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168) },
347 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169) },
351 void mdio_write(int RegAddr
, int value
)
355 RTL_W32(PHYAR
, 0x80000000 | (RegAddr
& 0xFF) << 16 | value
);
358 for (i
= 2000; i
> 0; i
--) {
359 /* Check if the RTL8169 has completed writing to the specified MII register */
360 if (!(RTL_R32(PHYAR
) & 0x80000000)) {
368 int mdio_read(int RegAddr
)
372 RTL_W32(PHYAR
, 0x0 | (RegAddr
& 0xFF) << 16);
375 for (i
= 2000; i
> 0; i
--) {
376 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
377 if (RTL_R32(PHYAR
) & 0x80000000) {
378 value
= (int) (RTL_R32(PHYAR
) & 0xFFFF);
387 static int rtl8169_init_board(unsigned long dev_iobase
, const char *name
)
393 printf ("%s\n", __FUNCTION__
);
397 /* Soft reset the chip. */
398 RTL_W8(ChipCmd
, CmdReset
);
400 /* Check that the chip has finished the reset. */
401 for (i
= 1000; i
> 0; i
--)
402 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
407 /* identify chip attached to board */
408 tmp
= RTL_R32(TxConfig
);
409 tmp
= ((tmp
& 0x7c000000) + ((tmp
& 0x00800000) << 2)) >> 24;
411 for (i
= ARRAY_SIZE(rtl_chip_info
) - 1; i
>= 0; i
--){
412 if (tmp
== rtl_chip_info
[i
].version
) {
418 /* if unknown chip, assume array element #0, original RTL-8169 in this case */
419 printf("PCI device %s: unknown chip version, assuming RTL-8169\n",
421 printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig
));
429 * TX and RX descriptors are 16 bytes. This causes problems with the cache
430 * maintenance on CPUs where the cache-line size exceeds the size of these
431 * descriptors. What will happen is that when the driver receives a packet
432 * it will be immediately requeued for the hardware to reuse. The CPU will
433 * therefore need to flush the cache-line containing the descriptor, which
434 * will cause all other descriptors in the same cache-line to be flushed
435 * along with it. If one of those descriptors had been written to by the
436 * device those changes (and the associated packet) will be lost.
438 * To work around this, we make use of non-cached memory if available. If
439 * descriptors are mapped uncached there's no need to manually flush them
440 * or invalidate them.
442 * Note that this only applies to descriptors. The packet data buffers do
443 * not have the same constraints since they are 1536 bytes large, so they
444 * are unlikely to share cache-lines.
446 static void *rtl_alloc_descs(unsigned int num
)
448 size_t size
= num
* RTL8169_DESC_SIZE
;
450 #ifdef CONFIG_SYS_NONCACHED_MEMORY
451 return (void *)noncached_alloc(size
, RTL8169_ALIGN
);
453 return memalign(RTL8169_ALIGN
, size
);
458 * Cache maintenance functions. These are simple wrappers around the more
459 * general purpose flush_cache() and invalidate_dcache_range() functions.
462 static void rtl_inval_rx_desc(struct RxDesc
*desc
)
464 #ifndef CONFIG_SYS_NONCACHED_MEMORY
465 unsigned long start
= (unsigned long)desc
& ~(ARCH_DMA_MINALIGN
- 1);
466 unsigned long end
= ALIGN(start
+ sizeof(*desc
), ARCH_DMA_MINALIGN
);
468 invalidate_dcache_range(start
, end
);
472 static void rtl_flush_rx_desc(struct RxDesc
*desc
)
474 #ifndef CONFIG_SYS_NONCACHED_MEMORY
475 flush_cache((unsigned long)desc
, sizeof(*desc
));
479 static void rtl_inval_tx_desc(struct TxDesc
*desc
)
481 #ifndef CONFIG_SYS_NONCACHED_MEMORY
482 unsigned long start
= (unsigned long)desc
& ~(ARCH_DMA_MINALIGN
- 1);
483 unsigned long end
= ALIGN(start
+ sizeof(*desc
), ARCH_DMA_MINALIGN
);
485 invalidate_dcache_range(start
, end
);
489 static void rtl_flush_tx_desc(struct TxDesc
*desc
)
491 #ifndef CONFIG_SYS_NONCACHED_MEMORY
492 flush_cache((unsigned long)desc
, sizeof(*desc
));
496 static void rtl_inval_buffer(void *buf
, size_t size
)
498 unsigned long start
= (unsigned long)buf
& ~(ARCH_DMA_MINALIGN
- 1);
499 unsigned long end
= ALIGN(start
+ size
, ARCH_DMA_MINALIGN
);
501 invalidate_dcache_range(start
, end
);
504 static void rtl_flush_buffer(void *buf
, size_t size
)
506 flush_cache((unsigned long)buf
, size
);
509 /**************************************************************************
510 RECV - Receive a frame
511 ***************************************************************************/
513 static int rtl_recv_common(struct udevice
*dev
, unsigned long dev_iobase
,
516 static int rtl_recv_common(pci_dev_t dev
, unsigned long dev_iobase
,
520 /* return true if there's an ethernet packet ready to read */
521 /* nic->packet should contain data on return */
522 /* nic->packetlen should contain length of data */
526 #ifdef DEBUG_RTL8169_RX
527 printf ("%s\n", __FUNCTION__
);
531 cur_rx
= tpc
->cur_rx
;
533 rtl_inval_rx_desc(&tpc
->RxDescArray
[cur_rx
]);
535 if ((le32_to_cpu(tpc
->RxDescArray
[cur_rx
].status
) & OWNbit
) == 0) {
536 if (!(le32_to_cpu(tpc
->RxDescArray
[cur_rx
].status
) & RxRES
)) {
537 length
= (int) (le32_to_cpu(tpc
->RxDescArray
[cur_rx
].
538 status
) & 0x00001FFF) - 4;
540 rtl_inval_buffer(tpc
->RxBufferRing
[cur_rx
], length
);
541 memcpy(rxdata
, tpc
->RxBufferRing
[cur_rx
], length
);
543 if (cur_rx
== NUM_RX_DESC
- 1)
544 tpc
->RxDescArray
[cur_rx
].status
=
545 cpu_to_le32((OWNbit
| EORbit
) + RX_BUF_SIZE
);
547 tpc
->RxDescArray
[cur_rx
].status
=
548 cpu_to_le32(OWNbit
+ RX_BUF_SIZE
);
550 tpc
->RxDescArray
[cur_rx
].buf_addr
= cpu_to_le32(
551 dm_pci_mem_to_phys(dev
,
552 (pci_addr_t
)(unsigned long)
553 tpc
->RxBufferRing
[cur_rx
]));
555 tpc
->RxDescArray
[cur_rx
].buf_addr
= cpu_to_le32(
556 pci_mem_to_phys(dev
, (pci_addr_t
)(unsigned long)
557 tpc
->RxBufferRing
[cur_rx
]));
559 rtl_flush_rx_desc(&tpc
->RxDescArray
[cur_rx
]);
563 net_process_received_packet(rxdata
, length
);
569 cur_rx
= (cur_rx
+ 1) % NUM_RX_DESC
;
570 tpc
->cur_rx
= cur_rx
;
574 ushort sts
= RTL_R8(IntrStatus
);
575 RTL_W8(IntrStatus
, sts
& ~(TxErr
| RxErr
| SYSErr
));
576 udelay(100); /* wait */
578 tpc
->cur_rx
= cur_rx
;
579 return (0); /* initially as this is called to flush the input */
583 int rtl8169_eth_recv(struct udevice
*dev
, int flags
, uchar
**packetp
)
585 struct rtl8169_private
*priv
= dev_get_priv(dev
);
587 return rtl_recv_common(dev
, priv
->iobase
, packetp
);
590 static int rtl_recv(struct eth_device
*dev
)
592 return rtl_recv_common((pci_dev_t
)(unsigned long)dev
->priv
,
595 #endif /* nCONFIG_DM_ETH */
598 /**************************************************************************
599 SEND - Transmit a frame
600 ***************************************************************************/
602 static int rtl_send_common(struct udevice
*dev
, unsigned long dev_iobase
,
603 void *packet
, int length
)
605 static int rtl_send_common(pci_dev_t dev
, unsigned long dev_iobase
,
606 void *packet
, int length
)
609 /* send the packet to destination */
613 int entry
= tpc
->cur_tx
% NUM_TX_DESC
;
617 #ifdef DEBUG_RTL8169_TX
618 int stime
= currticks();
619 printf ("%s\n", __FUNCTION__
);
620 printf("sending %d bytes\n", len
);
625 /* point to the current txb incase multiple tx_rings are used */
626 ptxb
= tpc
->Tx_skbuff
[entry
* MAX_ETH_FRAME_SIZE
];
627 memcpy(ptxb
, (char *)packet
, (int)length
);
629 while (len
< ETH_ZLEN
)
632 rtl_flush_buffer(ptxb
, ALIGN(len
, RTL8169_ALIGN
));
634 tpc
->TxDescArray
[entry
].buf_Haddr
= 0;
636 tpc
->TxDescArray
[entry
].buf_addr
= cpu_to_le32(
637 dm_pci_mem_to_phys(dev
, (pci_addr_t
)(unsigned long)ptxb
));
639 tpc
->TxDescArray
[entry
].buf_addr
= cpu_to_le32(
640 pci_mem_to_phys(dev
, (pci_addr_t
)(unsigned long)ptxb
));
642 if (entry
!= (NUM_TX_DESC
- 1)) {
643 tpc
->TxDescArray
[entry
].status
=
644 cpu_to_le32((OWNbit
| FSbit
| LSbit
) |
645 ((len
> ETH_ZLEN
) ? len
: ETH_ZLEN
));
647 tpc
->TxDescArray
[entry
].status
=
648 cpu_to_le32((OWNbit
| EORbit
| FSbit
| LSbit
) |
649 ((len
> ETH_ZLEN
) ? len
: ETH_ZLEN
));
651 rtl_flush_tx_desc(&tpc
->TxDescArray
[entry
]);
652 RTL_W8(TxPoll
, 0x40); /* set polling bit */
655 to
= currticks() + TX_TIMEOUT
;
657 rtl_inval_tx_desc(&tpc
->TxDescArray
[entry
]);
658 } while ((le32_to_cpu(tpc
->TxDescArray
[entry
].status
) & OWNbit
)
659 && (currticks() < to
)); /* wait */
661 if (currticks() >= to
) {
662 #ifdef DEBUG_RTL8169_TX
663 puts("tx timeout/error\n");
664 printf("%s elapsed time : %lu\n", __func__
, currticks()-stime
);
668 #ifdef DEBUG_RTL8169_TX
673 /* Delay to make net console (nc) work properly */
679 int rtl8169_eth_send(struct udevice
*dev
, void *packet
, int length
)
681 struct rtl8169_private
*priv
= dev_get_priv(dev
);
683 return rtl_send_common(dev
, priv
->iobase
, packet
, length
);
687 static int rtl_send(struct eth_device
*dev
, void *packet
, int length
)
689 return rtl_send_common((pci_dev_t
)(unsigned long)dev
->priv
,
690 dev
->iobase
, packet
, length
);
694 static void rtl8169_set_rx_mode(void)
696 u32 mc_filter
[2]; /* Multicast hash filter */
701 printf ("%s\n", __FUNCTION__
);
705 /* Too many to filter perfectly -- accept all multicasts. */
706 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
707 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
709 tmp
= rtl8169_rx_config
| rx_mode
| (RTL_R32(RxConfig
) &
710 rtl_chip_info
[tpc
->chipset
].RxConfigMask
);
712 RTL_W32(RxConfig
, tmp
);
713 RTL_W32(MAR0
+ 0, mc_filter
[0]);
714 RTL_W32(MAR0
+ 4, mc_filter
[1]);
718 static void rtl8169_hw_start(struct udevice
*dev
)
720 static void rtl8169_hw_start(pci_dev_t dev
)
726 int stime
= currticks();
727 printf ("%s\n", __FUNCTION__
);
731 /* Soft reset the chip. */
732 RTL_W8(ChipCmd
, CmdReset
);
734 /* Check that the chip has finished the reset. */
735 for (i
= 1000; i
> 0; i
--) {
736 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
743 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
745 /* RTL-8169sb/8110sb or previous version */
746 if (tpc
->chipset
<= 5)
747 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
749 RTL_W8(EarlyTxThres
, EarlyTxThld
);
751 /* For gigabit rtl8169 */
752 RTL_W16(RxMaxSize
, RxPacketMaxSize
);
754 /* Set Rx Config register */
755 i
= rtl8169_rx_config
| (RTL_R32(RxConfig
) &
756 rtl_chip_info
[tpc
->chipset
].RxConfigMask
);
757 RTL_W32(RxConfig
, i
);
759 /* Set DMA burst size and Interframe Gap Time */
760 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
761 (InterFrameGap
<< TxInterFrameGapShift
));
767 RTL_W32(TxDescStartAddrLow
, dm_pci_mem_to_phys(dev
,
768 (pci_addr_t
)(unsigned long)tpc
->TxDescArray
));
770 RTL_W32(TxDescStartAddrLow
, pci_mem_to_phys(dev
,
771 (pci_addr_t
)(unsigned long)tpc
->TxDescArray
));
773 RTL_W32(TxDescStartAddrHigh
, (unsigned long)0);
775 RTL_W32(RxDescStartAddrLow
, dm_pci_mem_to_phys(
776 dev
, (pci_addr_t
)(unsigned long)tpc
->RxDescArray
));
778 RTL_W32(RxDescStartAddrLow
, pci_mem_to_phys(
779 dev
, (pci_addr_t
)(unsigned long)tpc
->RxDescArray
));
781 RTL_W32(RxDescStartAddrHigh
, (unsigned long)0);
783 /* RTL-8169sc/8110sc or later version */
784 if (tpc
->chipset
> 5)
785 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
787 RTL_W8(Cfg9346
, Cfg9346_Lock
);
790 RTL_W32(RxMissed
, 0);
792 rtl8169_set_rx_mode();
794 /* no early-rx interrupts */
795 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
798 printf("%s elapsed time : %lu\n", __func__
, currticks()-stime
);
803 static void rtl8169_init_ring(struct udevice
*dev
)
805 static void rtl8169_init_ring(pci_dev_t dev
)
811 int stime
= currticks();
812 printf ("%s\n", __FUNCTION__
);
818 memset(tpc
->TxDescArray
, 0x0, NUM_TX_DESC
* sizeof(struct TxDesc
));
819 memset(tpc
->RxDescArray
, 0x0, NUM_RX_DESC
* sizeof(struct RxDesc
));
821 for (i
= 0; i
< NUM_TX_DESC
; i
++) {
822 tpc
->Tx_skbuff
[i
] = &txb
[i
];
825 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
826 if (i
== (NUM_RX_DESC
- 1))
827 tpc
->RxDescArray
[i
].status
=
828 cpu_to_le32((OWNbit
| EORbit
) + RX_BUF_SIZE
);
830 tpc
->RxDescArray
[i
].status
=
831 cpu_to_le32(OWNbit
+ RX_BUF_SIZE
);
833 tpc
->RxBufferRing
[i
] = &rxb
[i
* RX_BUF_SIZE
];
835 tpc
->RxDescArray
[i
].buf_addr
= cpu_to_le32(dm_pci_mem_to_phys(
836 dev
, (pci_addr_t
)(unsigned long)tpc
->RxBufferRing
[i
]));
838 tpc
->RxDescArray
[i
].buf_addr
= cpu_to_le32(pci_mem_to_phys(
839 dev
, (pci_addr_t
)(unsigned long)tpc
->RxBufferRing
[i
]));
841 rtl_flush_rx_desc(&tpc
->RxDescArray
[i
]);
845 printf("%s elapsed time : %lu\n", __func__
, currticks()-stime
);
850 static void rtl8169_common_start(struct udevice
*dev
, unsigned char *enetaddr
,
851 unsigned long dev_iobase
)
853 static void rtl8169_common_start(pci_dev_t dev
, unsigned char *enetaddr
,
854 unsigned long dev_iobase
)
860 int stime
= currticks();
861 printf ("%s\n", __FUNCTION__
);
866 rtl8169_init_ring(dev
);
867 rtl8169_hw_start(dev
);
868 /* Construct a perfect filter frame with the mac address as first match
869 * and broadcast for all others */
870 for (i
= 0; i
< 192; i
++)
873 txb
[0] = enetaddr
[0];
874 txb
[1] = enetaddr
[1];
875 txb
[2] = enetaddr
[2];
876 txb
[3] = enetaddr
[3];
877 txb
[4] = enetaddr
[4];
878 txb
[5] = enetaddr
[5];
881 printf("%s elapsed time : %lu\n", __func__
, currticks()-stime
);
886 static int rtl8169_eth_start(struct udevice
*dev
)
888 struct eth_pdata
*plat
= dev_get_platdata(dev
);
889 struct rtl8169_private
*priv
= dev_get_priv(dev
);
891 rtl8169_common_start(dev
, plat
->enetaddr
, priv
->iobase
);
896 /**************************************************************************
897 RESET - Finish setting up the ethernet interface
898 ***************************************************************************/
899 static int rtl_reset(struct eth_device
*dev
, bd_t
*bis
)
901 rtl8169_common_start((pci_dev_t
)(unsigned long)dev
->priv
,
902 dev
->enetaddr
, dev
->iobase
);
906 #endif /* nCONFIG_DM_ETH */
908 static void rtl_halt_common(unsigned long dev_iobase
)
913 printf ("%s\n", __FUNCTION__
);
918 /* Stop the chip's Tx and Rx DMA processes. */
919 RTL_W8(ChipCmd
, 0x00);
921 /* Disable interrupts by clearing the interrupt mask. */
922 RTL_W16(IntrMask
, 0x0000);
924 RTL_W32(RxMissed
, 0);
926 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
927 tpc
->RxBufferRing
[i
] = NULL
;
932 void rtl8169_eth_stop(struct udevice
*dev
)
934 struct rtl8169_private
*priv
= dev_get_priv(dev
);
936 rtl_halt_common(priv
->iobase
);
939 /**************************************************************************
940 HALT - Turn off ethernet interface
941 ***************************************************************************/
942 static void rtl_halt(struct eth_device
*dev
)
944 rtl_halt_common(dev
->iobase
);
949 static int rtl8169_write_hwaddr(struct udevice
*dev
)
951 struct eth_pdata
*plat
= dev_get_platdata(dev
);
954 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
956 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
957 RTL_W8(MAC0
+ i
, plat
->enetaddr
[i
]);
959 RTL_W8(Cfg9346
, Cfg9346_Lock
);
965 /**************************************************************************
966 INIT - Look for an adapter, this routine's visible to the outside
967 ***************************************************************************/
969 #define board_found 1
971 static int rtl_init(unsigned long dev_ioaddr
, const char *name
,
972 unsigned char *enetaddr
)
974 static int board_idx
= -1;
976 int option
= -1, Cap10_100
= 0, Cap1000
= 0;
979 printf ("%s\n", __FUNCTION__
);
985 /* point to private storage */
988 rc
= rtl8169_init_board(ioaddr
, name
);
992 /* Get MAC address. FIXME: read EEPROM */
993 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
994 enetaddr
[i
] = RTL_R8(MAC0
+ i
);
997 printf("chipset = %d\n", tpc
->chipset
);
998 printf("MAC Address");
999 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
1000 printf(":%02x", enetaddr
[i
]);
1004 #ifdef DEBUG_RTL8169
1005 /* Print out some hardware info */
1006 printf("%s: at ioaddr 0x%lx\n", name
, ioaddr
);
1009 /* if TBI is not endbled */
1010 if (!(RTL_R8(PHYstatus
) & TBI_Enable
)) {
1011 int val
= mdio_read(PHY_AUTO_NEGO_REG
);
1013 option
= (board_idx
>= MAX_UNITS
) ? 0 : media
[board_idx
];
1014 /* Force RTL8169 in 10/100/1000 Full/Half mode. */
1016 #ifdef DEBUG_RTL8169
1017 printf("%s: Force-mode Enabled.\n", name
);
1019 Cap10_100
= 0, Cap1000
= 0;
1022 Cap10_100
= PHY_Cap_10_Half
;
1023 Cap1000
= PHY_Cap_Null
;
1026 Cap10_100
= PHY_Cap_10_Full
;
1027 Cap1000
= PHY_Cap_Null
;
1030 Cap10_100
= PHY_Cap_100_Half
;
1031 Cap1000
= PHY_Cap_Null
;
1034 Cap10_100
= PHY_Cap_100_Full
;
1035 Cap1000
= PHY_Cap_Null
;
1038 Cap10_100
= PHY_Cap_Null
;
1039 Cap1000
= PHY_Cap_1000_Full
;
1044 mdio_write(PHY_AUTO_NEGO_REG
, Cap10_100
| (val
& 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
1045 mdio_write(PHY_1000_CTRL_REG
, Cap1000
);
1047 #ifdef DEBUG_RTL8169
1048 printf("%s: Auto-negotiation Enabled.\n",
1051 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
1052 mdio_write(PHY_AUTO_NEGO_REG
,
1053 PHY_Cap_10_Half
| PHY_Cap_10_Full
|
1054 PHY_Cap_100_Half
| PHY_Cap_100_Full
|
1057 /* enable 1000 Full Mode */
1058 mdio_write(PHY_1000_CTRL_REG
, PHY_Cap_1000_Full
);
1062 /* Enable auto-negotiation and restart auto-nigotiation */
1063 mdio_write(PHY_CTRL_REG
,
1064 PHY_Enable_Auto_Nego
| PHY_Restart_Auto_Nego
);
1067 /* wait for auto-negotiation process */
1068 for (i
= 10000; i
> 0; i
--) {
1069 /* check if auto-negotiation complete */
1070 if (mdio_read(PHY_STAT_REG
) & PHY_Auto_Nego_Comp
) {
1072 option
= RTL_R8(PHYstatus
);
1073 if (option
& _1000bpsF
) {
1074 #ifdef DEBUG_RTL8169
1075 printf("%s: 1000Mbps Full-duplex operation.\n",
1079 #ifdef DEBUG_RTL8169
1080 printf("%s: %sMbps %s-duplex operation.\n",
1082 (option
& _100bps
) ? "100" :
1084 (option
& FullDup
) ? "Full" :
1092 } /* end for-loop to wait for auto-negotiation process */
1096 #ifdef DEBUG_RTL8169
1098 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
1100 (RTL_R32(TBICSR
) & TBILinkOK
) ? "OK" : "Failed");
1105 tpc
->RxDescArray
= rtl_alloc_descs(NUM_RX_DESC
);
1106 if (!tpc
->RxDescArray
)
1109 tpc
->TxDescArray
= rtl_alloc_descs(NUM_TX_DESC
);
1110 if (!tpc
->TxDescArray
)
1116 #ifndef CONFIG_DM_ETH
1117 int rtl8169_initialize(bd_t
*bis
)
1120 int card_number
= 0;
1121 struct eth_device
*dev
;
1126 unsigned int region
;
1131 if ((devno
= pci_find_devices(supported
, idx
++)) < 0)
1134 pci_read_config_word(devno
, PCI_DEVICE_ID
, &device
);
1145 pci_read_config_dword(devno
, PCI_BASE_ADDRESS_0
+ (region
* 4), &iobase
);
1148 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase
);
1150 dev
= (struct eth_device
*)malloc(sizeof *dev
);
1152 printf("Can not allocate memory of rtl8169\n");
1156 memset(dev
, 0, sizeof(*dev
));
1157 sprintf (dev
->name
, "RTL8169#%d", card_number
);
1159 dev
->priv
= (void *)(unsigned long)devno
;
1160 dev
->iobase
= (int)pci_mem_to_phys(devno
, iobase
);
1162 dev
->init
= rtl_reset
;
1163 dev
->halt
= rtl_halt
;
1164 dev
->send
= rtl_send
;
1165 dev
->recv
= rtl_recv
;
1167 err
= rtl_init(dev
->iobase
, dev
->name
, dev
->enetaddr
);
1169 printf(pr_fmt("failed to initialize card: %d\n"), err
);
1182 #ifdef CONFIG_DM_ETH
1183 static int rtl8169_eth_probe(struct udevice
*dev
)
1185 struct pci_child_platdata
*pplat
= dev_get_parent_platdata(dev
);
1186 struct rtl8169_private
*priv
= dev_get_priv(dev
);
1187 struct eth_pdata
*plat
= dev_get_platdata(dev
);
1192 debug("rtl8169: REALTEK RTL8169 @0x%x\n", iobase
);
1193 switch (pplat
->device
) {
1201 dm_pci_read_config32(dev
, PCI_BASE_ADDRESS_0
+ region
* 4, &iobase
);
1203 priv
->iobase
= (int)dm_pci_mem_to_phys(dev
, iobase
);
1205 ret
= rtl_init(priv
->iobase
, dev
->name
, plat
->enetaddr
);
1207 printf(pr_fmt("failed to initialize card: %d\n"), ret
);
1214 static const struct eth_ops rtl8169_eth_ops
= {
1215 .start
= rtl8169_eth_start
,
1216 .send
= rtl8169_eth_send
,
1217 .recv
= rtl8169_eth_recv
,
1218 .stop
= rtl8169_eth_stop
,
1219 .write_hwaddr
= rtl8169_write_hwaddr
,
1222 static const struct udevice_id rtl8169_eth_ids
[] = {
1223 { .compatible
= "realtek,rtl8169" },
1227 U_BOOT_DRIVER(eth_rtl8169
) = {
1228 .name
= "eth_rtl8169",
1230 .of_match
= rtl8169_eth_ids
,
1231 .probe
= rtl8169_eth_probe
,
1232 .ops
= &rtl8169_eth_ops
,
1233 .priv_auto_alloc_size
= sizeof(struct rtl8169_private
),
1234 .platdata_auto_alloc_size
= sizeof(struct eth_pdata
),
1237 U_BOOT_PCI_DEVICE(eth_rtl8169
, supported
);