2 * sh_eth.c - Driver for Renesas ethernet controler.
4 * Copyright (C) 2008, 2011 Renesas Solutions Corp.
5 * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
7 * Copyright (C) 2013 Renesas Electronics Corporation
9 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/errno.h>
23 #ifndef CONFIG_SH_ETHER_USE_PORT
24 # error "Please define CONFIG_SH_ETHER_USE_PORT"
26 #ifndef CONFIG_SH_ETHER_PHY_ADDR
27 # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
30 #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF)
31 #define flush_cache_wback(addr, len) \
32 flush_dcache_range((u32)addr, (u32)(addr + len - 1))
34 #define flush_cache_wback(...)
37 #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
38 #define invalidate_cache(addr, len) \
40 u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \
45 start &= ~(line_size - 1); \
46 end = ((end + line_size - 1) & ~(line_size - 1)); \
48 invalidate_dcache_range(start, end); \
51 #define invalidate_cache(...)
54 #define TIMEOUT_CNT 1000
56 int sh_eth_send(struct eth_device
*dev
, void *packet
, int len
)
58 struct sh_eth_dev
*eth
= dev
->priv
;
59 int port
= eth
->port
, ret
= 0, timeout
;
60 struct sh_eth_info
*port_info
= ð
->port_info
[port
];
62 if (!packet
|| len
> 0xffff) {
63 printf(SHETHER_NAME
": %s: Invalid argument\n", __func__
);
68 /* packet must be a 4 byte boundary */
69 if ((int)packet
& 3) {
70 printf(SHETHER_NAME
": %s: packet not 4 byte alligned\n", __func__
);
75 /* Update tx descriptor */
76 flush_cache_wback(packet
, len
);
77 port_info
->tx_desc_cur
->td2
= ADDR_TO_PHY(packet
);
78 port_info
->tx_desc_cur
->td1
= len
<< 16;
79 /* Must preserve the end of descriptor list indication */
80 if (port_info
->tx_desc_cur
->td0
& TD_TDLE
)
81 port_info
->tx_desc_cur
->td0
= TD_TACT
| TD_TFP
| TD_TDLE
;
83 port_info
->tx_desc_cur
->td0
= TD_TACT
| TD_TFP
;
85 /* Restart the transmitter if disabled */
86 if (!(sh_eth_read(eth
, EDTRR
) & EDTRR_TRNS
))
87 sh_eth_write(eth
, EDTRR_TRNS
, EDTRR
);
89 /* Wait until packet is transmitted */
90 timeout
= TIMEOUT_CNT
;
92 invalidate_cache(port_info
->tx_desc_cur
,
93 sizeof(struct tx_desc_s
));
95 } while (port_info
->tx_desc_cur
->td0
& TD_TACT
&& timeout
--);
98 printf(SHETHER_NAME
": transmit timeout\n");
103 port_info
->tx_desc_cur
++;
104 if (port_info
->tx_desc_cur
>= port_info
->tx_desc_base
+ NUM_TX_DESC
)
105 port_info
->tx_desc_cur
= port_info
->tx_desc_base
;
111 int sh_eth_recv(struct eth_device
*dev
)
113 struct sh_eth_dev
*eth
= dev
->priv
;
114 int port
= eth
->port
, len
= 0;
115 struct sh_eth_info
*port_info
= ð
->port_info
[port
];
118 /* Check if the rx descriptor is ready */
119 invalidate_cache(port_info
->rx_desc_cur
, sizeof(struct rx_desc_s
));
120 if (!(port_info
->rx_desc_cur
->rd0
& RD_RACT
)) {
121 /* Check for errors */
122 if (!(port_info
->rx_desc_cur
->rd0
& RD_RFE
)) {
123 len
= port_info
->rx_desc_cur
->rd1
& 0xffff;
125 ADDR_TO_P2(port_info
->rx_desc_cur
->rd2
);
126 invalidate_cache(packet
, len
);
127 NetReceive(packet
, len
);
130 /* Make current descriptor available again */
131 if (port_info
->rx_desc_cur
->rd0
& RD_RDLE
)
132 port_info
->rx_desc_cur
->rd0
= RD_RACT
| RD_RDLE
;
134 port_info
->rx_desc_cur
->rd0
= RD_RACT
;
135 /* Point to the next descriptor */
136 port_info
->rx_desc_cur
++;
137 if (port_info
->rx_desc_cur
>=
138 port_info
->rx_desc_base
+ NUM_RX_DESC
)
139 port_info
->rx_desc_cur
= port_info
->rx_desc_base
;
142 /* Restart the receiver if disabled */
143 if (!(sh_eth_read(eth
, EDRRR
) & EDRRR_R
))
144 sh_eth_write(eth
, EDRRR_R
, EDRRR
);
149 static int sh_eth_reset(struct sh_eth_dev
*eth
)
151 #if defined(SH_ETH_TYPE_GETHER)
154 /* Start e-dmac transmitter and receiver */
155 sh_eth_write(eth
, EDSR_ENALL
, EDSR
);
157 /* Perform a software reset and wait for it to complete */
158 sh_eth_write(eth
, EDMR_SRST
, EDMR
);
159 for (i
= 0; i
< TIMEOUT_CNT
; i
++) {
160 if (!(sh_eth_read(eth
, EDMR
) & EDMR_SRST
))
165 if (i
== TIMEOUT_CNT
) {
166 printf(SHETHER_NAME
": Software reset timeout\n");
172 sh_eth_write(eth
, sh_eth_read(eth
, EDMR
) | EDMR_SRST
, EDMR
);
174 sh_eth_write(eth
, sh_eth_read(eth
, EDMR
) & ~EDMR_SRST
, EDMR
);
180 static int sh_eth_tx_desc_init(struct sh_eth_dev
*eth
)
182 int port
= eth
->port
, i
, ret
= 0;
184 struct sh_eth_info
*port_info
= ð
->port_info
[port
];
185 struct tx_desc_s
*cur_tx_desc
;
188 * Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned
190 port_info
->tx_desc_malloc
= malloc(NUM_TX_DESC
*
191 sizeof(struct tx_desc_s
) +
193 if (!port_info
->tx_desc_malloc
) {
194 printf(SHETHER_NAME
": malloc failed\n");
199 tmp_addr
= (u32
) (((int)port_info
->tx_desc_malloc
+ TX_DESC_SIZE
- 1) &
200 ~(TX_DESC_SIZE
- 1));
201 flush_cache_wback(tmp_addr
, NUM_TX_DESC
* sizeof(struct tx_desc_s
));
202 /* Make sure we use a P2 address (non-cacheable) */
203 port_info
->tx_desc_base
= (struct tx_desc_s
*)ADDR_TO_P2(tmp_addr
);
204 port_info
->tx_desc_cur
= port_info
->tx_desc_base
;
206 /* Initialize all descriptors */
207 for (cur_tx_desc
= port_info
->tx_desc_base
, i
= 0; i
< NUM_TX_DESC
;
208 cur_tx_desc
++, i
++) {
209 cur_tx_desc
->td0
= 0x00;
210 cur_tx_desc
->td1
= 0x00;
211 cur_tx_desc
->td2
= 0x00;
214 /* Mark the end of the descriptors */
216 cur_tx_desc
->td0
|= TD_TDLE
;
218 /* Point the controller to the tx descriptor list. Must use physical
220 sh_eth_write(eth
, ADDR_TO_PHY(port_info
->tx_desc_base
), TDLAR
);
221 #if defined(SH_ETH_TYPE_GETHER)
222 sh_eth_write(eth
, ADDR_TO_PHY(port_info
->tx_desc_base
), TDFAR
);
223 sh_eth_write(eth
, ADDR_TO_PHY(cur_tx_desc
), TDFXR
);
224 sh_eth_write(eth
, 0x01, TDFFR
);/* Last discriptor bit */
231 static int sh_eth_rx_desc_init(struct sh_eth_dev
*eth
)
233 int port
= eth
->port
, i
, ret
= 0;
234 struct sh_eth_info
*port_info
= ð
->port_info
[port
];
235 struct rx_desc_s
*cur_rx_desc
;
240 * Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned
242 port_info
->rx_desc_malloc
= malloc(NUM_RX_DESC
*
243 sizeof(struct rx_desc_s
) +
245 if (!port_info
->rx_desc_malloc
) {
246 printf(SHETHER_NAME
": malloc failed\n");
251 tmp_addr
= (u32
) (((int)port_info
->rx_desc_malloc
+ RX_DESC_SIZE
- 1) &
252 ~(RX_DESC_SIZE
- 1));
253 flush_cache_wback(tmp_addr
, NUM_RX_DESC
* sizeof(struct rx_desc_s
));
254 /* Make sure we use a P2 address (non-cacheable) */
255 port_info
->rx_desc_base
= (struct rx_desc_s
*)ADDR_TO_P2(tmp_addr
);
257 port_info
->rx_desc_cur
= port_info
->rx_desc_base
;
260 * Allocate rx data buffers. They must be 32 bytes aligned and in
263 port_info
->rx_buf_malloc
= malloc(
264 NUM_RX_DESC
* MAX_BUF_SIZE
+ RX_BUF_ALIGNE_SIZE
- 1);
265 if (!port_info
->rx_buf_malloc
) {
266 printf(SHETHER_NAME
": malloc failed\n");
271 tmp_addr
= (u32
)(((int)port_info
->rx_buf_malloc
272 + (RX_BUF_ALIGNE_SIZE
- 1)) &
273 ~(RX_BUF_ALIGNE_SIZE
- 1));
274 port_info
->rx_buf_base
= (u8
*)ADDR_TO_P2(tmp_addr
);
276 /* Initialize all descriptors */
277 for (cur_rx_desc
= port_info
->rx_desc_base
,
278 rx_buf
= port_info
->rx_buf_base
, i
= 0;
279 i
< NUM_RX_DESC
; cur_rx_desc
++, rx_buf
+= MAX_BUF_SIZE
, i
++) {
280 cur_rx_desc
->rd0
= RD_RACT
;
281 cur_rx_desc
->rd1
= MAX_BUF_SIZE
<< 16;
282 cur_rx_desc
->rd2
= (u32
) ADDR_TO_PHY(rx_buf
);
285 /* Mark the end of the descriptors */
287 cur_rx_desc
->rd0
|= RD_RDLE
;
289 /* Point the controller to the rx descriptor list */
290 sh_eth_write(eth
, ADDR_TO_PHY(port_info
->rx_desc_base
), RDLAR
);
291 #if defined(SH_ETH_TYPE_GETHER)
292 sh_eth_write(eth
, ADDR_TO_PHY(port_info
->rx_desc_base
), RDFAR
);
293 sh_eth_write(eth
, ADDR_TO_PHY(cur_rx_desc
), RDFXR
);
294 sh_eth_write(eth
, RDFFR_RDLF
, RDFFR
);
300 free(port_info
->rx_desc_malloc
);
301 port_info
->rx_desc_malloc
= NULL
;
307 static void sh_eth_tx_desc_free(struct sh_eth_dev
*eth
)
309 int port
= eth
->port
;
310 struct sh_eth_info
*port_info
= ð
->port_info
[port
];
312 if (port_info
->tx_desc_malloc
) {
313 free(port_info
->tx_desc_malloc
);
314 port_info
->tx_desc_malloc
= NULL
;
318 static void sh_eth_rx_desc_free(struct sh_eth_dev
*eth
)
320 int port
= eth
->port
;
321 struct sh_eth_info
*port_info
= ð
->port_info
[port
];
323 if (port_info
->rx_desc_malloc
) {
324 free(port_info
->rx_desc_malloc
);
325 port_info
->rx_desc_malloc
= NULL
;
328 if (port_info
->rx_buf_malloc
) {
329 free(port_info
->rx_buf_malloc
);
330 port_info
->rx_buf_malloc
= NULL
;
334 static int sh_eth_desc_init(struct sh_eth_dev
*eth
)
338 ret
= sh_eth_tx_desc_init(eth
);
342 ret
= sh_eth_rx_desc_init(eth
);
348 sh_eth_tx_desc_free(eth
);
354 static int sh_eth_phy_config(struct sh_eth_dev
*eth
)
356 int port
= eth
->port
, ret
= 0;
357 struct sh_eth_info
*port_info
= ð
->port_info
[port
];
358 struct eth_device
*dev
= port_info
->dev
;
359 struct phy_device
*phydev
;
361 phydev
= phy_connect(
362 miiphy_get_dev_by_name(dev
->name
),
363 port_info
->phy_addr
, dev
, CONFIG_SH_ETHER_PHY_MODE
);
364 port_info
->phydev
= phydev
;
370 static int sh_eth_config(struct sh_eth_dev
*eth
, bd_t
*bd
)
372 int port
= eth
->port
, ret
= 0;
374 struct sh_eth_info
*port_info
= ð
->port_info
[port
];
375 struct eth_device
*dev
= port_info
->dev
;
376 struct phy_device
*phy
;
378 /* Configure e-dmac registers */
379 sh_eth_write(eth
, (sh_eth_read(eth
, EDMR
) & ~EMDR_DESC_R
) |
380 (EMDR_DESC
| EDMR_EL
), EDMR
);
382 sh_eth_write(eth
, 0, EESIPR
);
383 sh_eth_write(eth
, 0, TRSCER
);
384 sh_eth_write(eth
, 0, TFTR
);
385 sh_eth_write(eth
, (FIFO_SIZE_T
| FIFO_SIZE_R
), FDR
);
386 sh_eth_write(eth
, RMCR_RST
, RMCR
);
387 #if defined(SH_ETH_TYPE_GETHER)
388 sh_eth_write(eth
, 0, RPADIR
);
390 sh_eth_write(eth
, (FIFO_F_D_RFF
| FIFO_F_D_RFD
), FCFTR
);
392 /* Configure e-mac registers */
393 sh_eth_write(eth
, 0, ECSIPR
);
395 /* Set Mac address */
396 val
= dev
->enetaddr
[0] << 24 | dev
->enetaddr
[1] << 16 |
397 dev
->enetaddr
[2] << 8 | dev
->enetaddr
[3];
398 sh_eth_write(eth
, val
, MAHR
);
400 val
= dev
->enetaddr
[4] << 8 | dev
->enetaddr
[5];
401 sh_eth_write(eth
, val
, MALR
);
403 sh_eth_write(eth
, RFLR_RFL_MIN
, RFLR
);
404 #if defined(SH_ETH_TYPE_GETHER)
405 sh_eth_write(eth
, 0, PIPR
);
406 sh_eth_write(eth
, APR_AP
, APR
);
407 sh_eth_write(eth
, MPR_MP
, MPR
);
408 sh_eth_write(eth
, TPAUSER_TPAUSE
, TPAUSER
);
411 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
412 sh_eth_write(eth
, CONFIG_SH_ETHER_SH7734_MII
, RMII_MII
);
413 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
414 sh_eth_write(eth
, sh_eth_read(eth
, RMIIMR
) | 0x1, RMIIMR
);
417 ret
= sh_eth_phy_config(eth
);
419 printf(SHETHER_NAME
": phy config timeout\n");
422 phy
= port_info
->phydev
;
423 ret
= phy_startup(phy
);
425 printf(SHETHER_NAME
": phy startup failure\n");
431 /* Set the transfer speed */
432 if (phy
->speed
== 100) {
433 printf(SHETHER_NAME
": 100Base/");
434 #if defined(SH_ETH_TYPE_GETHER)
435 sh_eth_write(eth
, GECMR_100B
, GECMR
);
436 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
437 sh_eth_write(eth
, 1, RTRATE
);
438 #elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \
439 defined(CONFIG_R8A7791)
442 } else if (phy
->speed
== 10) {
443 printf(SHETHER_NAME
": 10Base/");
444 #if defined(SH_ETH_TYPE_GETHER)
445 sh_eth_write(eth
, GECMR_10B
, GECMR
);
446 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
447 sh_eth_write(eth
, 0, RTRATE
);
450 #if defined(SH_ETH_TYPE_GETHER)
451 else if (phy
->speed
== 1000) {
452 printf(SHETHER_NAME
": 1000Base/");
453 sh_eth_write(eth
, GECMR_1000B
, GECMR
);
457 /* Check if full duplex mode is supported by the phy */
460 sh_eth_write(eth
, val
| (ECMR_CHG_DM
|ECMR_RE
|ECMR_TE
|ECMR_DM
),
464 sh_eth_write(eth
, val
| (ECMR_CHG_DM
|ECMR_RE
|ECMR_TE
), ECMR
);
473 static void sh_eth_start(struct sh_eth_dev
*eth
)
476 * Enable the e-dmac receiver only. The transmitter will be enabled when
477 * we have something to transmit
479 sh_eth_write(eth
, EDRRR_R
, EDRRR
);
482 static void sh_eth_stop(struct sh_eth_dev
*eth
)
484 sh_eth_write(eth
, ~EDRRR_R
, EDRRR
);
487 int sh_eth_init(struct eth_device
*dev
, bd_t
*bd
)
490 struct sh_eth_dev
*eth
= dev
->priv
;
492 ret
= sh_eth_reset(eth
);
496 ret
= sh_eth_desc_init(eth
);
500 ret
= sh_eth_config(eth
, bd
);
509 sh_eth_tx_desc_free(eth
);
510 sh_eth_rx_desc_free(eth
);
516 void sh_eth_halt(struct eth_device
*dev
)
518 struct sh_eth_dev
*eth
= dev
->priv
;
522 int sh_eth_initialize(bd_t
*bd
)
525 struct sh_eth_dev
*eth
= NULL
;
526 struct eth_device
*dev
= NULL
;
528 eth
= (struct sh_eth_dev
*)malloc(sizeof(struct sh_eth_dev
));
530 printf(SHETHER_NAME
": %s: malloc failed\n", __func__
);
535 dev
= (struct eth_device
*)malloc(sizeof(struct eth_device
));
537 printf(SHETHER_NAME
": %s: malloc failed\n", __func__
);
541 memset(dev
, 0, sizeof(struct eth_device
));
542 memset(eth
, 0, sizeof(struct sh_eth_dev
));
544 eth
->port
= CONFIG_SH_ETHER_USE_PORT
;
545 eth
->port_info
[eth
->port
].phy_addr
= CONFIG_SH_ETHER_PHY_ADDR
;
547 dev
->priv
= (void *)eth
;
549 dev
->init
= sh_eth_init
;
550 dev
->halt
= sh_eth_halt
;
551 dev
->send
= sh_eth_send
;
552 dev
->recv
= sh_eth_recv
;
553 eth
->port_info
[eth
->port
].dev
= dev
;
555 sprintf(dev
->name
, SHETHER_NAME
);
557 /* Register Device to EtherNet subsystem */
560 bb_miiphy_buses
[0].priv
= eth
;
561 miiphy_register(dev
->name
, bb_miiphy_read
, bb_miiphy_write
);
563 if (!eth_getenv_enetaddr("ethaddr", dev
->enetaddr
))
564 puts("Please set MAC address\n");
575 printf(SHETHER_NAME
": Failed\n");
579 /******* for bb_miiphy *******/
580 static int sh_eth_bb_init(struct bb_miiphy_bus
*bus
)
585 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus
*bus
)
587 struct sh_eth_dev
*eth
= bus
->priv
;
589 sh_eth_write(eth
, sh_eth_read(eth
, PIR
) | PIR_MMD
, PIR
);
594 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus
*bus
)
596 struct sh_eth_dev
*eth
= bus
->priv
;
598 sh_eth_write(eth
, sh_eth_read(eth
, PIR
) & ~PIR_MMD
, PIR
);
603 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus
*bus
, int v
)
605 struct sh_eth_dev
*eth
= bus
->priv
;
608 sh_eth_write(eth
, sh_eth_read(eth
, PIR
) | PIR_MDO
, PIR
);
610 sh_eth_write(eth
, sh_eth_read(eth
, PIR
) & ~PIR_MDO
, PIR
);
615 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus
*bus
, int *v
)
617 struct sh_eth_dev
*eth
= bus
->priv
;
619 *v
= (sh_eth_read(eth
, PIR
) & PIR_MDI
) >> 3;
624 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus
*bus
, int v
)
626 struct sh_eth_dev
*eth
= bus
->priv
;
629 sh_eth_write(eth
, sh_eth_read(eth
, PIR
) | PIR_MDC
, PIR
);
631 sh_eth_write(eth
, sh_eth_read(eth
, PIR
) & ~PIR_MDC
, PIR
);
636 static int sh_eth_bb_delay(struct bb_miiphy_bus
*bus
)
643 struct bb_miiphy_bus bb_miiphy_buses
[] = {
646 .init
= sh_eth_bb_init
,
647 .mdio_active
= sh_eth_bb_mdio_active
,
648 .mdio_tristate
= sh_eth_bb_mdio_tristate
,
649 .set_mdio
= sh_eth_bb_set_mdio
,
650 .get_mdio
= sh_eth_bb_get_mdio
,
651 .set_mdc
= sh_eth_bb_set_mdc
,
652 .delay
= sh_eth_bb_delay
,
655 int bb_miiphy_buses_num
= ARRAY_SIZE(bb_miiphy_buses
);