2 * sh_eth.c - Driver for Renesas ethernet controller.
4 * Copyright (C) 2008, 2011 Renesas Solutions Corp.
5 * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
7 * Copyright (C) 2013, 2014 Renesas Electronics Corporation
9 * SPDX-License-Identifier: GPL-2.0+
18 #include <linux/errno.h>
23 #ifndef CONFIG_SH_ETHER_USE_PORT
24 # error "Please define CONFIG_SH_ETHER_USE_PORT"
26 #ifndef CONFIG_SH_ETHER_PHY_ADDR
27 # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
30 #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF)
31 #define flush_cache_wback(addr, len) \
32 flush_dcache_range((u32)addr, (u32)(addr + len - 1))
34 #define flush_cache_wback(...)
37 #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
38 #define invalidate_cache(addr, len) \
40 u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \
45 start &= ~(line_size - 1); \
46 end = ((end + line_size - 1) & ~(line_size - 1)); \
48 invalidate_dcache_range(start, end); \
51 #define invalidate_cache(...)
54 #define TIMEOUT_CNT 1000
56 int sh_eth_send(struct eth_device
*dev
, void *packet
, int len
)
58 struct sh_eth_dev
*eth
= dev
->priv
;
59 int port
= eth
->port
, ret
= 0, timeout
;
60 struct sh_eth_info
*port_info
= ð
->port_info
[port
];
62 if (!packet
|| len
> 0xffff) {
63 printf(SHETHER_NAME
": %s: Invalid argument\n", __func__
);
68 /* packet must be a 4 byte boundary */
69 if ((int)packet
& 3) {
70 printf(SHETHER_NAME
": %s: packet not 4 byte alligned\n"
76 /* Update tx descriptor */
77 flush_cache_wback(packet
, len
);
78 port_info
->tx_desc_cur
->td2
= ADDR_TO_PHY(packet
);
79 port_info
->tx_desc_cur
->td1
= len
<< 16;
80 /* Must preserve the end of descriptor list indication */
81 if (port_info
->tx_desc_cur
->td0
& TD_TDLE
)
82 port_info
->tx_desc_cur
->td0
= TD_TACT
| TD_TFP
| TD_TDLE
;
84 port_info
->tx_desc_cur
->td0
= TD_TACT
| TD_TFP
;
86 flush_cache_wback(port_info
->tx_desc_cur
, sizeof(struct tx_desc_s
));
88 /* Restart the transmitter if disabled */
89 if (!(sh_eth_read(eth
, EDTRR
) & EDTRR_TRNS
))
90 sh_eth_write(eth
, EDTRR_TRNS
, EDTRR
);
92 /* Wait until packet is transmitted */
93 timeout
= TIMEOUT_CNT
;
95 invalidate_cache(port_info
->tx_desc_cur
,
96 sizeof(struct tx_desc_s
));
98 } while (port_info
->tx_desc_cur
->td0
& TD_TACT
&& timeout
--);
101 printf(SHETHER_NAME
": transmit timeout\n");
106 port_info
->tx_desc_cur
++;
107 if (port_info
->tx_desc_cur
>= port_info
->tx_desc_base
+ NUM_TX_DESC
)
108 port_info
->tx_desc_cur
= port_info
->tx_desc_base
;
114 int sh_eth_recv(struct eth_device
*dev
)
116 struct sh_eth_dev
*eth
= dev
->priv
;
117 int port
= eth
->port
, len
= 0;
118 struct sh_eth_info
*port_info
= ð
->port_info
[port
];
121 /* Check if the rx descriptor is ready */
122 invalidate_cache(port_info
->rx_desc_cur
, sizeof(struct rx_desc_s
));
123 if (!(port_info
->rx_desc_cur
->rd0
& RD_RACT
)) {
124 /* Check for errors */
125 if (!(port_info
->rx_desc_cur
->rd0
& RD_RFE
)) {
126 len
= port_info
->rx_desc_cur
->rd1
& 0xffff;
128 ADDR_TO_P2(port_info
->rx_desc_cur
->rd2
);
129 invalidate_cache(packet
, len
);
130 net_process_received_packet(packet
, len
);
133 /* Make current descriptor available again */
134 if (port_info
->rx_desc_cur
->rd0
& RD_RDLE
)
135 port_info
->rx_desc_cur
->rd0
= RD_RACT
| RD_RDLE
;
137 port_info
->rx_desc_cur
->rd0
= RD_RACT
;
139 flush_cache_wback(port_info
->rx_desc_cur
,
140 sizeof(struct rx_desc_s
));
142 /* Point to the next descriptor */
143 port_info
->rx_desc_cur
++;
144 if (port_info
->rx_desc_cur
>=
145 port_info
->rx_desc_base
+ NUM_RX_DESC
)
146 port_info
->rx_desc_cur
= port_info
->rx_desc_base
;
149 /* Restart the receiver if disabled */
150 if (!(sh_eth_read(eth
, EDRRR
) & EDRRR_R
))
151 sh_eth_write(eth
, EDRRR_R
, EDRRR
);
156 static int sh_eth_reset(struct sh_eth_dev
*eth
)
158 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
161 /* Start e-dmac transmitter and receiver */
162 sh_eth_write(eth
, EDSR_ENALL
, EDSR
);
164 /* Perform a software reset and wait for it to complete */
165 sh_eth_write(eth
, EDMR_SRST
, EDMR
);
166 for (i
= 0; i
< TIMEOUT_CNT
; i
++) {
167 if (!(sh_eth_read(eth
, EDMR
) & EDMR_SRST
))
172 if (i
== TIMEOUT_CNT
) {
173 printf(SHETHER_NAME
": Software reset timeout\n");
179 sh_eth_write(eth
, sh_eth_read(eth
, EDMR
) | EDMR_SRST
, EDMR
);
181 sh_eth_write(eth
, sh_eth_read(eth
, EDMR
) & ~EDMR_SRST
, EDMR
);
187 static int sh_eth_tx_desc_init(struct sh_eth_dev
*eth
)
189 int port
= eth
->port
, i
, ret
= 0;
190 u32 alloc_desc_size
= NUM_TX_DESC
* sizeof(struct tx_desc_s
);
191 struct sh_eth_info
*port_info
= ð
->port_info
[port
];
192 struct tx_desc_s
*cur_tx_desc
;
195 * Allocate rx descriptors. They must be aligned to size of struct
198 port_info
->tx_desc_alloc
=
199 memalign(sizeof(struct tx_desc_s
), alloc_desc_size
);
200 if (!port_info
->tx_desc_alloc
) {
201 printf(SHETHER_NAME
": memalign failed\n");
206 flush_cache_wback((u32
)port_info
->tx_desc_alloc
, alloc_desc_size
);
208 /* Make sure we use a P2 address (non-cacheable) */
209 port_info
->tx_desc_base
=
210 (struct tx_desc_s
*)ADDR_TO_P2((u32
)port_info
->tx_desc_alloc
);
211 port_info
->tx_desc_cur
= port_info
->tx_desc_base
;
213 /* Initialize all descriptors */
214 for (cur_tx_desc
= port_info
->tx_desc_base
, i
= 0; i
< NUM_TX_DESC
;
215 cur_tx_desc
++, i
++) {
216 cur_tx_desc
->td0
= 0x00;
217 cur_tx_desc
->td1
= 0x00;
218 cur_tx_desc
->td2
= 0x00;
221 /* Mark the end of the descriptors */
223 cur_tx_desc
->td0
|= TD_TDLE
;
225 /* Point the controller to the tx descriptor list. Must use physical
227 sh_eth_write(eth
, ADDR_TO_PHY(port_info
->tx_desc_base
), TDLAR
);
228 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
229 sh_eth_write(eth
, ADDR_TO_PHY(port_info
->tx_desc_base
), TDFAR
);
230 sh_eth_write(eth
, ADDR_TO_PHY(cur_tx_desc
), TDFXR
);
231 sh_eth_write(eth
, 0x01, TDFFR
);/* Last discriptor bit */
238 static int sh_eth_rx_desc_init(struct sh_eth_dev
*eth
)
240 int port
= eth
->port
, i
, ret
= 0;
241 u32 alloc_desc_size
= NUM_RX_DESC
* sizeof(struct rx_desc_s
);
242 struct sh_eth_info
*port_info
= ð
->port_info
[port
];
243 struct rx_desc_s
*cur_rx_desc
;
247 * Allocate rx descriptors. They must be aligned to size of struct
250 port_info
->rx_desc_alloc
=
251 memalign(sizeof(struct rx_desc_s
), alloc_desc_size
);
252 if (!port_info
->rx_desc_alloc
) {
253 printf(SHETHER_NAME
": memalign failed\n");
258 flush_cache_wback(port_info
->rx_desc_alloc
, alloc_desc_size
);
260 /* Make sure we use a P2 address (non-cacheable) */
261 port_info
->rx_desc_base
=
262 (struct rx_desc_s
*)ADDR_TO_P2((u32
)port_info
->rx_desc_alloc
);
264 port_info
->rx_desc_cur
= port_info
->rx_desc_base
;
267 * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
268 * aligned and in P2 area.
270 port_info
->rx_buf_alloc
=
271 memalign(RX_BUF_ALIGNE_SIZE
, NUM_RX_DESC
* MAX_BUF_SIZE
);
272 if (!port_info
->rx_buf_alloc
) {
273 printf(SHETHER_NAME
": alloc failed\n");
278 port_info
->rx_buf_base
= (u8
*)ADDR_TO_P2((u32
)port_info
->rx_buf_alloc
);
280 /* Initialize all descriptors */
281 for (cur_rx_desc
= port_info
->rx_desc_base
,
282 rx_buf
= port_info
->rx_buf_base
, i
= 0;
283 i
< NUM_RX_DESC
; cur_rx_desc
++, rx_buf
+= MAX_BUF_SIZE
, i
++) {
284 cur_rx_desc
->rd0
= RD_RACT
;
285 cur_rx_desc
->rd1
= MAX_BUF_SIZE
<< 16;
286 cur_rx_desc
->rd2
= (u32
) ADDR_TO_PHY(rx_buf
);
289 /* Mark the end of the descriptors */
291 cur_rx_desc
->rd0
|= RD_RDLE
;
293 /* Point the controller to the rx descriptor list */
294 sh_eth_write(eth
, ADDR_TO_PHY(port_info
->rx_desc_base
), RDLAR
);
295 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
296 sh_eth_write(eth
, ADDR_TO_PHY(port_info
->rx_desc_base
), RDFAR
);
297 sh_eth_write(eth
, ADDR_TO_PHY(cur_rx_desc
), RDFXR
);
298 sh_eth_write(eth
, RDFFR_RDLF
, RDFFR
);
304 free(port_info
->rx_desc_alloc
);
305 port_info
->rx_desc_alloc
= NULL
;
311 static void sh_eth_tx_desc_free(struct sh_eth_dev
*eth
)
313 int port
= eth
->port
;
314 struct sh_eth_info
*port_info
= ð
->port_info
[port
];
316 if (port_info
->tx_desc_alloc
) {
317 free(port_info
->tx_desc_alloc
);
318 port_info
->tx_desc_alloc
= NULL
;
322 static void sh_eth_rx_desc_free(struct sh_eth_dev
*eth
)
324 int port
= eth
->port
;
325 struct sh_eth_info
*port_info
= ð
->port_info
[port
];
327 if (port_info
->rx_desc_alloc
) {
328 free(port_info
->rx_desc_alloc
);
329 port_info
->rx_desc_alloc
= NULL
;
332 if (port_info
->rx_buf_alloc
) {
333 free(port_info
->rx_buf_alloc
);
334 port_info
->rx_buf_alloc
= NULL
;
338 static int sh_eth_desc_init(struct sh_eth_dev
*eth
)
342 ret
= sh_eth_tx_desc_init(eth
);
346 ret
= sh_eth_rx_desc_init(eth
);
352 sh_eth_tx_desc_free(eth
);
358 static int sh_eth_phy_config(struct sh_eth_dev
*eth
)
360 int port
= eth
->port
, ret
= 0;
361 struct sh_eth_info
*port_info
= ð
->port_info
[port
];
362 struct eth_device
*dev
= port_info
->dev
;
363 struct phy_device
*phydev
;
365 phydev
= phy_connect(
366 miiphy_get_dev_by_name(dev
->name
),
367 port_info
->phy_addr
, dev
, CONFIG_SH_ETHER_PHY_MODE
);
368 port_info
->phydev
= phydev
;
374 static int sh_eth_config(struct sh_eth_dev
*eth
, bd_t
*bd
)
376 int port
= eth
->port
, ret
= 0;
378 struct sh_eth_info
*port_info
= ð
->port_info
[port
];
379 struct eth_device
*dev
= port_info
->dev
;
380 struct phy_device
*phy
;
382 /* Configure e-dmac registers */
383 sh_eth_write(eth
, (sh_eth_read(eth
, EDMR
) & ~EMDR_DESC_R
) |
384 (EMDR_DESC
| EDMR_EL
), EDMR
);
386 sh_eth_write(eth
, 0, EESIPR
);
387 sh_eth_write(eth
, 0, TRSCER
);
388 sh_eth_write(eth
, 0, TFTR
);
389 sh_eth_write(eth
, (FIFO_SIZE_T
| FIFO_SIZE_R
), FDR
);
390 sh_eth_write(eth
, RMCR_RST
, RMCR
);
391 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
392 sh_eth_write(eth
, 0, RPADIR
);
394 sh_eth_write(eth
, (FIFO_F_D_RFF
| FIFO_F_D_RFD
), FCFTR
);
396 /* Configure e-mac registers */
397 sh_eth_write(eth
, 0, ECSIPR
);
399 /* Set Mac address */
400 val
= dev
->enetaddr
[0] << 24 | dev
->enetaddr
[1] << 16 |
401 dev
->enetaddr
[2] << 8 | dev
->enetaddr
[3];
402 sh_eth_write(eth
, val
, MAHR
);
404 val
= dev
->enetaddr
[4] << 8 | dev
->enetaddr
[5];
405 sh_eth_write(eth
, val
, MALR
);
407 sh_eth_write(eth
, RFLR_RFL_MIN
, RFLR
);
408 #if defined(SH_ETH_TYPE_GETHER)
409 sh_eth_write(eth
, 0, PIPR
);
411 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
412 sh_eth_write(eth
, APR_AP
, APR
);
413 sh_eth_write(eth
, MPR_MP
, MPR
);
414 sh_eth_write(eth
, TPAUSER_TPAUSE
, TPAUSER
);
417 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
418 sh_eth_write(eth
, CONFIG_SH_ETHER_SH7734_MII
, RMII_MII
);
419 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
420 defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
421 sh_eth_write(eth
, sh_eth_read(eth
, RMIIMR
) | 0x1, RMIIMR
);
424 ret
= sh_eth_phy_config(eth
);
426 printf(SHETHER_NAME
": phy config timeout\n");
429 phy
= port_info
->phydev
;
430 ret
= phy_startup(phy
);
432 printf(SHETHER_NAME
": phy startup failure\n");
438 /* Set the transfer speed */
439 if (phy
->speed
== 100) {
440 printf(SHETHER_NAME
": 100Base/");
441 #if defined(SH_ETH_TYPE_GETHER)
442 sh_eth_write(eth
, GECMR_100B
, GECMR
);
443 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
444 sh_eth_write(eth
, 1, RTRATE
);
445 #elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \
446 defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \
447 defined(CONFIG_R8A7794)
450 } else if (phy
->speed
== 10) {
451 printf(SHETHER_NAME
": 10Base/");
452 #if defined(SH_ETH_TYPE_GETHER)
453 sh_eth_write(eth
, GECMR_10B
, GECMR
);
454 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
455 sh_eth_write(eth
, 0, RTRATE
);
458 #if defined(SH_ETH_TYPE_GETHER)
459 else if (phy
->speed
== 1000) {
460 printf(SHETHER_NAME
": 1000Base/");
461 sh_eth_write(eth
, GECMR_1000B
, GECMR
);
465 /* Check if full duplex mode is supported by the phy */
468 sh_eth_write(eth
, val
| (ECMR_CHG_DM
|ECMR_RE
|ECMR_TE
|ECMR_DM
),
472 sh_eth_write(eth
, val
| (ECMR_CHG_DM
|ECMR_RE
|ECMR_TE
), ECMR
);
481 static void sh_eth_start(struct sh_eth_dev
*eth
)
484 * Enable the e-dmac receiver only. The transmitter will be enabled when
485 * we have something to transmit
487 sh_eth_write(eth
, EDRRR_R
, EDRRR
);
490 static void sh_eth_stop(struct sh_eth_dev
*eth
)
492 sh_eth_write(eth
, ~EDRRR_R
, EDRRR
);
495 int sh_eth_init(struct eth_device
*dev
, bd_t
*bd
)
498 struct sh_eth_dev
*eth
= dev
->priv
;
500 ret
= sh_eth_reset(eth
);
504 ret
= sh_eth_desc_init(eth
);
508 ret
= sh_eth_config(eth
, bd
);
517 sh_eth_tx_desc_free(eth
);
518 sh_eth_rx_desc_free(eth
);
524 void sh_eth_halt(struct eth_device
*dev
)
526 struct sh_eth_dev
*eth
= dev
->priv
;
530 int sh_eth_initialize(bd_t
*bd
)
533 struct sh_eth_dev
*eth
= NULL
;
534 struct eth_device
*dev
= NULL
;
536 eth
= (struct sh_eth_dev
*)malloc(sizeof(struct sh_eth_dev
));
538 printf(SHETHER_NAME
": %s: malloc failed\n", __func__
);
543 dev
= (struct eth_device
*)malloc(sizeof(struct eth_device
));
545 printf(SHETHER_NAME
": %s: malloc failed\n", __func__
);
549 memset(dev
, 0, sizeof(struct eth_device
));
550 memset(eth
, 0, sizeof(struct sh_eth_dev
));
552 eth
->port
= CONFIG_SH_ETHER_USE_PORT
;
553 eth
->port_info
[eth
->port
].phy_addr
= CONFIG_SH_ETHER_PHY_ADDR
;
555 dev
->priv
= (void *)eth
;
557 dev
->init
= sh_eth_init
;
558 dev
->halt
= sh_eth_halt
;
559 dev
->send
= sh_eth_send
;
560 dev
->recv
= sh_eth_recv
;
561 eth
->port_info
[eth
->port
].dev
= dev
;
563 strcpy(dev
->name
, SHETHER_NAME
);
565 /* Register Device to EtherNet subsystem */
568 bb_miiphy_buses
[0].priv
= eth
;
570 struct mii_dev
*mdiodev
= mdio_alloc();
573 strncpy(mdiodev
->name
, dev
->name
, MDIO_NAME_LEN
);
574 mdiodev
->read
= bb_miiphy_read
;
575 mdiodev
->write
= bb_miiphy_write
;
577 retval
= mdio_register(mdiodev
);
581 if (!eth_getenv_enetaddr("ethaddr", dev
->enetaddr
))
582 puts("Please set MAC address\n");
593 printf(SHETHER_NAME
": Failed\n");
597 /******* for bb_miiphy *******/
598 static int sh_eth_bb_init(struct bb_miiphy_bus
*bus
)
603 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus
*bus
)
605 struct sh_eth_dev
*eth
= bus
->priv
;
607 sh_eth_write(eth
, sh_eth_read(eth
, PIR
) | PIR_MMD
, PIR
);
612 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus
*bus
)
614 struct sh_eth_dev
*eth
= bus
->priv
;
616 sh_eth_write(eth
, sh_eth_read(eth
, PIR
) & ~PIR_MMD
, PIR
);
621 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus
*bus
, int v
)
623 struct sh_eth_dev
*eth
= bus
->priv
;
626 sh_eth_write(eth
, sh_eth_read(eth
, PIR
) | PIR_MDO
, PIR
);
628 sh_eth_write(eth
, sh_eth_read(eth
, PIR
) & ~PIR_MDO
, PIR
);
633 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus
*bus
, int *v
)
635 struct sh_eth_dev
*eth
= bus
->priv
;
637 *v
= (sh_eth_read(eth
, PIR
) & PIR_MDI
) >> 3;
642 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus
*bus
, int v
)
644 struct sh_eth_dev
*eth
= bus
->priv
;
647 sh_eth_write(eth
, sh_eth_read(eth
, PIR
) | PIR_MDC
, PIR
);
649 sh_eth_write(eth
, sh_eth_read(eth
, PIR
) & ~PIR_MDC
, PIR
);
654 static int sh_eth_bb_delay(struct bb_miiphy_bus
*bus
)
661 struct bb_miiphy_bus bb_miiphy_buses
[] = {
664 .init
= sh_eth_bb_init
,
665 .mdio_active
= sh_eth_bb_mdio_active
,
666 .mdio_tristate
= sh_eth_bb_mdio_tristate
,
667 .set_mdio
= sh_eth_bb_set_mdio
,
668 .get_mdio
= sh_eth_bb_get_mdio
,
669 .set_mdc
= sh_eth_bb_set_mdc
,
670 .delay
= sh_eth_bb_delay
,
673 int bb_miiphy_buses_num
= ARRAY_SIZE(bb_miiphy_buses
);