2 * sh_eth.h - Driver for Renesas SuperH ethernet controller.
4 * Copyright (C) 2008 - 2012 Renesas Solutions Corp.
5 * Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu
6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/types.h>
14 #define SHETHER_NAME "sh_eth"
16 #if defined(CONFIG_SH)
17 /* Malloc returns addresses in the P1 area (cacheable). However we need to
18 use area P2 (non-cacheable) */
19 #define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000))
21 /* The ethernet controller needs to use physical addresses */
22 #if defined(CONFIG_SH_32BIT)
23 #define ADDR_TO_PHY(addr) ((((int)(addr) & ~0xe0000000) | 0x40000000))
25 #define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000)
27 #elif defined(CONFIG_ARM)
30 #define ADDR_TO_PHY(addr) ((int)(addr))
31 #define ADDR_TO_P2(addr) (addr)
32 #endif /* defined(CONFIG_SH) */
34 /* base padding size is 16 */
35 #ifndef CONFIG_SH_ETHER_ALIGNE_SIZE
36 #define CONFIG_SH_ETHER_ALIGNE_SIZE 16
39 /* Number of supported ports */
40 #define MAX_PORT_NUM 2
42 /* Buffers must be big enough to hold the largest ethernet frame. Also, rx
43 buffers must be a multiple of 32 bytes */
44 #define MAX_BUF_SIZE (48 * 32)
46 /* The number of tx descriptors must be large enough to point to 5 or more
47 frames. If each frame uses 2 descriptors, at least 10 descriptors are needed.
48 We use one descriptor per frame */
51 /* The size of the tx descriptor is determined by how much padding is used.
52 4, 20, or 52 bytes of padding can be used */
53 #define TX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
55 /* Tx descriptor. We always use 3 bytes of padding */
59 u32 td2
; /* Buffer start */
60 u8 padding
[TX_DESC_PADDING
]; /* aligned cache line size */
63 /* There is no limitation in the number of rx descriptors */
66 /* The size of the rx descriptor is determined by how much padding is used.
67 4, 20, or 52 bytes of padding can be used */
68 #define RX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
69 /* aligned cache line size */
70 #define RX_BUF_ALIGNE_SIZE (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
72 /* Rx descriptor. We always use 4 bytes of padding */
76 u32 rd2
; /* Buffer start */
77 u8 padding
[TX_DESC_PADDING
]; /* aligned cache line size */
81 struct tx_desc_s
*tx_desc_alloc
;
82 struct tx_desc_s
*tx_desc_base
;
83 struct tx_desc_s
*tx_desc_cur
;
84 struct rx_desc_s
*rx_desc_alloc
;
85 struct rx_desc_s
*rx_desc_base
;
86 struct rx_desc_s
*rx_desc_cur
;
91 struct eth_device
*dev
;
92 struct phy_device
*phydev
;
97 struct sh_eth_info port_info
[MAX_PORT_NUM
];
100 /* from linux/drivers/net/ethernet/renesas/sh_eth.h */
102 /* E-DMAC registers */
131 /* Ether registers */
165 RMIIMR
, /* R8A7790 */
171 /* This value must be written at last. */
172 SH_ETH_MAX_REGISTER_OFFSET
,
175 static const u16 sh_eth_offset_gigabit
[SH_ETH_MAX_REGISTER_OFFSET
] = {
229 #if defined(SH_ETH_TYPE_RZ)
230 static const u16 sh_eth_offset_rz
[SH_ETH_MAX_REGISTER_OFFSET
] = {
284 static const u16 sh_eth_offset_fast_sh4
[SH_ETH_MAX_REGISTER_OFFSET
] = {
337 /* Register Address */
338 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
339 #define SH_ETH_TYPE_GETHER
340 #define BASE_IO_ADDR 0xfee00000
341 #elif defined(CONFIG_CPU_SH7757) || \
342 defined(CONFIG_CPU_SH7752) || \
343 defined(CONFIG_CPU_SH7753)
344 #if defined(CONFIG_SH_ETHER_USE_GETHER)
345 #define SH_ETH_TYPE_GETHER
346 #define BASE_IO_ADDR 0xfee00000
348 #define SH_ETH_TYPE_ETHER
349 #define BASE_IO_ADDR 0xfef00000
351 #elif defined(CONFIG_CPU_SH7724)
352 #define SH_ETH_TYPE_ETHER
353 #define BASE_IO_ADDR 0xA4600000
354 #elif defined(CONFIG_R8A7740)
355 #define SH_ETH_TYPE_GETHER
356 #define BASE_IO_ADDR 0xE9A00000
357 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
358 defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
359 #define SH_ETH_TYPE_ETHER
360 #define BASE_IO_ADDR 0xEE700200
361 #elif defined(CONFIG_R7S72100)
362 #define SH_ETH_TYPE_RZ
363 #define BASE_IO_ADDR 0xE8203000
368 * Copy from Linux driver source code
370 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
373 EDSR_ENT
= 0x01, EDSR_ENR
= 0x02,
375 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
380 EDMR_DL1
= 0x20, EDMR_DL0
= 0x10,
381 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
382 EDMR_SRST
= 0x03, /* Receive/Send reset */
383 EMDR_DESC_R
= 0x30, /* Descriptor reserve size */
384 EDMR_EL
= 0x40, /* Litte endian */
385 #elif defined(SH_ETH_TYPE_ETHER)
387 EMDR_DESC_R
= 0x30, /* Descriptor reserve size */
388 EDMR_EL
= 0x40, /* Litte endian */
394 #if CONFIG_SH_ETHER_ALIGNE_SIZE == 64
395 # define EMDR_DESC EDMR_DL1
396 #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32
397 # define EMDR_DESC EDMR_DL0
398 #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */
403 #define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */
407 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
416 #if defined(CONFIG_CPU_SH7757) || \
417 defined(CONFIG_CPU_SH7752) || \
418 defined(CONFIG_CPU_SH7753)
419 GECMR_1000B
= 0x20, GECMR_100B
= 0x01, GECMR_10B
= 0x00,
421 GECMR_1000B
= 0x01, GECMR_100B
= 0x04, GECMR_10B
= 0x00,
432 TPAUSER_TPAUSE
= 0x0000ffff,
433 TPAUSER_UNLIMITED
= 0,
438 BCFR_RPAUSE
= 0x0000ffff,
444 PIR_MDI
= 0x08, PIR_MDO
= 0x04, PIR_MMD
= 0x02, PIR_MDC
= 0x01,
448 enum PHY_STATUS_BIT
{ PHY_ST_LINK
= 0x01, };
452 #if defined(SH_ETH_TYPE_ETHER)
453 EESR_TWB
= 0x40000000,
455 EESR_TWB
= 0xC0000000,
456 EESR_TC1
= 0x20000000,
457 EESR_TUC
= 0x10000000,
458 EESR_ROC
= 0x80000000,
460 EESR_TABT
= 0x04000000,
461 EESR_RABT
= 0x02000000, EESR_RFRMER
= 0x01000000,
462 #if defined(SH_ETH_TYPE_ETHER)
463 EESR_ADE
= 0x00800000,
465 EESR_ECI
= 0x00400000,
466 EESR_FTC
= 0x00200000, EESR_TDE
= 0x00100000,
467 EESR_TFE
= 0x00080000, EESR_FRC
= 0x00040000,
468 EESR_RDE
= 0x00020000, EESR_RFE
= 0x00010000,
469 #if defined(SH_ETH_TYPE_ETHER)
470 EESR_CND
= 0x00000800,
472 EESR_DLC
= 0x00000400,
473 EESR_CD
= 0x00000200, EESR_RTO
= 0x00000100,
474 EESR_RMAF
= 0x00000080, EESR_CEEF
= 0x00000040,
475 EESR_CELF
= 0x00000020, EESR_RRF
= 0x00000010,
476 EESR_RTLF
= 0x00000008, EESR_RTSF
= 0x00000004,
477 EESR_PRE
= 0x00000002, EESR_CERF
= 0x00000001,
481 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
482 # define TX_CHECK (EESR_TC1 | EESR_FTC)
483 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
484 | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
485 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE)
488 # define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO)
489 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
490 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
491 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE)
496 DMAC_M_TWB
= 0x40000000, DMAC_M_TABT
= 0x04000000,
497 DMAC_M_RABT
= 0x02000000,
498 DMAC_M_RFRMER
= 0x01000000, DMAC_M_ADF
= 0x00800000,
499 DMAC_M_ECI
= 0x00400000, DMAC_M_FTC
= 0x00200000,
500 DMAC_M_TDE
= 0x00100000, DMAC_M_TFE
= 0x00080000,
501 DMAC_M_FRC
= 0x00040000, DMAC_M_RDE
= 0x00020000,
502 DMAC_M_RFE
= 0x00010000, DMAC_M_TINT4
= 0x00000800,
503 DMAC_M_TINT3
= 0x00000400, DMAC_M_TINT2
= 0x00000200,
504 DMAC_M_TINT1
= 0x00000100, DMAC_M_RINT8
= 0x00000080,
505 DMAC_M_RINT5
= 0x00000010, DMAC_M_RINT4
= 0x00000008,
506 DMAC_M_RINT3
= 0x00000004, DMAC_M_RINT2
= 0x00000002,
507 DMAC_M_RINT1
= 0x00000001,
510 /* Receive descriptor bit */
512 RD_RACT
= 0x80000000, RD_RDLE
= 0x40000000,
513 RD_RFP1
= 0x20000000, RD_RFP0
= 0x10000000,
514 RD_RFE
= 0x08000000, RD_RFS10
= 0x00000200,
515 RD_RFS9
= 0x00000100, RD_RFS8
= 0x00000080,
516 RD_RFS7
= 0x00000040, RD_RFS6
= 0x00000020,
517 RD_RFS5
= 0x00000010, RD_RFS4
= 0x00000008,
518 RD_RFS3
= 0x00000004, RD_RFS2
= 0x00000002,
519 RD_RFS1
= 0x00000001,
521 #define RDF1ST RD_RFP1
522 #define RDFEND RD_RFP0
523 #define RD_RFP (RD_RFP1|RD_RFP0)
532 FCFTR_RFF2
= 0x00040000, FCFTR_RFF1
= 0x00020000,
533 FCFTR_RFF0
= 0x00010000, FCFTR_RFD2
= 0x00000004,
534 FCFTR_RFD1
= 0x00000002, FCFTR_RFD0
= 0x00000001,
536 #define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
537 #define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
539 /* Transfer descriptor bit */
541 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) || \
542 defined(SH_ETH_TYPE_RZ)
543 TD_TACT
= 0x80000000,
545 TD_TACT
= 0x7fffffff,
547 TD_TDLE
= 0x40000000, TD_TFP1
= 0x20000000,
548 TD_TFP0
= 0x10000000,
550 #define TDF1ST TD_TFP1
551 #define TDFEND TD_TFP0
552 #define TD_TFP (TD_TFP1|TD_TFP0)
555 enum RECV_RST_BIT
{ RMCR_RST
= 0x01, };
557 enum FELIC_MODE_BIT
{
558 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
559 ECMR_TRCCM
= 0x04000000, ECMR_RCSC
= 0x00800000,
560 ECMR_DPAD
= 0x00200000, ECMR_RZPF
= 0x00100000,
562 ECMR_ZPF
= 0x00080000, ECMR_PFR
= 0x00040000, ECMR_RXF
= 0x00020000,
563 ECMR_TXF
= 0x00010000, ECMR_MCT
= 0x00002000, ECMR_PRCEF
= 0x00001000,
564 ECMR_PMDE
= 0x00000200, ECMR_RE
= 0x00000040, ECMR_TE
= 0x00000020,
565 ECMR_ILB
= 0x00000008, ECMR_ELB
= 0x00000004, ECMR_DM
= 0x00000002,
566 ECMR_PRM
= 0x00000001,
567 #ifdef CONFIG_CPU_SH7724
568 ECMR_RTM
= 0x00000010,
569 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
570 defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
571 ECMR_RTM
= 0x00000004,
576 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
577 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | \
578 ECMR_RXF | ECMR_TXF | ECMR_MCT)
579 #elif defined(SH_ETH_TYPE_ETHER)
580 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
582 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
586 enum ECSR_STATUS_BIT
{
587 #if defined(SH_ETH_TYPE_ETHER)
588 ECSR_BRCRX
= 0x20, ECSR_PSRTO
= 0x10,
591 ECSR_MPD
= 0x02, ECSR_ICD
= 0x01,
594 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
595 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
597 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
598 ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP)
602 enum ECSIPR_STATUS_MASK_BIT
{
603 #if defined(SH_ETH_TYPE_ETHER)
604 ECSIPR_BRCRXIP
= 0x20,
605 ECSIPR_PSRTOIP
= 0x10,
606 #elif defined(SH_ETY_TYPE_GETHER)
607 ECSIPR_PSRTOIP
= 0x10,
610 ECSIPR_LCHNGIP
= 0x04,
615 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
616 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
618 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
619 ECSIPR_ICDIP | ECSIPR_MPDIP)
634 DESC_I_TINT4
= 0x0800, DESC_I_TINT3
= 0x0400, DESC_I_TINT2
= 0x0200,
635 DESC_I_TINT1
= 0x0100, DESC_I_RINT8
= 0x0080, DESC_I_RINT5
= 0x0010,
636 DESC_I_RINT4
= 0x0008, DESC_I_RINT3
= 0x0004, DESC_I_RINT2
= 0x0002,
637 DESC_I_RINT1
= 0x0001,
642 RPADIR_PADS1
= 0x20000, RPADIR_PADS0
= 0x10000,
643 RPADIR_PADR
= 0x0003f,
646 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
647 # define RPADIR_INIT (0x00)
649 # define RPADIR_INIT (RPADIR_PADS1)
654 FIFO_SIZE_T
= 0x00000700, FIFO_SIZE_R
= 0x00000007,
657 static inline unsigned long sh_eth_reg_addr(struct sh_eth_dev
*eth
,
660 #if defined(SH_ETH_TYPE_GETHER)
661 const u16
*reg_offset
= sh_eth_offset_gigabit
;
662 #elif defined(SH_ETH_TYPE_ETHER)
663 const u16
*reg_offset
= sh_eth_offset_fast_sh4
;
664 #elif defined(SH_ETH_TYPE_RZ)
665 const u16
*reg_offset
= sh_eth_offset_rz
;
669 return BASE_IO_ADDR
+ reg_offset
[enum_index
] + 0x800 * eth
->port
;
672 static inline void sh_eth_write(struct sh_eth_dev
*eth
, unsigned long data
,
675 outl(data
, sh_eth_reg_addr(eth
, enum_index
));
678 static inline unsigned long sh_eth_read(struct sh_eth_dev
*eth
,
681 return inl(sh_eth_reg_addr(eth
, enum_index
));