1 /*------------------------------------------------------------------------
3 . This is a driver for SMSC's 91C111 single-chip Ethernet device.
6 . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 . Rolf Offermanns <rof@sysgo.de>
9 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
10 . Developed by Simple Network Magic Corporation (SNMC)
11 . Copyright (C) 1996 by Erik Stahlman (ES)
13 * SPDX-License-Identifier: GPL-2.0+
15 . Information contained in this file was obtained from the LAN91C111
16 . manual from SMC. To get a copy, if you really want one, you can find
17 . information under www.smsc.com.
20 . "Features" of the SMC chip:
21 . Integrated PHY/MAC for 10/100BaseT Operation
22 . Supports internal and external MII
23 . Integrated 8K packet memory
24 . EEPROM interface for configuration
27 . io = for the base address
31 . Erik Stahlman ( erik@vt.edu )
32 . Daris A Nevil ( dnevil@snmc.com )
35 . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
38 . o SMSC LAN91C111 databook (www.smsc.com)
39 . o smc9194.c by Erik Stahlman
40 . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
43 . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks.
44 . 10/17/01 Marco Hasewinkel Modify for DNP/1110
45 . 07/25/01 Woojung Huh Modify for ADS Bitsy
46 . 04/25/01 Daris A Nevil Initial public release through SMSC
47 . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111
48 ----------------------------------------------------------------------------*/
57 /* Use power-down feature of the chip */
65 static const char version
[] =
66 "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n";
69 /* Autonegotiation timeout in seconds */
70 #ifndef CONFIG_SMC_AUTONEG_TIMEOUT
71 #define CONFIG_SMC_AUTONEG_TIMEOUT 10
74 /*------------------------------------------------------------------------
76 . Configuration options, for the experienced user to change.
78 -------------------------------------------------------------------------*/
81 . Wait time for memory to be free. This probably shouldn't be
82 . tuned that much, as waiting for this means nothing else happens
85 #define MEMORY_WAIT_TIME 16
89 #define PRINTK3(args...) printf(args)
91 #define PRINTK3(args...)
95 #define PRINTK2(args...) printf(args)
97 #define PRINTK2(args...)
101 #define PRINTK(args...) printf(args)
103 #define PRINTK(args...)
107 /*------------------------------------------------------------------------
109 . The internal workings of the driver. If you are changing anything
110 . here with the SMC stuff, you should have the datasheet and know
111 . what you are doing.
113 -------------------------------------------------------------------------*/
115 /* Memory sizing constant */
116 #define LAN91C111_MEMORY_MULTIPLIER (1024*2)
118 #ifndef CONFIG_SMC91111_BASE
119 #error "SMC91111 Base address must be passed to initialization funciton"
120 /* #define CONFIG_SMC91111_BASE 0x20000300 */
123 #define SMC_DEV_NAME "SMC91111"
124 #define SMC_PHY_ADDR 0x0000
125 #define SMC_ALLOC_MAX_TRY 5
126 #define SMC_TX_TIMEOUT 30
128 #define SMC_PHY_CLOCK_DELAY 1000
132 #ifdef CONFIG_SMC_USE_32_BIT
138 #ifdef SHARED_RESOURCES
139 extern void swap_to(int device_id
);
144 #ifndef CONFIG_SMC91111_EXT_PHY
145 static void smc_phy_configure(struct eth_device
*dev
);
146 #endif /* !CONFIG_SMC91111_EXT_PHY */
149 ------------------------------------------------------------
153 ------------------------------------------------------------
156 #ifdef CONFIG_SMC_USE_IOFUNCS
158 * input and output functions
160 * Implemented due to inx,outx macros accessing the device improperly
161 * and putting the device into an unkown state.
163 * For instance, on Sharp LPD7A400 SDK, affects were chip memory
164 * could not be free'd (hence the alloc failures), duplicate packets,
165 * packets being corrupt (shifted) on the wire, etc. Switching to the
166 * inx,outx functions fixed this problem.
169 static inline word
SMC_inw(struct eth_device
*dev
, dword offset
)
172 v
= *((volatile word
*)(dev
->iobase
+ offset
));
173 barrier(); *(volatile u32
*)(0xc0000000);
177 static inline void SMC_outw(struct eth_device
*dev
, word value
, dword offset
)
179 *((volatile word
*)(dev
->iobase
+ offset
)) = value
;
180 barrier(); *(volatile u32
*)(0xc0000000);
183 static inline byte
SMC_inb(struct eth_device
*dev
, dword offset
)
187 _w
= SMC_inw(dev
, offset
& ~((dword
)1));
188 return (offset
& 1) ? (byte
)(_w
>> 8) : (byte
)(_w
);
191 static inline void SMC_outb(struct eth_device
*dev
, byte value
, dword offset
)
195 _w
= SMC_inw(dev
, offset
& ~((dword
)1));
197 *((volatile word
*)(dev
->iobase
+ (offset
& ~((dword
)1)))) =
198 (value
<<8) | (_w
& 0x00ff);
200 *((volatile word
*)(dev
->iobase
+ offset
)) =
201 value
| (_w
& 0xff00);
204 static inline void SMC_insw(struct eth_device
*dev
, dword offset
,
205 volatile uchar
* buf
, dword len
)
207 volatile word
*p
= (volatile word
*)buf
;
210 *p
++ = SMC_inw(dev
, offset
);
212 *((volatile u32
*)(0xc0000000));
216 static inline void SMC_outsw(struct eth_device
*dev
, dword offset
,
217 uchar
* buf
, dword len
)
219 volatile word
*p
= (volatile word
*)buf
;
222 SMC_outw(dev
, *p
++, offset
);
224 *(volatile u32
*)(0xc0000000);
227 #endif /* CONFIG_SMC_USE_IOFUNCS */
230 . A rather simple routine to print out a packet for debugging purposes.
233 static void print_packet( byte
*, int );
236 #define tx_done(dev) 1
238 static int poll4int (struct eth_device
*dev
, byte mask
, int timeout
)
240 int tmo
= get_timer (0) + timeout
* CONFIG_SYS_HZ
;
242 word old_bank
= SMC_inw (dev
, BSR_REG
);
244 PRINTK2 ("Polling...\n");
245 SMC_SELECT_BANK (dev
, 2);
246 while ((SMC_inw (dev
, SMC91111_INT_REG
) & mask
) == 0) {
247 if (get_timer (0) >= tmo
) {
253 /* restore old bank selection */
254 SMC_SELECT_BANK (dev
, old_bank
);
262 /* Only one release command at a time, please */
263 static inline void smc_wait_mmu_release_complete (struct eth_device
*dev
)
267 /* assume bank 2 selected */
268 while (SMC_inw (dev
, MMU_CMD_REG
) & MC_BUSY
) {
269 udelay (1); /* Wait until not busy */
276 . Function: smc_reset( void )
278 . This sets the SMC91111 chip to its normal state, hopefully from whatever
279 . mess that any other DOS driver has put it in.
281 . Maybe I should reset more registers to defaults in here? SOFTRST should
285 . 1. send a SOFT RESET
286 . 2. wait for it to finish
287 . 3. enable autorelease mode
288 . 4. reset the memory management unit
289 . 5. clear all interrupts
292 static void smc_reset (struct eth_device
*dev
)
294 PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME
);
296 /* This resets the registers mostly to defaults, but doesn't
297 affect EEPROM. That seems unnecessary */
298 SMC_SELECT_BANK (dev
, 0);
299 SMC_outw (dev
, RCR_SOFTRST
, RCR_REG
);
301 /* Setup the Configuration Register */
302 /* This is necessary because the CONFIG_REG is not affected */
303 /* by a soft reset */
305 SMC_SELECT_BANK (dev
, 1);
306 #if defined(CONFIG_SMC91111_EXT_PHY)
307 SMC_outw (dev
, CONFIG_DEFAULT
| CONFIG_EXT_PHY
, CONFIG_REG
);
309 SMC_outw (dev
, CONFIG_DEFAULT
, CONFIG_REG
);
313 /* Release from possible power-down state */
314 /* Configuration register is not affected by Soft Reset */
315 SMC_outw (dev
, SMC_inw (dev
, CONFIG_REG
) | CONFIG_EPH_POWER_EN
,
318 SMC_SELECT_BANK (dev
, 0);
320 /* this should pause enough for the chip to be happy */
323 /* Disable transmit and receive functionality */
324 SMC_outw (dev
, RCR_CLEAR
, RCR_REG
);
325 SMC_outw (dev
, TCR_CLEAR
, TCR_REG
);
327 /* set the control register */
328 SMC_SELECT_BANK (dev
, 1);
329 SMC_outw (dev
, CTL_DEFAULT
, CTL_REG
);
332 SMC_SELECT_BANK (dev
, 2);
333 smc_wait_mmu_release_complete (dev
);
334 SMC_outw (dev
, MC_RESET
, MMU_CMD_REG
);
335 while (SMC_inw (dev
, MMU_CMD_REG
) & MC_BUSY
)
336 udelay (1); /* Wait until not busy */
338 /* Note: It doesn't seem that waiting for the MMU busy is needed here,
339 but this is a place where future chipsets _COULD_ break. Be wary
340 of issuing another MMU command right after this */
342 /* Disable all interrupts */
343 SMC_outb (dev
, 0, IM_REG
);
347 . Function: smc_enable
348 . Purpose: let the chip talk to the outside work
350 . 1. Enable the transmitter
351 . 2. Enable the receiver
352 . 3. Enable interrupts
354 static void smc_enable(struct eth_device
*dev
)
356 PRINTK2("%s: smc_enable\n", SMC_DEV_NAME
);
357 SMC_SELECT_BANK( dev
, 0 );
358 /* see the header file for options in TCR/RCR DEFAULT*/
359 SMC_outw( dev
, TCR_DEFAULT
, TCR_REG
);
360 SMC_outw( dev
, RCR_DEFAULT
, RCR_REG
);
363 /* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
368 . Purpose: closes down the SMC91xxx chip.
370 . 1. zero the interrupt mask
371 . 2. clear the enable receive flag
372 . 3. clear the enable xmit flags
375 . (1) maybe utilize power down mode.
376 . Why not yet? Because while the chip will go into power down mode,
377 . the manual says that it will wake up in response to any I/O requests
378 . in the register space. Empirical results do not show this working.
380 static void smc_halt(struct eth_device
*dev
)
382 PRINTK2("%s: smc_halt\n", SMC_DEV_NAME
);
384 /* no more interrupts for me */
385 SMC_SELECT_BANK( dev
, 2 );
386 SMC_outb( dev
, 0, IM_REG
);
388 /* and tell the card to stay away from that nasty outside world */
389 SMC_SELECT_BANK( dev
, 0 );
390 SMC_outb( dev
, RCR_CLEAR
, RCR_REG
);
391 SMC_outb( dev
, TCR_CLEAR
, TCR_REG
);
398 . Function: smc_send(struct net_device * )
400 . This sends the actual packet to the SMC9xxx chip.
403 . First, see if a saved_skb is available.
404 . ( this should NOT be called if there is no 'saved_skb'
405 . Now, find the packet number that the chip allocated
406 . Point the data pointers at it in memory
407 . Set the length word in the chip's memory
408 . Dump the packet to chip memory
409 . Check if a last byte is needed ( odd length packet )
410 . if so, set the control flag right
411 . Tell the card to send it
412 . Enable the transmit interrupt, so I know if it failed
413 . Free the kernel data if I actually sent it.
415 static int smc_send(struct eth_device
*dev
, void *packet
, int packet_length
)
427 /* save PTR and PNR registers before manipulation */
428 SMC_SELECT_BANK (dev
, 2);
429 saved_pnr
= SMC_inb( dev
, PN_REG
);
430 saved_ptr
= SMC_inw( dev
, PTR_REG
);
432 PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME
);
434 length
= ETH_ZLEN
< packet_length
? packet_length
: ETH_ZLEN
;
437 ** The MMU wants the number of pages to be the number of 256 bytes
438 ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
440 ** The 91C111 ignores the size bits, but the code is left intact
441 ** for backwards and future compatibility.
443 ** Pkt size for allocating is data length +6 (for additional status
444 ** words, length and ctl!)
446 ** If odd size then last byte is included in this header.
448 numPages
= ((length
& 0xfffe) + 6);
449 numPages
>>= 8; /* Divide by 256 */
452 printf ("%s: Far too big packet error. \n", SMC_DEV_NAME
);
456 /* now, try to allocate the memory */
457 SMC_SELECT_BANK (dev
, 2);
458 SMC_outw (dev
, MC_ALLOC
| numPages
, MMU_CMD_REG
);
460 /* FIXME: the ALLOC_INT bit never gets set *
461 * so the following will always give a *
462 * memory allocation error. *
463 * same code works in armboot though *
469 time_out
= MEMORY_WAIT_TIME
;
471 status
= SMC_inb (dev
, SMC91111_INT_REG
);
472 if (status
& IM_ALLOC_INT
) {
473 /* acknowledge the interrupt */
474 SMC_outb (dev
, IM_ALLOC_INT
, SMC91111_INT_REG
);
477 } while (--time_out
);
480 PRINTK2 ("%s: memory allocation, try %d failed ...\n",
482 if (try < SMC_ALLOC_MAX_TRY
)
488 PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
491 buf
= (byte
*) packet
;
493 /* If I get here, I _know_ there is a packet slot waiting for me */
494 packet_no
= SMC_inb (dev
, AR_REG
);
495 if (packet_no
& AR_FAILED
) {
496 /* or isn't there? BAD CHIP! */
497 printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME
);
501 /* we have a packet address, so tell the card to use it */
502 #ifndef CONFIG_XAENIAX
503 SMC_outb (dev
, packet_no
, PN_REG
);
505 /* On Xaeniax board, we can't use SMC_outb here because that way
506 * the Allocate MMU command will end up written to the command register
507 * as well, which will lead to a problem.
509 SMC_outl (dev
, packet_no
<< 16, 0);
511 /* do not write new ptr value if Write data fifo not empty */
512 while ( saved_ptr
& PTR_NOTEMPTY
)
513 printf ("Write data fifo not empty!\n");
515 /* point to the beginning of the packet */
516 SMC_outw (dev
, PTR_AUTOINC
, PTR_REG
);
518 PRINTK3 ("%s: Trying to xmit packet of length %x\n",
519 SMC_DEV_NAME
, length
);
522 printf ("Transmitting Packet\n");
523 print_packet (buf
, length
);
526 /* send the packet length ( +6 for status, length and ctl byte )
527 and the status word ( set to zeros ) */
529 SMC_outl (dev
, (length
+ 6) << 16, SMC91111_DATA_REG
);
531 SMC_outw (dev
, 0, SMC91111_DATA_REG
);
532 /* send the packet length ( +6 for status words, length, and ctl */
533 SMC_outw (dev
, (length
+ 6), SMC91111_DATA_REG
);
536 /* send the actual data
537 . I _think_ it's faster to send the longs first, and then
538 . mop up by sending the last word. It depends heavily
539 . on alignment, at least on the 486. Maybe it would be
540 . a good idea to check which is optimal? But that could take
541 . almost as much time as is saved?
544 SMC_outsl (dev
, SMC91111_DATA_REG
, buf
, length
>> 2);
545 #ifndef CONFIG_XAENIAX
547 SMC_outw (dev
, *((word
*) (buf
+ (length
& 0xFFFFFFFC))),
550 /* On XANEIAX, we can only use 32-bit writes, so we need to handle
551 * unaligned tail part specially. The standard code doesn't work.
553 if ((length
& 3) == 3) {
554 u16
* ptr
= (u16
*) &buf
[length
-3];
555 SMC_outl(dev
, (*ptr
) | ((0x2000 | buf
[length
-1]) << 16),
557 } else if ((length
& 2) == 2) {
558 u16
* ptr
= (u16
*) &buf
[length
-2];
559 SMC_outl(dev
, *ptr
, SMC91111_DATA_REG
);
560 } else if (length
& 1) {
561 SMC_outl(dev
, (0x2000 | buf
[length
-1]), SMC91111_DATA_REG
);
563 SMC_outl(dev
, 0, SMC91111_DATA_REG
);
567 SMC_outsw (dev
, SMC91111_DATA_REG
, buf
, (length
) >> 1);
568 #endif /* USE_32_BIT */
570 #ifndef CONFIG_XAENIAX
571 /* Send the last byte, if there is one. */
572 if ((length
& 1) == 0) {
573 SMC_outw (dev
, 0, SMC91111_DATA_REG
);
575 SMC_outw (dev
, buf
[length
- 1] | 0x2000, SMC91111_DATA_REG
);
579 /* and let the chipset deal with it */
580 SMC_outw (dev
, MC_ENQUEUE
, MMU_CMD_REG
);
582 /* poll for TX INT */
583 /* if (poll4int (dev, IM_TX_INT, SMC_TX_TIMEOUT)) { */
584 /* poll for TX_EMPTY INT - autorelease enabled */
585 if (poll4int(dev
, IM_TX_EMPTY_INT
, SMC_TX_TIMEOUT
)) {
587 PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME
);
590 /* no need to release, MMU does that now */
591 #ifdef CONFIG_XAENIAX
592 SMC_outw (dev
, MC_FREEPKT
, MMU_CMD_REG
);
595 /* wait for MMU getting ready (low) */
596 while (SMC_inw (dev
, MMU_CMD_REG
) & MC_BUSY
) {
600 PRINTK2 ("MMU ready\n");
606 SMC_outb (dev
, IM_TX_EMPTY_INT
, SMC91111_INT_REG
);
607 /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */
608 PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME
,
612 /* no need to release, MMU does that now */
613 #ifdef CONFIG_XAENIAX
614 SMC_outw (dev
, MC_FREEPKT
, MMU_CMD_REG
);
617 /* wait for MMU getting ready (low) */
618 while (SMC_inw (dev
, MMU_CMD_REG
) & MC_BUSY
) {
622 PRINTK2 ("MMU ready\n");
627 /* restore previously saved registers */
628 #ifndef CONFIG_XAENIAX
629 SMC_outb( dev
, saved_pnr
, PN_REG
);
631 /* On Xaeniax board, we can't use SMC_outb here because that way
632 * the Allocate MMU command will end up written to the command register
633 * as well, which will lead to a problem.
635 SMC_outl(dev
, saved_pnr
<< 16, 0);
637 SMC_outw( dev
, saved_ptr
, PTR_REG
);
642 static int smc_write_hwaddr(struct eth_device
*dev
)
647 SMC_SELECT_BANK (dev
, 1);
649 for (i
= 0; i
< 6; i
+= 2) {
652 address
= dev
->enetaddr
[i
+ 1] << 8;
653 address
|= dev
->enetaddr
[i
];
654 SMC_outw(dev
, address
, (ADDR0_REG
+ i
));
657 for (i
= 0; i
< 6; i
++)
658 SMC_outb(dev
, dev
->enetaddr
[i
], (ADDR0_REG
+ i
));
665 * Open and Initialize the board
667 * Set up everything, reset the card, etc ..
670 static int smc_init(struct eth_device
*dev
, bd_t
*bd
)
674 PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME
);
676 /* reset the hardware */
680 /* Configure the PHY */
681 #ifndef CONFIG_SMC91111_EXT_PHY
682 smc_phy_configure (dev
);
685 /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
686 /* SMC_SELECT_BANK(dev, 0); */
687 /* SMC_outw(dev, 0, RPC_REG); */
689 printf(SMC_DEV_NAME
": MAC %pM\n", dev
->enetaddr
);
694 /*-------------------------------------------------------------
696 . smc_rcv - receive a packet from the card
698 . There is ( at least ) a packet waiting to be read from
702 . o If an error, record it
703 . o otherwise, read in the packet
704 --------------------------------------------------------------
706 static int smc_rcv(struct eth_device
*dev
)
718 SMC_SELECT_BANK(dev
, 2);
719 /* save PTR and PTR registers */
720 saved_pnr
= SMC_inb( dev
, PN_REG
);
721 saved_ptr
= SMC_inw( dev
, PTR_REG
);
723 packet_number
= SMC_inw( dev
, RXFIFO_REG
);
725 if ( packet_number
& RXFIFO_REMPTY
) {
730 PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME
);
731 /* start reading from the start of the packet */
732 SMC_outw( dev
, PTR_READ
| PTR_RCV
| PTR_AUTOINC
, PTR_REG
);
734 /* First two words are status and packet_length */
736 stat_len
= SMC_inl(dev
, SMC91111_DATA_REG
);
737 status
= stat_len
& 0xffff;
738 packet_length
= stat_len
>> 16;
740 status
= SMC_inw( dev
, SMC91111_DATA_REG
);
741 packet_length
= SMC_inw( dev
, SMC91111_DATA_REG
);
744 packet_length
&= 0x07ff; /* mask off top bits */
746 PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status
, packet_length
);
748 if ( !(status
& RS_ERRORS
) ){
749 /* Adjust for having already read the first two words */
750 packet_length
-= 4; /*4; */
753 /* set odd length for bug in LAN91C111, */
754 /* which never sets RS_ODDFRAME */
759 PRINTK3(" Reading %d dwords (and %d bytes) \n",
760 packet_length
>> 2, packet_length
& 3 );
761 /* QUESTION: Like in the TX routine, do I want
762 to send the DWORDs or the bytes first, or some
763 mixture. A mixture might improve already slow PIO
765 SMC_insl( dev
, SMC91111_DATA_REG
, NetRxPackets
[0],
766 packet_length
>> 2 );
767 /* read the left over bytes */
768 if (packet_length
& 3) {
771 byte
*tail
= (byte
*)(NetRxPackets
[0] +
772 (packet_length
& ~3));
773 dword leftover
= SMC_inl(dev
, SMC91111_DATA_REG
);
774 for (i
=0; i
<(packet_length
& 3); i
++)
775 *tail
++ = (byte
) (leftover
>> (8*i
)) & 0xff;
778 PRINTK3(" Reading %d words and %d byte(s) \n",
779 (packet_length
>> 1 ), packet_length
& 1 );
780 SMC_insw(dev
, SMC91111_DATA_REG
, NetRxPackets
[0],
783 #endif /* USE_32_BIT */
786 printf("Receiving Packet\n");
787 print_packet( NetRxPackets
[0], packet_length
);
795 while ( SMC_inw( dev
, MMU_CMD_REG
) & MC_BUSY
)
796 udelay(1); /* Wait until not busy */
798 /* error or good, tell the card to get rid of this packet */
799 SMC_outw( dev
, MC_RELEASE
, MMU_CMD_REG
);
801 while ( SMC_inw( dev
, MMU_CMD_REG
) & MC_BUSY
)
802 udelay(1); /* Wait until not busy */
804 /* restore saved registers */
805 #ifndef CONFIG_XAENIAX
806 SMC_outb( dev
, saved_pnr
, PN_REG
);
808 /* On Xaeniax board, we can't use SMC_outb here because that way
809 * the Allocate MMU command will end up written to the command register
810 * as well, which will lead to a problem.
812 SMC_outl( dev
, saved_pnr
<< 16, 0);
814 SMC_outw( dev
, saved_ptr
, PTR_REG
);
817 /* Pass the packet up to the protocol layers. */
818 NetReceive(NetRxPackets
[0], packet_length
);
819 return packet_length
;
828 /*------------------------------------------------------------
829 . Modify a bit in the LAN91C111 register set
830 .-------------------------------------------------------------*/
831 static word
smc_modify_regbit(struct eth_device
*dev
, int bank
, int ioaddr
, int reg
,
832 unsigned int bit
, int val
)
836 SMC_SELECT_BANK( dev
, bank
);
838 regval
= SMC_inw( dev
, reg
);
844 SMC_outw( dev
, regval
, 0 );
849 /*------------------------------------------------------------
850 . Retrieve a bit in the LAN91C111 register set
851 .-------------------------------------------------------------*/
852 static int smc_get_regbit(struct eth_device
*dev
, int bank
, int ioaddr
, int reg
, unsigned int bit
)
854 SMC_SELECT_BANK( dev
, bank
);
855 if ( SMC_inw( dev
, reg
) & bit
)
862 /*------------------------------------------------------------
863 . Modify a LAN91C111 register (word access only)
864 .-------------------------------------------------------------*/
865 static void smc_modify_reg(struct eth_device
*dev
, int bank
, int ioaddr
, int reg
, word val
)
867 SMC_SELECT_BANK( dev
, bank
);
868 SMC_outw( dev
, val
, reg
);
872 /*------------------------------------------------------------
873 . Retrieve a LAN91C111 register (word access only)
874 .-------------------------------------------------------------*/
875 static int smc_get_reg(struct eth_device
*dev
, int bank
, int ioaddr
, int reg
)
877 SMC_SELECT_BANK( dev
, bank
);
878 return(SMC_inw( dev
, reg
));
883 /*---PHY CONTROL AND CONFIGURATION----------------------------------------- */
887 /*------------------------------------------------------------
888 . Debugging function for viewing MII Management serial bitstream
889 .-------------------------------------------------------------*/
890 static void smc_dump_mii_stream (byte
* bits
, int size
)
895 for (i
= 0; i
< size
; ++i
) {
896 printf ("%d", i
% 10);
900 for (i
= 0; i
< size
; ++i
) {
901 if (bits
[i
] & MII_MDOE
)
908 for (i
= 0; i
< size
; ++i
) {
909 if (bits
[i
] & MII_MDO
)
916 for (i
= 0; i
< size
; ++i
) {
917 if (bits
[i
] & MII_MDI
)
927 /*------------------------------------------------------------
928 . Reads a register from the MII Management serial interface
929 .-------------------------------------------------------------*/
930 #ifndef CONFIG_SMC91111_EXT_PHY
931 static word
smc_read_phy_register (struct eth_device
*dev
, byte phyreg
)
941 byte phyaddr
= SMC_PHY_ADDR
;
943 /* 32 consecutive ones on MDO to establish sync */
944 for (i
= 0; i
< 32; ++i
)
945 bits
[clk_idx
++] = MII_MDOE
| MII_MDO
;
947 /* Start code <01> */
948 bits
[clk_idx
++] = MII_MDOE
;
949 bits
[clk_idx
++] = MII_MDOE
| MII_MDO
;
951 /* Read command <10> */
952 bits
[clk_idx
++] = MII_MDOE
| MII_MDO
;
953 bits
[clk_idx
++] = MII_MDOE
;
955 /* Output the PHY address, msb first */
957 for (i
= 0; i
< 5; ++i
) {
959 bits
[clk_idx
++] = MII_MDOE
| MII_MDO
;
961 bits
[clk_idx
++] = MII_MDOE
;
963 /* Shift to next lowest bit */
967 /* Output the phy register number, msb first */
969 for (i
= 0; i
< 5; ++i
) {
971 bits
[clk_idx
++] = MII_MDOE
| MII_MDO
;
973 bits
[clk_idx
++] = MII_MDOE
;
975 /* Shift to next lowest bit */
979 /* Tristate and turnaround (2 bit times) */
981 /*bits[clk_idx++] = 0; */
983 /* Input starts at this bit time */
986 /* Will input 16 bits */
987 for (i
= 0; i
< 16; ++i
)
990 /* Final clock bit */
993 /* Save the current bank */
994 oldBank
= SMC_inw (dev
, BANK_SELECT
);
997 SMC_SELECT_BANK (dev
, 3);
999 /* Get the current MII register value */
1000 mii_reg
= SMC_inw (dev
, MII_REG
);
1002 /* Turn off all MII Interface bits */
1003 mii_reg
&= ~(MII_MDOE
| MII_MCLK
| MII_MDI
| MII_MDO
);
1005 /* Clock all 64 cycles */
1006 for (i
= 0; i
< sizeof bits
; ++i
) {
1007 /* Clock Low - output data */
1008 SMC_outw (dev
, mii_reg
| bits
[i
], MII_REG
);
1009 udelay (SMC_PHY_CLOCK_DELAY
);
1012 /* Clock Hi - input data */
1013 SMC_outw (dev
, mii_reg
| bits
[i
] | MII_MCLK
, MII_REG
);
1014 udelay (SMC_PHY_CLOCK_DELAY
);
1015 bits
[i
] |= SMC_inw (dev
, MII_REG
) & MII_MDI
;
1018 /* Return to idle state */
1019 /* Set clock to low, data to low, and output tristated */
1020 SMC_outw (dev
, mii_reg
, MII_REG
);
1021 udelay (SMC_PHY_CLOCK_DELAY
);
1023 /* Restore original bank select */
1024 SMC_SELECT_BANK (dev
, oldBank
);
1026 /* Recover input data */
1028 for (i
= 0; i
< 16; ++i
) {
1031 if (bits
[input_idx
++] & MII_MDI
)
1035 #if (SMC_DEBUG > 2 )
1036 printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
1037 phyaddr
, phyreg
, phydata
);
1038 smc_dump_mii_stream (bits
, sizeof bits
);
1045 /*------------------------------------------------------------
1046 . Writes a register to the MII Management serial interface
1047 .-------------------------------------------------------------*/
1048 static void smc_write_phy_register (struct eth_device
*dev
, byte phyreg
,
1057 byte phyaddr
= SMC_PHY_ADDR
;
1059 /* 32 consecutive ones on MDO to establish sync */
1060 for (i
= 0; i
< 32; ++i
)
1061 bits
[clk_idx
++] = MII_MDOE
| MII_MDO
;
1063 /* Start code <01> */
1064 bits
[clk_idx
++] = MII_MDOE
;
1065 bits
[clk_idx
++] = MII_MDOE
| MII_MDO
;
1067 /* Write command <01> */
1068 bits
[clk_idx
++] = MII_MDOE
;
1069 bits
[clk_idx
++] = MII_MDOE
| MII_MDO
;
1071 /* Output the PHY address, msb first */
1073 for (i
= 0; i
< 5; ++i
) {
1075 bits
[clk_idx
++] = MII_MDOE
| MII_MDO
;
1077 bits
[clk_idx
++] = MII_MDOE
;
1079 /* Shift to next lowest bit */
1083 /* Output the phy register number, msb first */
1085 for (i
= 0; i
< 5; ++i
) {
1087 bits
[clk_idx
++] = MII_MDOE
| MII_MDO
;
1089 bits
[clk_idx
++] = MII_MDOE
;
1091 /* Shift to next lowest bit */
1095 /* Tristate and turnaround (2 bit times) */
1096 bits
[clk_idx
++] = 0;
1097 bits
[clk_idx
++] = 0;
1099 /* Write out 16 bits of data, msb first */
1101 for (i
= 0; i
< 16; ++i
) {
1103 bits
[clk_idx
++] = MII_MDOE
| MII_MDO
;
1105 bits
[clk_idx
++] = MII_MDOE
;
1107 /* Shift to next lowest bit */
1111 /* Final clock bit (tristate) */
1112 bits
[clk_idx
++] = 0;
1114 /* Save the current bank */
1115 oldBank
= SMC_inw (dev
, BANK_SELECT
);
1118 SMC_SELECT_BANK (dev
, 3);
1120 /* Get the current MII register value */
1121 mii_reg
= SMC_inw (dev
, MII_REG
);
1123 /* Turn off all MII Interface bits */
1124 mii_reg
&= ~(MII_MDOE
| MII_MCLK
| MII_MDI
| MII_MDO
);
1126 /* Clock all cycles */
1127 for (i
= 0; i
< sizeof bits
; ++i
) {
1128 /* Clock Low - output data */
1129 SMC_outw (dev
, mii_reg
| bits
[i
], MII_REG
);
1130 udelay (SMC_PHY_CLOCK_DELAY
);
1133 /* Clock Hi - input data */
1134 SMC_outw (dev
, mii_reg
| bits
[i
] | MII_MCLK
, MII_REG
);
1135 udelay (SMC_PHY_CLOCK_DELAY
);
1136 bits
[i
] |= SMC_inw (dev
, MII_REG
) & MII_MDI
;
1139 /* Return to idle state */
1140 /* Set clock to low, data to low, and output tristated */
1141 SMC_outw (dev
, mii_reg
, MII_REG
);
1142 udelay (SMC_PHY_CLOCK_DELAY
);
1144 /* Restore original bank select */
1145 SMC_SELECT_BANK (dev
, oldBank
);
1147 #if (SMC_DEBUG > 2 )
1148 printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
1149 phyaddr
, phyreg
, phydata
);
1150 smc_dump_mii_stream (bits
, sizeof bits
);
1153 #endif /* !CONFIG_SMC91111_EXT_PHY */
1156 /*------------------------------------------------------------
1157 . Configures the specified PHY using Autonegotiation. Calls
1158 . smc_phy_fixed() if the user has requested a certain config.
1159 .-------------------------------------------------------------*/
1160 #ifndef CONFIG_SMC91111_EXT_PHY
1161 static void smc_phy_configure (struct eth_device
*dev
)
1164 word my_phy_caps
; /* My PHY capabilities */
1165 word my_ad_caps
; /* My Advertised capabilities */
1166 word status
= 0; /*;my status = 0 */
1168 PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME
);
1170 /* Reset the PHY, setting all other bits to zero */
1171 smc_write_phy_register (dev
, PHY_CNTL_REG
, PHY_CNTL_RST
);
1173 /* Wait for the reset to complete, or time out */
1174 timeout
= 6; /* Wait up to 3 seconds */
1176 if (!(smc_read_phy_register (dev
, PHY_CNTL_REG
)
1178 /* reset complete */
1182 mdelay(500); /* wait 500 millisecs */
1186 printf ("%s:PHY reset timed out\n", SMC_DEV_NAME
);
1187 goto smc_phy_configure_exit
;
1190 /* Read PHY Register 18, Status Output */
1191 /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */
1193 /* Enable PHY Interrupts (for register 18) */
1194 /* Interrupts listed here are disabled */
1195 smc_write_phy_register (dev
, PHY_MASK_REG
, 0xffff);
1197 /* Configure the Receive/Phy Control register */
1198 SMC_SELECT_BANK (dev
, 0);
1199 SMC_outw (dev
, RPC_DEFAULT
, RPC_REG
);
1201 /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
1202 my_phy_caps
= smc_read_phy_register (dev
, PHY_STAT_REG
);
1203 my_ad_caps
= PHY_AD_CSMA
; /* I am CSMA capable */
1205 if (my_phy_caps
& PHY_STAT_CAP_T4
)
1206 my_ad_caps
|= PHY_AD_T4
;
1208 if (my_phy_caps
& PHY_STAT_CAP_TXF
)
1209 my_ad_caps
|= PHY_AD_TX_FDX
;
1211 if (my_phy_caps
& PHY_STAT_CAP_TXH
)
1212 my_ad_caps
|= PHY_AD_TX_HDX
;
1214 if (my_phy_caps
& PHY_STAT_CAP_TF
)
1215 my_ad_caps
|= PHY_AD_10_FDX
;
1217 if (my_phy_caps
& PHY_STAT_CAP_TH
)
1218 my_ad_caps
|= PHY_AD_10_HDX
;
1220 /* Update our Auto-Neg Advertisement Register */
1221 smc_write_phy_register (dev
, PHY_AD_REG
, my_ad_caps
);
1223 /* Read the register back. Without this, it appears that when */
1224 /* auto-negotiation is restarted, sometimes it isn't ready and */
1225 /* the link does not come up. */
1226 smc_read_phy_register(dev
, PHY_AD_REG
);
1228 PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME
, my_phy_caps
);
1229 PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME
, my_ad_caps
);
1231 /* Restart auto-negotiation process in order to advertise my caps */
1232 smc_write_phy_register (dev
, PHY_CNTL_REG
,
1233 PHY_CNTL_ANEG_EN
| PHY_CNTL_ANEG_RST
);
1235 /* Wait for the auto-negotiation to complete. This may take from */
1236 /* 2 to 3 seconds. */
1237 /* Wait for the reset to complete, or time out */
1238 timeout
= CONFIG_SMC_AUTONEG_TIMEOUT
* 2;
1241 status
= smc_read_phy_register (dev
, PHY_STAT_REG
);
1242 if (status
& PHY_STAT_ANEG_ACK
) {
1243 /* auto-negotiate complete */
1247 mdelay(500); /* wait 500 millisecs */
1249 /* Restart auto-negotiation if remote fault */
1250 if (status
& PHY_STAT_REM_FLT
) {
1251 printf ("%s: PHY remote fault detected\n",
1254 /* Restart auto-negotiation */
1255 printf ("%s: PHY restarting auto-negotiation\n",
1257 smc_write_phy_register (dev
, PHY_CNTL_REG
,
1266 printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME
);
1269 /* Fail if we detected an auto-negotiate remote fault */
1270 if (status
& PHY_STAT_REM_FLT
) {
1271 printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME
);
1274 /* Re-Configure the Receive/Phy Control register */
1275 SMC_outw (dev
, RPC_DEFAULT
, RPC_REG
);
1277 smc_phy_configure_exit
: ;
1280 #endif /* !CONFIG_SMC91111_EXT_PHY */
1284 static void print_packet( byte
* buf
, int length
)
1290 printf("Packet of length %d \n", length
);
1293 lines
= length
/ 16;
1294 remainder
= length
% 16;
1296 for ( i
= 0; i
< lines
; i
++ ) {
1299 for ( cur
= 0; cur
< 8; cur
++ ) {
1304 printf("%02x%02x ", a
, b
);
1308 for ( i
= 0; i
< remainder
/2 ; i
++ ) {
1313 printf("%02x%02x ", a
, b
);
1320 int smc91111_initialize(u8 dev_num
, int base_addr
)
1322 struct smc91111_priv
*priv
;
1323 struct eth_device
*dev
;
1326 priv
= malloc(sizeof(*priv
));
1329 dev
= malloc(sizeof(*dev
));
1335 memset(dev
, 0, sizeof(*dev
));
1336 priv
->dev_num
= dev_num
;
1338 dev
->iobase
= base_addr
;
1341 SMC_SELECT_BANK(dev
, 1);
1342 for (i
= 0; i
< 6; ++i
)
1343 dev
->enetaddr
[i
] = SMC_inb(dev
, (ADDR0_REG
+ i
));
1346 dev
->init
= smc_init
;
1347 dev
->halt
= smc_halt
;
1348 dev
->send
= smc_send
;
1349 dev
->recv
= smc_rcv
;
1350 dev
->write_hwaddr
= smc_write_hwaddr
;
1351 sprintf(dev
->name
, "%s-%hu", SMC_DEV_NAME
, dev_num
);