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[thirdparty/u-boot.git] / drivers / net / sni_ave.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /**
3 * sni_ave.c - Socionext UniPhier AVE ethernet driver
4 * Copyright 2016-2018 Socionext inc.
5 */
6
7 #include <clk.h>
8 #include <cpu_func.h>
9 #include <dm.h>
10 #include <fdt_support.h>
11 #include <malloc.h>
12 #include <miiphy.h>
13 #include <net.h>
14 #include <regmap.h>
15 #include <reset.h>
16 #include <syscon.h>
17 #include <dm/device_compat.h>
18 #include <linux/err.h>
19 #include <linux/io.h>
20 #include <linux/iopoll.h>
21
22 #define AVE_GRST_DELAY_MSEC 40
23 #define AVE_MIN_XMITSIZE 60
24 #define AVE_SEND_TIMEOUT_COUNT 1000
25 #define AVE_MDIO_TIMEOUT_USEC 10000
26 #define AVE_HALT_TIMEOUT_USEC 10000
27
28 /* General Register Group */
29 #define AVE_IDR 0x000 /* ID */
30 #define AVE_VR 0x004 /* Version */
31 #define AVE_GRR 0x008 /* Global Reset */
32 #define AVE_CFGR 0x00c /* Configuration */
33
34 /* Interrupt Register Group */
35 #define AVE_GIMR 0x100 /* Global Interrupt Mask */
36 #define AVE_GISR 0x104 /* Global Interrupt Status */
37
38 /* MAC Register Group */
39 #define AVE_TXCR 0x200 /* TX Setup */
40 #define AVE_RXCR 0x204 /* RX Setup */
41 #define AVE_RXMAC1R 0x208 /* MAC address (lower) */
42 #define AVE_RXMAC2R 0x20c /* MAC address (upper) */
43 #define AVE_MDIOCTR 0x214 /* MDIO Control */
44 #define AVE_MDIOAR 0x218 /* MDIO Address */
45 #define AVE_MDIOWDR 0x21c /* MDIO Data */
46 #define AVE_MDIOSR 0x220 /* MDIO Status */
47 #define AVE_MDIORDR 0x224 /* MDIO Rd Data */
48
49 /* Descriptor Control Register Group */
50 #define AVE_DESCC 0x300 /* Descriptor Control */
51 #define AVE_TXDC 0x304 /* TX Descriptor Configuration */
52 #define AVE_RXDC 0x308 /* RX Descriptor Ring0 Configuration */
53 #define AVE_IIRQC 0x34c /* Interval IRQ Control */
54
55 /* 64bit descriptor memory */
56 #define AVE_DESC_SIZE_64 12 /* Descriptor Size */
57 #define AVE_TXDM_64 0x1000 /* Tx Descriptor Memory */
58 #define AVE_RXDM_64 0x1c00 /* Rx Descriptor Memory */
59
60 /* 32bit descriptor memory */
61 #define AVE_DESC_SIZE_32 8 /* Descriptor Size */
62 #define AVE_TXDM_32 0x1000 /* Tx Descriptor Memory */
63 #define AVE_RXDM_32 0x1800 /* Rx Descriptor Memory */
64
65 /* RMII Bridge Register Group */
66 #define AVE_RSTCTRL 0x8028 /* Reset control */
67 #define AVE_RSTCTRL_RMIIRST BIT(16)
68 #define AVE_LINKSEL 0x8034 /* Link speed setting */
69 #define AVE_LINKSEL_100M BIT(0)
70
71 /* AVE_GRR */
72 #define AVE_GRR_PHYRST BIT(4) /* Reset external PHY */
73 #define AVE_GRR_GRST BIT(0) /* Reset all MAC */
74
75 /* AVE_CFGR */
76 #define AVE_CFGR_MII BIT(27) /* Func mode (1:MII/RMII, 0:RGMII) */
77
78 /* AVE_GISR (common with GIMR) */
79 #define AVE_GIMR_CLR 0
80 #define AVE_GISR_CLR GENMASK(31, 0)
81
82 /* AVE_TXCR */
83 #define AVE_TXCR_FLOCTR BIT(18) /* Flow control */
84 #define AVE_TXCR_TXSPD_1G BIT(17)
85 #define AVE_TXCR_TXSPD_100 BIT(16)
86
87 /* AVE_RXCR */
88 #define AVE_RXCR_RXEN BIT(30) /* Rx enable */
89 #define AVE_RXCR_FDUPEN BIT(22) /* Interface mode */
90 #define AVE_RXCR_FLOCTR BIT(21) /* Flow control */
91
92 /* AVE_MDIOCTR */
93 #define AVE_MDIOCTR_RREQ BIT(3) /* Read request */
94 #define AVE_MDIOCTR_WREQ BIT(2) /* Write request */
95
96 /* AVE_MDIOSR */
97 #define AVE_MDIOSR_STS BIT(0) /* access status */
98
99 /* AVE_DESCC */
100 #define AVE_DESCC_RXDSTPSTS BIT(20)
101 #define AVE_DESCC_RD0 BIT(8) /* Enable Rx descriptor Ring0 */
102 #define AVE_DESCC_RXDSTP BIT(4) /* Pause Rx descriptor */
103 #define AVE_DESCC_TD BIT(0) /* Enable Tx descriptor */
104
105 /* AVE_TXDC/RXDC */
106 #define AVE_DESC_SIZE(priv, num) \
107 ((num) * ((priv)->data->is_desc_64bit ? AVE_DESC_SIZE_64 : \
108 AVE_DESC_SIZE_32))
109
110 /* Command status for descriptor */
111 #define AVE_STS_OWN BIT(31) /* Descriptor ownership */
112 #define AVE_STS_OK BIT(27) /* Normal transmit */
113 #define AVE_STS_1ST BIT(26) /* Head of buffer chain */
114 #define AVE_STS_LAST BIT(25) /* Tail of buffer chain */
115 #define AVE_STS_PKTLEN_TX_MASK GENMASK(15, 0)
116 #define AVE_STS_PKTLEN_RX_MASK GENMASK(10, 0)
117
118 #define AVE_DESC_OFS_CMDSTS 0
119 #define AVE_DESC_OFS_ADDRL 4
120 #define AVE_DESC_OFS_ADDRU 8
121
122 /* Parameter for ethernet frame */
123 #define AVE_RXCR_MTU 1518
124
125 /* SG */
126 #define SG_ETPINMODE 0x540
127 #define SG_ETPINMODE_EXTPHY BIT(1) /* for LD11 */
128 #define SG_ETPINMODE_RMII(ins) BIT(ins)
129
130 #define AVE_MAX_CLKS 4
131 #define AVE_MAX_RSTS 2
132
133 enum desc_id {
134 AVE_DESCID_TX,
135 AVE_DESCID_RX,
136 };
137
138 struct ave_private {
139 phys_addr_t iobase;
140 unsigned int nclks;
141 struct clk clk[AVE_MAX_CLKS];
142 unsigned int nrsts;
143 struct reset_ctl rst[AVE_MAX_RSTS];
144 struct regmap *regmap;
145 unsigned int regmap_arg;
146
147 struct mii_dev *bus;
148 struct phy_device *phydev;
149 int phy_mode;
150 int max_speed;
151
152 int rx_pos;
153 int rx_siz;
154 int rx_off;
155 int tx_num;
156
157 u8 tx_adj_packetbuf[PKTSIZE_ALIGN + PKTALIGN];
158 void *tx_adj_buf;
159
160 const struct ave_soc_data *data;
161 };
162
163 struct ave_soc_data {
164 bool is_desc_64bit;
165 const char *clock_names[AVE_MAX_CLKS];
166 const char *reset_names[AVE_MAX_RSTS];
167 int (*get_pinmode)(struct ave_private *priv);
168 };
169
170 static u32 ave_desc_read(struct ave_private *priv, enum desc_id id, int entry,
171 int offset)
172 {
173 int desc_size;
174 u32 addr;
175
176 if (priv->data->is_desc_64bit) {
177 desc_size = AVE_DESC_SIZE_64;
178 addr = (id == AVE_DESCID_TX) ? AVE_TXDM_64 : AVE_RXDM_64;
179 } else {
180 desc_size = AVE_DESC_SIZE_32;
181 addr = (id == AVE_DESCID_TX) ? AVE_TXDM_32 : AVE_RXDM_32;
182 }
183
184 addr += entry * desc_size + offset;
185
186 return readl(priv->iobase + addr);
187 }
188
189 static u32 ave_desc_read_cmdsts(struct ave_private *priv, enum desc_id id,
190 int entry)
191 {
192 return ave_desc_read(priv, id, entry, AVE_DESC_OFS_CMDSTS);
193 }
194
195 static void ave_desc_write(struct ave_private *priv, enum desc_id id,
196 int entry, int offset, u32 val)
197 {
198 int desc_size;
199 u32 addr;
200
201 if (priv->data->is_desc_64bit) {
202 desc_size = AVE_DESC_SIZE_64;
203 addr = (id == AVE_DESCID_TX) ? AVE_TXDM_64 : AVE_RXDM_64;
204 } else {
205 desc_size = AVE_DESC_SIZE_32;
206 addr = (id == AVE_DESCID_TX) ? AVE_TXDM_32 : AVE_RXDM_32;
207 }
208
209 addr += entry * desc_size + offset;
210 writel(val, priv->iobase + addr);
211 }
212
213 static void ave_desc_write_cmdsts(struct ave_private *priv, enum desc_id id,
214 int entry, u32 val)
215 {
216 ave_desc_write(priv, id, entry, AVE_DESC_OFS_CMDSTS, val);
217 }
218
219 static void ave_desc_write_addr(struct ave_private *priv, enum desc_id id,
220 int entry, uintptr_t paddr)
221 {
222 ave_desc_write(priv, id, entry,
223 AVE_DESC_OFS_ADDRL, lower_32_bits(paddr));
224 if (priv->data->is_desc_64bit)
225 ave_desc_write(priv, id, entry,
226 AVE_DESC_OFS_ADDRU, upper_32_bits(paddr));
227 }
228
229 static void ave_cache_invalidate(uintptr_t vaddr, int len)
230 {
231 invalidate_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN),
232 roundup(vaddr + len, ARCH_DMA_MINALIGN));
233 }
234
235 static void ave_cache_flush(uintptr_t vaddr, int len)
236 {
237 flush_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN),
238 roundup(vaddr + len, ARCH_DMA_MINALIGN));
239 }
240
241 static int ave_mdiobus_read(struct mii_dev *bus,
242 int phyid, int devad, int regnum)
243 {
244 struct ave_private *priv = bus->priv;
245 u32 mdioctl, mdiosr;
246 int ret;
247
248 /* write address */
249 writel((phyid << 8) | regnum, priv->iobase + AVE_MDIOAR);
250
251 /* read request */
252 mdioctl = readl(priv->iobase + AVE_MDIOCTR);
253 writel(mdioctl | AVE_MDIOCTR_RREQ, priv->iobase + AVE_MDIOCTR);
254
255 ret = readl_poll_timeout(priv->iobase + AVE_MDIOSR, mdiosr,
256 !(mdiosr & AVE_MDIOSR_STS),
257 AVE_MDIO_TIMEOUT_USEC);
258 if (ret) {
259 pr_err("%s: failed to read from mdio (phy:%d reg:%x)\n",
260 priv->phydev->dev->name, phyid, regnum);
261 return ret;
262 }
263
264 return readl(priv->iobase + AVE_MDIORDR) & GENMASK(15, 0);
265 }
266
267 static int ave_mdiobus_write(struct mii_dev *bus,
268 int phyid, int devad, int regnum, u16 val)
269 {
270 struct ave_private *priv = bus->priv;
271 u32 mdioctl, mdiosr;
272 int ret;
273
274 /* write address */
275 writel((phyid << 8) | regnum, priv->iobase + AVE_MDIOAR);
276
277 /* write data */
278 writel(val, priv->iobase + AVE_MDIOWDR);
279
280 /* write request */
281 mdioctl = readl(priv->iobase + AVE_MDIOCTR);
282 writel((mdioctl | AVE_MDIOCTR_WREQ) & ~AVE_MDIOCTR_RREQ,
283 priv->iobase + AVE_MDIOCTR);
284
285 ret = readl_poll_timeout(priv->iobase + AVE_MDIOSR, mdiosr,
286 !(mdiosr & AVE_MDIOSR_STS),
287 AVE_MDIO_TIMEOUT_USEC);
288 if (ret)
289 pr_err("%s: failed to write to mdio (phy:%d reg:%x)\n",
290 priv->phydev->dev->name, phyid, regnum);
291
292 return ret;
293 }
294
295 static int ave_adjust_link(struct ave_private *priv)
296 {
297 struct phy_device *phydev = priv->phydev;
298 struct eth_pdata *pdata = dev_get_platdata(phydev->dev);
299 u32 val, txcr, rxcr, rxcr_org;
300 u16 rmt_adv = 0, lcl_adv = 0;
301 u8 cap;
302
303 /* set RGMII speed */
304 val = readl(priv->iobase + AVE_TXCR);
305 val &= ~(AVE_TXCR_TXSPD_100 | AVE_TXCR_TXSPD_1G);
306
307 if (phy_interface_is_rgmii(phydev) && phydev->speed == SPEED_1000)
308 val |= AVE_TXCR_TXSPD_1G;
309 else if (phydev->speed == SPEED_100)
310 val |= AVE_TXCR_TXSPD_100;
311
312 writel(val, priv->iobase + AVE_TXCR);
313
314 /* set RMII speed (100M/10M only) */
315 if (!phy_interface_is_rgmii(phydev)) {
316 val = readl(priv->iobase + AVE_LINKSEL);
317 if (phydev->speed == SPEED_10)
318 val &= ~AVE_LINKSEL_100M;
319 else
320 val |= AVE_LINKSEL_100M;
321 writel(val, priv->iobase + AVE_LINKSEL);
322 }
323
324 /* check current RXCR/TXCR */
325 rxcr = readl(priv->iobase + AVE_RXCR);
326 txcr = readl(priv->iobase + AVE_TXCR);
327 rxcr_org = rxcr;
328
329 if (phydev->duplex) {
330 rxcr |= AVE_RXCR_FDUPEN;
331
332 if (phydev->pause)
333 rmt_adv |= LPA_PAUSE_CAP;
334 if (phydev->asym_pause)
335 rmt_adv |= LPA_PAUSE_ASYM;
336 if (phydev->advertising & ADVERTISED_Pause)
337 lcl_adv |= ADVERTISE_PAUSE_CAP;
338 if (phydev->advertising & ADVERTISED_Asym_Pause)
339 lcl_adv |= ADVERTISE_PAUSE_ASYM;
340
341 cap = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
342 if (cap & FLOW_CTRL_TX)
343 txcr |= AVE_TXCR_FLOCTR;
344 else
345 txcr &= ~AVE_TXCR_FLOCTR;
346 if (cap & FLOW_CTRL_RX)
347 rxcr |= AVE_RXCR_FLOCTR;
348 else
349 rxcr &= ~AVE_RXCR_FLOCTR;
350 } else {
351 rxcr &= ~AVE_RXCR_FDUPEN;
352 rxcr &= ~AVE_RXCR_FLOCTR;
353 txcr &= ~AVE_TXCR_FLOCTR;
354 }
355
356 if (rxcr_org != rxcr) {
357 /* disable Rx mac */
358 writel(rxcr & ~AVE_RXCR_RXEN, priv->iobase + AVE_RXCR);
359 /* change and enable TX/Rx mac */
360 writel(txcr, priv->iobase + AVE_TXCR);
361 writel(rxcr, priv->iobase + AVE_RXCR);
362 }
363
364 pr_notice("%s: phy:%s speed:%d mac:%pM\n",
365 phydev->dev->name, phydev->drv->name, phydev->speed,
366 pdata->enetaddr);
367
368 return phydev->link;
369 }
370
371 static int ave_mdiobus_init(struct ave_private *priv, const char *name)
372 {
373 struct mii_dev *bus = mdio_alloc();
374
375 if (!bus)
376 return -ENOMEM;
377
378 bus->read = ave_mdiobus_read;
379 bus->write = ave_mdiobus_write;
380 snprintf(bus->name, sizeof(bus->name), "%s", name);
381 bus->priv = priv;
382
383 return mdio_register(bus);
384 }
385
386 static int ave_phy_init(struct ave_private *priv, void *dev)
387 {
388 struct phy_device *phydev;
389 int mask = GENMASK(31, 0), ret;
390
391 phydev = phy_find_by_mask(priv->bus, mask, priv->phy_mode);
392 if (!phydev)
393 return -ENODEV;
394
395 phy_connect_dev(phydev, dev);
396
397 phydev->supported &= PHY_GBIT_FEATURES;
398 if (priv->max_speed) {
399 ret = phy_set_supported(phydev, priv->max_speed);
400 if (ret)
401 return ret;
402 }
403 phydev->advertising = phydev->supported;
404
405 priv->phydev = phydev;
406 phy_config(phydev);
407
408 return 0;
409 }
410
411 static void ave_stop(struct udevice *dev)
412 {
413 struct ave_private *priv = dev_get_priv(dev);
414 u32 val;
415 int ret;
416
417 val = readl(priv->iobase + AVE_GRR);
418 if (val)
419 return;
420
421 val = readl(priv->iobase + AVE_RXCR);
422 val &= ~AVE_RXCR_RXEN;
423 writel(val, priv->iobase + AVE_RXCR);
424
425 writel(0, priv->iobase + AVE_DESCC);
426 ret = readl_poll_timeout(priv->iobase + AVE_DESCC, val, !val,
427 AVE_HALT_TIMEOUT_USEC);
428 if (ret)
429 pr_warn("%s: halt timeout\n", priv->phydev->dev->name);
430
431 writel(AVE_GRR_GRST, priv->iobase + AVE_GRR);
432
433 phy_shutdown(priv->phydev);
434 }
435
436 static void ave_reset(struct ave_private *priv)
437 {
438 u32 val;
439
440 /* reset RMII register */
441 val = readl(priv->iobase + AVE_RSTCTRL);
442 val &= ~AVE_RSTCTRL_RMIIRST;
443 writel(val, priv->iobase + AVE_RSTCTRL);
444
445 /* assert reset */
446 writel(AVE_GRR_GRST | AVE_GRR_PHYRST, priv->iobase + AVE_GRR);
447 mdelay(AVE_GRST_DELAY_MSEC);
448
449 /* 1st, negate PHY reset only */
450 writel(AVE_GRR_GRST, priv->iobase + AVE_GRR);
451 mdelay(AVE_GRST_DELAY_MSEC);
452
453 /* negate reset */
454 writel(0, priv->iobase + AVE_GRR);
455 mdelay(AVE_GRST_DELAY_MSEC);
456
457 /* negate RMII register */
458 val = readl(priv->iobase + AVE_RSTCTRL);
459 val |= AVE_RSTCTRL_RMIIRST;
460 writel(val, priv->iobase + AVE_RSTCTRL);
461 }
462
463 static int ave_start(struct udevice *dev)
464 {
465 struct ave_private *priv = dev_get_priv(dev);
466 uintptr_t paddr;
467 u32 val;
468 int i;
469
470 ave_reset(priv);
471
472 priv->rx_pos = 0;
473 priv->rx_off = 2; /* RX data has 2byte offsets */
474 priv->tx_num = 0;
475 priv->tx_adj_buf =
476 (void *)roundup((uintptr_t)&priv->tx_adj_packetbuf[0],
477 PKTALIGN);
478 priv->rx_siz = (PKTSIZE_ALIGN - priv->rx_off);
479
480 val = 0;
481 if (priv->phy_mode != PHY_INTERFACE_MODE_RGMII)
482 val |= AVE_CFGR_MII;
483 writel(val, priv->iobase + AVE_CFGR);
484
485 /* use one descriptor for Tx */
486 writel(AVE_DESC_SIZE(priv, 1) << 16, priv->iobase + AVE_TXDC);
487 ave_desc_write_cmdsts(priv, AVE_DESCID_TX, 0, 0);
488 ave_desc_write_addr(priv, AVE_DESCID_TX, 0, 0);
489
490 /* use PKTBUFSRX descriptors for Rx */
491 writel(AVE_DESC_SIZE(priv, PKTBUFSRX) << 16, priv->iobase + AVE_RXDC);
492 for (i = 0; i < PKTBUFSRX; i++) {
493 paddr = (uintptr_t)net_rx_packets[i];
494 ave_cache_flush(paddr, priv->rx_siz + priv->rx_off);
495 ave_desc_write_addr(priv, AVE_DESCID_RX, i, paddr);
496 ave_desc_write_cmdsts(priv, AVE_DESCID_RX, i, priv->rx_siz);
497 }
498
499 writel(AVE_GISR_CLR, priv->iobase + AVE_GISR);
500 writel(AVE_GIMR_CLR, priv->iobase + AVE_GIMR);
501
502 writel(AVE_RXCR_RXEN | AVE_RXCR_FDUPEN | AVE_RXCR_FLOCTR | AVE_RXCR_MTU,
503 priv->iobase + AVE_RXCR);
504 writel(AVE_DESCC_RD0 | AVE_DESCC_TD, priv->iobase + AVE_DESCC);
505
506 phy_startup(priv->phydev);
507 ave_adjust_link(priv);
508
509 return 0;
510 }
511
512 static int ave_write_hwaddr(struct udevice *dev)
513 {
514 struct ave_private *priv = dev_get_priv(dev);
515 struct eth_pdata *pdata = dev_get_platdata(dev);
516 u8 *mac = pdata->enetaddr;
517
518 writel(mac[0] | mac[1] << 8 | mac[2] << 16 | mac[3] << 24,
519 priv->iobase + AVE_RXMAC1R);
520 writel(mac[4] | mac[5] << 8, priv->iobase + AVE_RXMAC2R);
521
522 return 0;
523 }
524
525 static int ave_send(struct udevice *dev, void *packet, int length)
526 {
527 struct ave_private *priv = dev_get_priv(dev);
528 u32 val;
529 void *ptr = packet;
530 int count;
531
532 /* adjust alignment for descriptor */
533 if ((uintptr_t)ptr & 0x3) {
534 memcpy(priv->tx_adj_buf, (const void *)ptr, length);
535 ptr = priv->tx_adj_buf;
536 }
537
538 /* padding for minimum length */
539 if (length < AVE_MIN_XMITSIZE) {
540 memset(ptr + length, 0, AVE_MIN_XMITSIZE - length);
541 length = AVE_MIN_XMITSIZE;
542 }
543
544 /* check ownership and wait for previous xmit done */
545 count = AVE_SEND_TIMEOUT_COUNT;
546 do {
547 val = ave_desc_read_cmdsts(priv, AVE_DESCID_TX, 0);
548 } while ((val & AVE_STS_OWN) && --count);
549 if (!count)
550 return -ETIMEDOUT;
551
552 ave_cache_flush((uintptr_t)ptr, length);
553 ave_desc_write_addr(priv, AVE_DESCID_TX, 0, (uintptr_t)ptr);
554
555 val = AVE_STS_OWN | AVE_STS_1ST | AVE_STS_LAST |
556 (length & AVE_STS_PKTLEN_TX_MASK);
557 ave_desc_write_cmdsts(priv, AVE_DESCID_TX, 0, val);
558 priv->tx_num++;
559
560 count = AVE_SEND_TIMEOUT_COUNT;
561 do {
562 val = ave_desc_read_cmdsts(priv, AVE_DESCID_TX, 0);
563 } while ((val & AVE_STS_OWN) && --count);
564 if (!count)
565 return -ETIMEDOUT;
566
567 if (!(val & AVE_STS_OK))
568 pr_warn("%s: bad send packet status:%08x\n",
569 priv->phydev->dev->name, le32_to_cpu(val));
570
571 return 0;
572 }
573
574 static int ave_recv(struct udevice *dev, int flags, uchar **packetp)
575 {
576 struct ave_private *priv = dev_get_priv(dev);
577 uchar *ptr;
578 int length = 0;
579 u32 cmdsts;
580
581 while (1) {
582 cmdsts = ave_desc_read_cmdsts(priv, AVE_DESCID_RX,
583 priv->rx_pos);
584 if (!(cmdsts & AVE_STS_OWN))
585 /* hardware ownership, no received packets */
586 return -EAGAIN;
587
588 ptr = net_rx_packets[priv->rx_pos] + priv->rx_off;
589 if (cmdsts & AVE_STS_OK)
590 break;
591
592 pr_warn("%s: bad packet[%d] status:%08x ptr:%p\n",
593 priv->phydev->dev->name, priv->rx_pos,
594 le32_to_cpu(cmdsts), ptr);
595 }
596
597 length = cmdsts & AVE_STS_PKTLEN_RX_MASK;
598
599 /* invalidate after DMA is done */
600 ave_cache_invalidate((uintptr_t)ptr, length);
601 *packetp = ptr;
602
603 return length;
604 }
605
606 static int ave_free_packet(struct udevice *dev, uchar *packet, int length)
607 {
608 struct ave_private *priv = dev_get_priv(dev);
609
610 ave_cache_flush((uintptr_t)net_rx_packets[priv->rx_pos],
611 priv->rx_siz + priv->rx_off);
612
613 ave_desc_write_cmdsts(priv, AVE_DESCID_RX,
614 priv->rx_pos, priv->rx_siz);
615
616 if (++priv->rx_pos >= PKTBUFSRX)
617 priv->rx_pos = 0;
618
619 return 0;
620 }
621
622 static int ave_pro4_get_pinmode(struct ave_private *priv)
623 {
624 u32 reg, mask, val = 0;
625
626 if (priv->regmap_arg > 0)
627 return -EINVAL;
628
629 mask = SG_ETPINMODE_RMII(0);
630
631 switch (priv->phy_mode) {
632 case PHY_INTERFACE_MODE_RMII:
633 val = SG_ETPINMODE_RMII(0);
634 break;
635 case PHY_INTERFACE_MODE_MII:
636 case PHY_INTERFACE_MODE_RGMII:
637 break;
638 default:
639 return -EINVAL;
640 }
641
642 regmap_read(priv->regmap, SG_ETPINMODE, &reg);
643 reg &= ~mask;
644 reg |= val;
645 regmap_write(priv->regmap, SG_ETPINMODE, reg);
646
647 return 0;
648 }
649
650 static int ave_ld11_get_pinmode(struct ave_private *priv)
651 {
652 u32 reg, mask, val = 0;
653
654 if (priv->regmap_arg > 0)
655 return -EINVAL;
656
657 mask = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0);
658
659 switch (priv->phy_mode) {
660 case PHY_INTERFACE_MODE_INTERNAL:
661 break;
662 case PHY_INTERFACE_MODE_RMII:
663 val = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0);
664 break;
665 default:
666 return -EINVAL;
667 }
668
669 regmap_read(priv->regmap, SG_ETPINMODE, &reg);
670 reg &= ~mask;
671 reg |= val;
672 regmap_write(priv->regmap, SG_ETPINMODE, reg);
673
674 return 0;
675 }
676
677 static int ave_ld20_get_pinmode(struct ave_private *priv)
678 {
679 u32 reg, mask, val = 0;
680
681 if (priv->regmap_arg > 0)
682 return -EINVAL;
683
684 mask = SG_ETPINMODE_RMII(0);
685
686 switch (priv->phy_mode) {
687 case PHY_INTERFACE_MODE_RMII:
688 val = SG_ETPINMODE_RMII(0);
689 break;
690 case PHY_INTERFACE_MODE_RGMII:
691 break;
692 default:
693 return -EINVAL;
694 }
695
696 regmap_read(priv->regmap, SG_ETPINMODE, &reg);
697 reg &= ~mask;
698 reg |= val;
699 regmap_write(priv->regmap, SG_ETPINMODE, reg);
700
701 return 0;
702 }
703
704 static int ave_pxs3_get_pinmode(struct ave_private *priv)
705 {
706 u32 reg, mask, val = 0;
707
708 if (priv->regmap_arg > 1)
709 return -EINVAL;
710
711 mask = SG_ETPINMODE_RMII(priv->regmap_arg);
712
713 switch (priv->phy_mode) {
714 case PHY_INTERFACE_MODE_RMII:
715 val = SG_ETPINMODE_RMII(priv->regmap_arg);
716 break;
717 case PHY_INTERFACE_MODE_RGMII:
718 break;
719 default:
720 return -EINVAL;
721 }
722
723 regmap_read(priv->regmap, SG_ETPINMODE, &reg);
724 reg &= ~mask;
725 reg |= val;
726 regmap_write(priv->regmap, SG_ETPINMODE, reg);
727
728 return 0;
729 }
730
731 static int ave_ofdata_to_platdata(struct udevice *dev)
732 {
733 struct eth_pdata *pdata = dev_get_platdata(dev);
734 struct ave_private *priv = dev_get_priv(dev);
735 struct ofnode_phandle_args args;
736 const char *phy_mode;
737 const u32 *valp;
738 int ret, nc, nr;
739 const char *name;
740
741 priv->data = (const struct ave_soc_data *)dev_get_driver_data(dev);
742 if (!priv->data)
743 return -EINVAL;
744
745 pdata->iobase = devfdt_get_addr(dev);
746 pdata->phy_interface = -1;
747 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
748 NULL);
749 if (phy_mode)
750 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
751 if (pdata->phy_interface == -1) {
752 dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode);
753 return -EINVAL;
754 }
755
756 pdata->max_speed = 0;
757 valp = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed",
758 NULL);
759 if (valp)
760 pdata->max_speed = fdt32_to_cpu(*valp);
761
762 for (nc = 0; nc < AVE_MAX_CLKS; nc++) {
763 name = priv->data->clock_names[nc];
764 if (!name)
765 break;
766 ret = clk_get_by_name(dev, name, &priv->clk[nc]);
767 if (ret) {
768 dev_err(dev, "Failed to get clocks property: %d\n",
769 ret);
770 goto out_clk_free;
771 }
772 priv->nclks++;
773 }
774
775 for (nr = 0; nr < AVE_MAX_RSTS; nr++) {
776 name = priv->data->reset_names[nr];
777 if (!name)
778 break;
779 ret = reset_get_by_name(dev, name, &priv->rst[nr]);
780 if (ret) {
781 dev_err(dev, "Failed to get resets property: %d\n",
782 ret);
783 goto out_reset_free;
784 }
785 priv->nrsts++;
786 }
787
788 ret = dev_read_phandle_with_args(dev, "socionext,syscon-phy-mode",
789 NULL, 1, 0, &args);
790 if (ret) {
791 dev_err(dev, "Failed to get syscon-phy-mode property: %d\n",
792 ret);
793 goto out_reset_free;
794 }
795
796 priv->regmap = syscon_node_to_regmap(args.node);
797 if (IS_ERR(priv->regmap)) {
798 ret = PTR_ERR(priv->regmap);
799 dev_err(dev, "can't get syscon: %d\n", ret);
800 goto out_reset_free;
801 }
802
803 if (args.args_count != 1) {
804 ret = -EINVAL;
805 dev_err(dev, "Invalid argument of syscon-phy-mode\n");
806 goto out_reset_free;
807 }
808
809 priv->regmap_arg = args.args[0];
810
811 return 0;
812
813 out_reset_free:
814 while (--nr >= 0)
815 reset_free(&priv->rst[nr]);
816 out_clk_free:
817 while (--nc >= 0)
818 clk_free(&priv->clk[nc]);
819
820 return ret;
821 }
822
823 static int ave_probe(struct udevice *dev)
824 {
825 struct eth_pdata *pdata = dev_get_platdata(dev);
826 struct ave_private *priv = dev_get_priv(dev);
827 int ret, nc, nr;
828
829 priv->data = (const struct ave_soc_data *)dev_get_driver_data(dev);
830 if (!priv->data)
831 return -EINVAL;
832
833 priv->iobase = pdata->iobase;
834 priv->phy_mode = pdata->phy_interface;
835 priv->max_speed = pdata->max_speed;
836
837 ret = priv->data->get_pinmode(priv);
838 if (ret) {
839 dev_err(dev, "Invalid phy-mode\n");
840 return -EINVAL;
841 }
842
843 for (nc = 0; nc < priv->nclks; nc++) {
844 ret = clk_enable(&priv->clk[nc]);
845 if (ret) {
846 dev_err(dev, "Failed to enable clk: %d\n", ret);
847 goto out_clk_release;
848 }
849 }
850
851 for (nr = 0; nr < priv->nrsts; nr++) {
852 ret = reset_deassert(&priv->rst[nr]);
853 if (ret) {
854 dev_err(dev, "Failed to deassert reset: %d\n", ret);
855 goto out_reset_release;
856 }
857 }
858
859 ave_reset(priv);
860
861 ret = ave_mdiobus_init(priv, dev->name);
862 if (ret) {
863 dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
864 goto out_reset_release;
865 }
866
867 priv->bus = miiphy_get_dev_by_name(dev->name);
868
869 ret = ave_phy_init(priv, dev);
870 if (ret) {
871 dev_err(dev, "Failed to initialize phy: %d\n", ret);
872 goto out_mdiobus_release;
873 }
874
875 return 0;
876
877 out_mdiobus_release:
878 mdio_unregister(priv->bus);
879 mdio_free(priv->bus);
880 out_reset_release:
881 reset_release_all(priv->rst, nr);
882 out_clk_release:
883 clk_release_all(priv->clk, nc);
884
885 return ret;
886 }
887
888 static int ave_remove(struct udevice *dev)
889 {
890 struct ave_private *priv = dev_get_priv(dev);
891
892 free(priv->phydev);
893 mdio_unregister(priv->bus);
894 mdio_free(priv->bus);
895 reset_release_all(priv->rst, priv->nrsts);
896 clk_release_all(priv->clk, priv->nclks);
897
898 return 0;
899 }
900
901 static const struct eth_ops ave_ops = {
902 .start = ave_start,
903 .stop = ave_stop,
904 .send = ave_send,
905 .recv = ave_recv,
906 .free_pkt = ave_free_packet,
907 .write_hwaddr = ave_write_hwaddr,
908 };
909
910 static const struct ave_soc_data ave_pro4_data = {
911 .is_desc_64bit = false,
912 .clock_names = {
913 "gio", "ether", "ether-gb", "ether-phy",
914 },
915 .reset_names = {
916 "gio", "ether",
917 },
918 .get_pinmode = ave_pro4_get_pinmode,
919 };
920
921 static const struct ave_soc_data ave_pxs2_data = {
922 .is_desc_64bit = false,
923 .clock_names = {
924 "ether",
925 },
926 .reset_names = {
927 "ether",
928 },
929 .get_pinmode = ave_pro4_get_pinmode,
930 };
931
932 static const struct ave_soc_data ave_ld11_data = {
933 .is_desc_64bit = false,
934 .clock_names = {
935 "ether",
936 },
937 .reset_names = {
938 "ether",
939 },
940 .get_pinmode = ave_ld11_get_pinmode,
941 };
942
943 static const struct ave_soc_data ave_ld20_data = {
944 .is_desc_64bit = true,
945 .clock_names = {
946 "ether",
947 },
948 .reset_names = {
949 "ether",
950 },
951 .get_pinmode = ave_ld20_get_pinmode,
952 };
953
954 static const struct ave_soc_data ave_pxs3_data = {
955 .is_desc_64bit = false,
956 .clock_names = {
957 "ether",
958 },
959 .reset_names = {
960 "ether",
961 },
962 .get_pinmode = ave_pxs3_get_pinmode,
963 };
964
965 static const struct udevice_id ave_ids[] = {
966 {
967 .compatible = "socionext,uniphier-pro4-ave4",
968 .data = (ulong)&ave_pro4_data,
969 },
970 {
971 .compatible = "socionext,uniphier-pxs2-ave4",
972 .data = (ulong)&ave_pxs2_data,
973 },
974 {
975 .compatible = "socionext,uniphier-ld11-ave4",
976 .data = (ulong)&ave_ld11_data,
977 },
978 {
979 .compatible = "socionext,uniphier-ld20-ave4",
980 .data = (ulong)&ave_ld20_data,
981 },
982 {
983 .compatible = "socionext,uniphier-pxs3-ave4",
984 .data = (ulong)&ave_pxs3_data,
985 },
986 { /* Sentinel */ }
987 };
988
989 U_BOOT_DRIVER(ave) = {
990 .name = "ave",
991 .id = UCLASS_ETH,
992 .of_match = ave_ids,
993 .probe = ave_probe,
994 .remove = ave_remove,
995 .ofdata_to_platdata = ave_ofdata_to_platdata,
996 .ops = &ave_ops,
997 .priv_auto_alloc_size = sizeof(struct ave_private),
998 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
999 };
"Das U-Boot" Source Tree