3 * Author: Amit Singh Tomar, amittomer25@gmail.com
5 * SPDX-License-Identifier: GPL-2.0+
7 * Ethernet driver for H3/A64/A83T based SoC's
9 * It is derived from the work done by
10 * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!
15 #include <asm/arch/clock.h>
16 #include <asm/arch/gpio.h>
19 #include <fdt_support.h>
20 #include <linux/err.h>
25 #include <asm-generic/gpio.h>
28 #define MDIO_CMD_MII_BUSY BIT(0)
29 #define MDIO_CMD_MII_WRITE BIT(1)
31 #define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0
32 #define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4
33 #define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000
34 #define MDIO_CMD_MII_PHY_ADDR_SHIFT 12
36 #define CONFIG_TX_DESCR_NUM 32
37 #define CONFIG_RX_DESCR_NUM 32
38 #define CONFIG_ETH_BUFSIZE 2048 /* Note must be dma aligned */
41 * The datasheet says that each descriptor can transfers up to 4096 bytes
42 * But later, the register documentation reduces that value to 2048,
43 * using 2048 cause strange behaviours and even BSP driver use 2047
45 #define CONFIG_ETH_RXSIZE 2044 /* Note must fit in ETH_BUFSIZE */
47 #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
48 #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
50 #define H3_EPHY_DEFAULT_VALUE 0x58000
51 #define H3_EPHY_DEFAULT_MASK GENMASK(31, 15)
52 #define H3_EPHY_ADDR_SHIFT 20
53 #define REG_PHY_ADDR_MASK GENMASK(4, 0)
54 #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
55 #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
56 #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
58 #define SC_RMII_EN BIT(13)
59 #define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */
60 #define SC_ETCS_MASK GENMASK(1, 0)
61 #define SC_ETCS_EXT_GMII 0x1
62 #define SC_ETCS_INT_GMII 0x2
64 #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
66 #define AHB_GATE_OFFSET_EPHY 0
68 #if defined(CONFIG_MACH_SUNXI_H3_H5)
69 #define SUN8I_GPD8_GMAC 2
71 #define SUN8I_GPD8_GMAC 4
74 /* H3/A64 EMAC Register's offset */
75 #define EMAC_CTL0 0x00
76 #define EMAC_CTL1 0x04
77 #define EMAC_INT_STA 0x08
78 #define EMAC_INT_EN 0x0c
79 #define EMAC_TX_CTL0 0x10
80 #define EMAC_TX_CTL1 0x14
81 #define EMAC_TX_FLOW_CTL 0x1c
82 #define EMAC_TX_DMA_DESC 0x20
83 #define EMAC_RX_CTL0 0x24
84 #define EMAC_RX_CTL1 0x28
85 #define EMAC_RX_DMA_DESC 0x34
86 #define EMAC_MII_CMD 0x48
87 #define EMAC_MII_DATA 0x4c
88 #define EMAC_ADDR0_HIGH 0x50
89 #define EMAC_ADDR0_LOW 0x54
90 #define EMAC_TX_DMA_STA 0xb0
91 #define EMAC_TX_CUR_DESC 0xb4
92 #define EMAC_TX_CUR_BUF 0xb8
93 #define EMAC_RX_DMA_STA 0xc0
94 #define EMAC_RX_CUR_DESC 0xc4
96 DECLARE_GLOBAL_DATA_PTR
;
104 struct emac_dma_desc
{
109 } __aligned(ARCH_DMA_MINALIGN
);
111 struct emac_eth_dev
{
112 struct emac_dma_desc rx_chain
[CONFIG_TX_DESCR_NUM
];
113 struct emac_dma_desc tx_chain
[CONFIG_RX_DESCR_NUM
];
114 char rxbuffer
[RX_TOTAL_BUFSIZE
] __aligned(ARCH_DMA_MINALIGN
);
115 char txbuffer
[TX_TOTAL_BUFSIZE
] __aligned(ARCH_DMA_MINALIGN
);
127 bool use_internal_phy
;
129 enum emac_variant variant
;
131 phys_addr_t sysctl_reg
;
132 struct phy_device
*phydev
;
134 #ifdef CONFIG_DM_GPIO
135 struct gpio_desc reset_gpio
;
140 struct sun8i_eth_pdata
{
141 struct eth_pdata eth_pdata
;
146 static int sun8i_mdio_read(struct mii_dev
*bus
, int addr
, int devad
, int reg
)
148 struct udevice
*dev
= bus
->priv
;
149 struct emac_eth_dev
*priv
= dev_get_priv(dev
);
152 int timeout
= CONFIG_MDIO_TIMEOUT
;
154 miiaddr
&= ~MDIO_CMD_MII_WRITE
;
155 miiaddr
&= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK
;
156 miiaddr
|= (reg
<< MDIO_CMD_MII_PHY_REG_ADDR_SHIFT
) &
157 MDIO_CMD_MII_PHY_REG_ADDR_MASK
;
159 miiaddr
&= ~MDIO_CMD_MII_PHY_ADDR_MASK
;
161 miiaddr
|= (addr
<< MDIO_CMD_MII_PHY_ADDR_SHIFT
) &
162 MDIO_CMD_MII_PHY_ADDR_MASK
;
164 miiaddr
|= MDIO_CMD_MII_BUSY
;
166 writel(miiaddr
, priv
->mac_reg
+ EMAC_MII_CMD
);
168 start
= get_timer(0);
169 while (get_timer(start
) < timeout
) {
170 if (!(readl(priv
->mac_reg
+ EMAC_MII_CMD
) & MDIO_CMD_MII_BUSY
))
171 return readl(priv
->mac_reg
+ EMAC_MII_DATA
);
178 static int sun8i_mdio_write(struct mii_dev
*bus
, int addr
, int devad
, int reg
,
181 struct udevice
*dev
= bus
->priv
;
182 struct emac_eth_dev
*priv
= dev_get_priv(dev
);
185 int ret
= -1, timeout
= CONFIG_MDIO_TIMEOUT
;
187 miiaddr
&= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK
;
188 miiaddr
|= (reg
<< MDIO_CMD_MII_PHY_REG_ADDR_SHIFT
) &
189 MDIO_CMD_MII_PHY_REG_ADDR_MASK
;
191 miiaddr
&= ~MDIO_CMD_MII_PHY_ADDR_MASK
;
192 miiaddr
|= (addr
<< MDIO_CMD_MII_PHY_ADDR_SHIFT
) &
193 MDIO_CMD_MII_PHY_ADDR_MASK
;
195 miiaddr
|= MDIO_CMD_MII_WRITE
;
196 miiaddr
|= MDIO_CMD_MII_BUSY
;
198 writel(val
, priv
->mac_reg
+ EMAC_MII_DATA
);
199 writel(miiaddr
, priv
->mac_reg
+ EMAC_MII_CMD
);
201 start
= get_timer(0);
202 while (get_timer(start
) < timeout
) {
203 if (!(readl(priv
->mac_reg
+ EMAC_MII_CMD
) &
204 MDIO_CMD_MII_BUSY
)) {
214 static int _sun8i_write_hwaddr(struct emac_eth_dev
*priv
, u8
*mac_id
)
216 u32 macid_lo
, macid_hi
;
218 macid_lo
= mac_id
[0] + (mac_id
[1] << 8) + (mac_id
[2] << 16) +
220 macid_hi
= mac_id
[4] + (mac_id
[5] << 8);
222 writel(macid_hi
, priv
->mac_reg
+ EMAC_ADDR0_HIGH
);
223 writel(macid_lo
, priv
->mac_reg
+ EMAC_ADDR0_LOW
);
228 static void sun8i_adjust_link(struct emac_eth_dev
*priv
,
229 struct phy_device
*phydev
)
233 v
= readl(priv
->mac_reg
+ EMAC_CTL0
);
242 switch (phydev
->speed
) {
253 writel(v
, priv
->mac_reg
+ EMAC_CTL0
);
256 static int sun8i_emac_set_syscon_ephy(struct emac_eth_dev
*priv
, u32
*reg
)
258 if (priv
->use_internal_phy
) {
259 /* H3 based SoC's that has an Internal 100MBit PHY
260 * needs to be configured and powered up before use
262 *reg
&= ~H3_EPHY_DEFAULT_MASK
;
263 *reg
|= H3_EPHY_DEFAULT_VALUE
;
264 *reg
|= priv
->phyaddr
<< H3_EPHY_ADDR_SHIFT
;
265 *reg
&= ~H3_EPHY_SHUTDOWN
;
266 *reg
|= H3_EPHY_SELECT
;
268 /* This is to select External Gigabit PHY on
269 * the boards with H3 SoC.
271 *reg
&= ~H3_EPHY_SELECT
;
276 static int sun8i_emac_set_syscon(struct emac_eth_dev
*priv
)
281 reg
= readl(priv
->sysctl_reg
);
283 if (priv
->variant
== H3_EMAC
) {
284 ret
= sun8i_emac_set_syscon_ephy(priv
, ®
);
289 reg
&= ~(SC_ETCS_MASK
| SC_EPIT
);
290 if (priv
->variant
== H3_EMAC
|| priv
->variant
== A64_EMAC
)
293 switch (priv
->interface
) {
294 case PHY_INTERFACE_MODE_MII
:
297 case PHY_INTERFACE_MODE_RGMII
:
298 reg
|= SC_EPIT
| SC_ETCS_INT_GMII
;
300 case PHY_INTERFACE_MODE_RMII
:
301 if (priv
->variant
== H3_EMAC
||
302 priv
->variant
== A64_EMAC
) {
303 reg
|= SC_RMII_EN
| SC_ETCS_EXT_GMII
;
306 /* RMII not supported on A83T */
308 debug("%s: Invalid PHY interface\n", __func__
);
312 writel(reg
, priv
->sysctl_reg
);
317 static int sun8i_phy_init(struct emac_eth_dev
*priv
, void *dev
)
319 struct phy_device
*phydev
;
321 phydev
= phy_connect(priv
->bus
, priv
->phyaddr
, dev
, priv
->interface
);
325 phy_connect_dev(phydev
, dev
);
327 priv
->phydev
= phydev
;
328 phy_config(priv
->phydev
);
333 static void rx_descs_init(struct emac_eth_dev
*priv
)
335 struct emac_dma_desc
*desc_table_p
= &priv
->rx_chain
[0];
336 char *rxbuffs
= &priv
->rxbuffer
[0];
337 struct emac_dma_desc
*desc_p
;
340 /* flush Rx buffers */
341 flush_dcache_range((uintptr_t)rxbuffs
, (ulong
)rxbuffs
+
344 for (idx
= 0; idx
< CONFIG_RX_DESCR_NUM
; idx
++) {
345 desc_p
= &desc_table_p
[idx
];
346 desc_p
->buf_addr
= (uintptr_t)&rxbuffs
[idx
* CONFIG_ETH_BUFSIZE
]
348 desc_p
->next
= (uintptr_t)&desc_table_p
[idx
+ 1];
349 desc_p
->st
|= CONFIG_ETH_RXSIZE
;
350 desc_p
->status
= BIT(31);
353 /* Correcting the last pointer of the chain */
354 desc_p
->next
= (uintptr_t)&desc_table_p
[0];
356 flush_dcache_range((uintptr_t)priv
->rx_chain
,
357 (uintptr_t)priv
->rx_chain
+
358 sizeof(priv
->rx_chain
));
360 writel((uintptr_t)&desc_table_p
[0], (priv
->mac_reg
+ EMAC_RX_DMA_DESC
));
361 priv
->rx_currdescnum
= 0;
364 static void tx_descs_init(struct emac_eth_dev
*priv
)
366 struct emac_dma_desc
*desc_table_p
= &priv
->tx_chain
[0];
367 char *txbuffs
= &priv
->txbuffer
[0];
368 struct emac_dma_desc
*desc_p
;
371 for (idx
= 0; idx
< CONFIG_TX_DESCR_NUM
; idx
++) {
372 desc_p
= &desc_table_p
[idx
];
373 desc_p
->buf_addr
= (uintptr_t)&txbuffs
[idx
* CONFIG_ETH_BUFSIZE
]
375 desc_p
->next
= (uintptr_t)&desc_table_p
[idx
+ 1];
376 desc_p
->status
= (1 << 31);
380 /* Correcting the last pointer of the chain */
381 desc_p
->next
= (uintptr_t)&desc_table_p
[0];
383 /* Flush all Tx buffer descriptors */
384 flush_dcache_range((uintptr_t)priv
->tx_chain
,
385 (uintptr_t)priv
->tx_chain
+
386 sizeof(priv
->tx_chain
));
388 writel((uintptr_t)&desc_table_p
[0], priv
->mac_reg
+ EMAC_TX_DMA_DESC
);
389 priv
->tx_currdescnum
= 0;
392 static int _sun8i_emac_eth_init(struct emac_eth_dev
*priv
, u8
*enetaddr
)
397 reg
= readl((priv
->mac_reg
+ EMAC_CTL1
));
401 setbits_le32((priv
->mac_reg
+ EMAC_CTL1
), 0x1);
403 reg
= readl(priv
->mac_reg
+ EMAC_CTL1
);
404 } while ((reg
& 0x01) != 0 && (--timeout
));
406 printf("%s: Timeout\n", __func__
);
411 /* Rewrite mac address after reset */
412 _sun8i_write_hwaddr(priv
, enetaddr
);
414 v
= readl(priv
->mac_reg
+ EMAC_TX_CTL1
);
415 /* TX_MD Transmission starts after a full frame located in TX DMA FIFO*/
417 writel(v
, priv
->mac_reg
+ EMAC_TX_CTL1
);
419 v
= readl(priv
->mac_reg
+ EMAC_RX_CTL1
);
420 /* RX_MD RX DMA reads data from RX DMA FIFO to host memory after a
421 * complete frame has been written to RX DMA FIFO
424 writel(v
, priv
->mac_reg
+ EMAC_RX_CTL1
);
427 writel(8 << 24, priv
->mac_reg
+ EMAC_CTL1
);
429 /* Initialize rx/tx descriptors */
434 genphy_parse_link(priv
->phydev
);
436 sun8i_adjust_link(priv
, priv
->phydev
);
439 v
= readl(priv
->mac_reg
+ EMAC_RX_CTL1
);
441 writel(v
, priv
->mac_reg
+ EMAC_RX_CTL1
);
443 v
= readl(priv
->mac_reg
+ EMAC_TX_CTL1
);
445 writel(v
, priv
->mac_reg
+ EMAC_TX_CTL1
);
448 setbits_le32(priv
->mac_reg
+ EMAC_RX_CTL0
, BIT(31));
449 setbits_le32(priv
->mac_reg
+ EMAC_TX_CTL0
, BIT(31));
454 static int parse_phy_pins(struct udevice
*dev
)
457 const char *pin_name
;
460 offset
= fdtdec_lookup_phandle(gd
->fdt_blob
, dev_of_offset(dev
),
463 printf("WARNING: emac: cannot find pinctrl-0 node\n");
467 drive
= fdt_getprop_u32_default_node(gd
->fdt_blob
, offset
, 0,
468 "allwinner,drive", 4);
469 pull
= fdt_getprop_u32_default_node(gd
->fdt_blob
, offset
, 0,
470 "allwinner,pull", 0);
474 pin_name
= fdt_stringlist_get(gd
->fdt_blob
, offset
,
475 "allwinner,pins", i
, NULL
);
478 if (pin_name
[0] != 'P')
480 pin
= (pin_name
[1] - 'A') << 5;
483 pin
+= simple_strtol(&pin_name
[2], NULL
, 10);
485 sunxi_gpio_set_cfgpin(pin
, SUN8I_GPD8_GMAC
);
486 sunxi_gpio_set_drv(pin
, drive
);
487 sunxi_gpio_set_pull(pin
, pull
);
491 printf("WARNING: emac: cannot find allwinner,pins property\n");
498 static int _sun8i_eth_recv(struct emac_eth_dev
*priv
, uchar
**packetp
)
500 u32 status
, desc_num
= priv
->rx_currdescnum
;
501 struct emac_dma_desc
*desc_p
= &priv
->rx_chain
[desc_num
];
502 int length
= -EAGAIN
;
504 uintptr_t desc_start
= (uintptr_t)desc_p
;
505 uintptr_t desc_end
= desc_start
+
506 roundup(sizeof(*desc_p
), ARCH_DMA_MINALIGN
);
508 ulong data_start
= (uintptr_t)desc_p
->buf_addr
;
511 /* Invalidate entire buffer descriptor */
512 invalidate_dcache_range(desc_start
, desc_end
);
514 status
= desc_p
->status
;
516 /* Check for DMA own bit */
517 if (!(status
& BIT(31))) {
518 length
= (desc_p
->status
>> 16) & 0x3FFF;
522 debug("RX: Bad Packet (runt)\n");
525 data_end
= data_start
+ length
;
526 /* Invalidate received data */
527 invalidate_dcache_range(rounddown(data_start
,
532 if (length
> CONFIG_ETH_RXSIZE
) {
533 printf("Received packet is too big (len=%d)\n",
537 *packetp
= (uchar
*)(ulong
)desc_p
->buf_addr
;
545 static int _sun8i_emac_eth_send(struct emac_eth_dev
*priv
, void *packet
,
548 u32 v
, desc_num
= priv
->tx_currdescnum
;
549 struct emac_dma_desc
*desc_p
= &priv
->tx_chain
[desc_num
];
550 uintptr_t desc_start
= (uintptr_t)desc_p
;
551 uintptr_t desc_end
= desc_start
+
552 roundup(sizeof(*desc_p
), ARCH_DMA_MINALIGN
);
554 uintptr_t data_start
= (uintptr_t)desc_p
->buf_addr
;
555 uintptr_t data_end
= data_start
+
556 roundup(len
, ARCH_DMA_MINALIGN
);
558 /* Invalidate entire buffer descriptor */
559 invalidate_dcache_range(desc_start
, desc_end
);
562 /* Mandatory undocumented bit */
563 desc_p
->st
|= BIT(24);
565 memcpy((void *)data_start
, packet
, len
);
567 /* Flush data to be sent */
568 flush_dcache_range(data_start
, data_end
);
571 desc_p
->st
|= BIT(30);
572 desc_p
->st
|= BIT(31);
575 desc_p
->st
|= BIT(29);
576 desc_p
->status
= BIT(31);
578 /*Descriptors st and status field has changed, so FLUSH it */
579 flush_dcache_range(desc_start
, desc_end
);
581 /* Move to next Descriptor and wrap around */
582 if (++desc_num
>= CONFIG_TX_DESCR_NUM
)
584 priv
->tx_currdescnum
= desc_num
;
587 v
= readl(priv
->mac_reg
+ EMAC_TX_CTL1
);
588 v
|= BIT(31);/* mandatory */
589 v
|= BIT(30);/* mandatory */
590 writel(v
, priv
->mac_reg
+ EMAC_TX_CTL1
);
595 static int sun8i_eth_write_hwaddr(struct udevice
*dev
)
597 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
598 struct emac_eth_dev
*priv
= dev_get_priv(dev
);
600 return _sun8i_write_hwaddr(priv
, pdata
->enetaddr
);
603 static void sun8i_emac_board_setup(struct emac_eth_dev
*priv
)
605 struct sunxi_ccm_reg
*ccm
= (struct sunxi_ccm_reg
*)SUNXI_CCM_BASE
;
607 #ifdef CONFIG_MACH_SUNXI_H3_H5
608 /* Only H3/H5 have clock controls for internal EPHY */
609 if (priv
->use_internal_phy
) {
610 /* Set clock gating for ephy */
611 setbits_le32(&ccm
->bus_gate4
, BIT(AHB_GATE_OFFSET_EPHY
));
614 setbits_le32(&ccm
->ahb_reset2_cfg
, BIT(AHB_RESET_OFFSET_EPHY
));
618 /* Set clock gating for emac */
619 setbits_le32(&ccm
->ahb_gate0
, BIT(AHB_GATE_OFFSET_GMAC
));
622 setbits_le32(&ccm
->ahb_reset0_cfg
, BIT(AHB_RESET_OFFSET_GMAC
));
625 #if defined(CONFIG_DM_GPIO)
626 static int sun8i_mdio_reset(struct mii_dev
*bus
)
628 struct udevice
*dev
= bus
->priv
;
629 struct emac_eth_dev
*priv
= dev_get_priv(dev
);
630 struct sun8i_eth_pdata
*pdata
= dev_get_platdata(dev
);
633 if (!dm_gpio_is_valid(&priv
->reset_gpio
))
637 ret
= dm_gpio_set_value(&priv
->reset_gpio
, 0);
641 udelay(pdata
->reset_delays
[0]);
643 ret
= dm_gpio_set_value(&priv
->reset_gpio
, 1);
647 udelay(pdata
->reset_delays
[1]);
649 ret
= dm_gpio_set_value(&priv
->reset_gpio
, 0);
653 udelay(pdata
->reset_delays
[2]);
659 static int sun8i_mdio_init(const char *name
, struct udevice
*priv
)
661 struct mii_dev
*bus
= mdio_alloc();
664 debug("Failed to allocate MDIO bus\n");
668 bus
->read
= sun8i_mdio_read
;
669 bus
->write
= sun8i_mdio_write
;
670 snprintf(bus
->name
, sizeof(bus
->name
), name
);
671 bus
->priv
= (void *)priv
;
672 #if defined(CONFIG_DM_GPIO)
673 bus
->reset
= sun8i_mdio_reset
;
676 return mdio_register(bus
);
679 static int sun8i_emac_eth_start(struct udevice
*dev
)
681 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
683 return _sun8i_emac_eth_init(dev
->priv
, pdata
->enetaddr
);
686 static int sun8i_emac_eth_send(struct udevice
*dev
, void *packet
, int length
)
688 struct emac_eth_dev
*priv
= dev_get_priv(dev
);
690 return _sun8i_emac_eth_send(priv
, packet
, length
);
693 static int sun8i_emac_eth_recv(struct udevice
*dev
, int flags
, uchar
**packetp
)
695 struct emac_eth_dev
*priv
= dev_get_priv(dev
);
697 return _sun8i_eth_recv(priv
, packetp
);
700 static int _sun8i_free_pkt(struct emac_eth_dev
*priv
)
702 u32 desc_num
= priv
->rx_currdescnum
;
703 struct emac_dma_desc
*desc_p
= &priv
->rx_chain
[desc_num
];
704 uintptr_t desc_start
= (uintptr_t)desc_p
;
705 uintptr_t desc_end
= desc_start
+
706 roundup(sizeof(u32
), ARCH_DMA_MINALIGN
);
708 /* Make the current descriptor valid again */
709 desc_p
->status
|= BIT(31);
711 /* Flush Status field of descriptor */
712 flush_dcache_range(desc_start
, desc_end
);
714 /* Move to next desc and wrap-around condition. */
715 if (++desc_num
>= CONFIG_RX_DESCR_NUM
)
717 priv
->rx_currdescnum
= desc_num
;
722 static int sun8i_eth_free_pkt(struct udevice
*dev
, uchar
*packet
,
725 struct emac_eth_dev
*priv
= dev_get_priv(dev
);
727 return _sun8i_free_pkt(priv
);
730 static void sun8i_emac_eth_stop(struct udevice
*dev
)
732 struct emac_eth_dev
*priv
= dev_get_priv(dev
);
734 /* Stop Rx/Tx transmitter */
735 clrbits_le32(priv
->mac_reg
+ EMAC_RX_CTL0
, BIT(31));
736 clrbits_le32(priv
->mac_reg
+ EMAC_TX_CTL0
, BIT(31));
739 clrbits_le32(priv
->mac_reg
+ EMAC_TX_CTL1
, BIT(30));
741 phy_shutdown(priv
->phydev
);
744 static int sun8i_emac_eth_probe(struct udevice
*dev
)
746 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
747 struct emac_eth_dev
*priv
= dev_get_priv(dev
);
749 priv
->mac_reg
= (void *)pdata
->iobase
;
751 sun8i_emac_board_setup(priv
);
752 sun8i_emac_set_syscon(priv
);
754 sun8i_mdio_init(dev
->name
, dev
);
755 priv
->bus
= miiphy_get_dev_by_name(dev
->name
);
757 return sun8i_phy_init(priv
, dev
);
760 static const struct eth_ops sun8i_emac_eth_ops
= {
761 .start
= sun8i_emac_eth_start
,
762 .write_hwaddr
= sun8i_eth_write_hwaddr
,
763 .send
= sun8i_emac_eth_send
,
764 .recv
= sun8i_emac_eth_recv
,
765 .free_pkt
= sun8i_eth_free_pkt
,
766 .stop
= sun8i_emac_eth_stop
,
769 static int sun8i_emac_eth_ofdata_to_platdata(struct udevice
*dev
)
771 struct sun8i_eth_pdata
*sun8i_pdata
= dev_get_platdata(dev
);
772 struct eth_pdata
*pdata
= &sun8i_pdata
->eth_pdata
;
773 struct emac_eth_dev
*priv
= dev_get_priv(dev
);
774 const char *phy_mode
;
775 int node
= dev_of_offset(dev
);
777 #ifdef CONFIG_DM_GPIO
778 int reset_flags
= GPIOD_IS_OUT
;
782 pdata
->iobase
= devfdt_get_addr_name(dev
, "emac");
783 priv
->sysctl_reg
= devfdt_get_addr_name(dev
, "syscon");
785 pdata
->phy_interface
= -1;
787 priv
->use_internal_phy
= false;
789 offset
= fdtdec_lookup_phandle(gd
->fdt_blob
, node
,
792 priv
->phyaddr
= fdtdec_get_int(gd
->fdt_blob
, offset
, "reg",
795 phy_mode
= fdt_getprop(gd
->fdt_blob
, node
, "phy-mode", NULL
);
798 pdata
->phy_interface
= phy_get_interface_by_name(phy_mode
);
799 printf("phy interface%d\n", pdata
->phy_interface
);
801 if (pdata
->phy_interface
== -1) {
802 debug("%s: Invalid PHY interface '%s'\n", __func__
, phy_mode
);
806 priv
->variant
= dev_get_driver_data(dev
);
808 if (!priv
->variant
) {
809 printf("%s: Missing variant '%s'\n", __func__
,
810 (char *)priv
->variant
);
814 if (priv
->variant
== H3_EMAC
) {
815 if (fdt_getprop(gd
->fdt_blob
, node
,
816 "allwinner,use-internal-phy", NULL
))
817 priv
->use_internal_phy
= true;
820 priv
->interface
= pdata
->phy_interface
;
822 if (!priv
->use_internal_phy
)
825 #ifdef CONFIG_DM_GPIO
826 if (fdtdec_get_bool(gd
->fdt_blob
, dev_of_offset(dev
),
827 "snps,reset-active-low"))
828 reset_flags
|= GPIOD_ACTIVE_LOW
;
830 ret
= gpio_request_by_name(dev
, "snps,reset-gpio", 0,
831 &priv
->reset_gpio
, reset_flags
);
834 ret
= fdtdec_get_int_array(gd
->fdt_blob
, dev_of_offset(dev
),
835 "snps,reset-delays-us",
836 sun8i_pdata
->reset_delays
, 3);
837 } else if (ret
== -ENOENT
) {
845 static const struct udevice_id sun8i_emac_eth_ids
[] = {
846 {.compatible
= "allwinner,sun8i-h3-emac", .data
= (uintptr_t)H3_EMAC
},
847 {.compatible
= "allwinner,sun50i-a64-emac",
848 .data
= (uintptr_t)A64_EMAC
},
849 {.compatible
= "allwinner,sun8i-a83t-emac",
850 .data
= (uintptr_t)A83T_EMAC
},
854 U_BOOT_DRIVER(eth_sun8i_emac
) = {
855 .name
= "eth_sun8i_emac",
857 .of_match
= sun8i_emac_eth_ids
,
858 .ofdata_to_platdata
= sun8i_emac_eth_ofdata_to_platdata
,
859 .probe
= sun8i_emac_eth_probe
,
860 .ops
= &sun8i_emac_eth_ops
,
861 .priv_auto_alloc_size
= sizeof(struct emac_eth_dev
),
862 .platdata_auto_alloc_size
= sizeof(struct sun8i_eth_pdata
),
863 .flags
= DM_FLAG_ALLOC_PRIV_DMA
,