2 * sunxi_emac.c -- Allwinner A10 ethernet driver
4 * (C) Copyright 2012, Stefan Roese <sr@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/err.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/gpio.h>
22 u32 tx_mode
; /* 0x04 */
23 u32 tx_flow
; /* 0x08 */
24 u32 tx_ctl0
; /* 0x0c */
25 u32 tx_ctl1
; /* 0x10 */
26 u32 tx_ins
; /* 0x14 */
27 u32 tx_pl0
; /* 0x18 */
28 u32 tx_pl1
; /* 0x1c */
29 u32 tx_sta
; /* 0x20 */
30 u32 tx_io_data
; /* 0x24 */
31 u32 tx_io_data1
;/* 0x28 */
32 u32 tx_tsvl0
; /* 0x2c */
33 u32 tx_tsvh0
; /* 0x30 */
34 u32 tx_tsvl1
; /* 0x34 */
35 u32 tx_tsvh1
; /* 0x38 */
36 u32 rx_ctl
; /* 0x3c */
37 u32 rx_hash0
; /* 0x40 */
38 u32 rx_hash1
; /* 0x44 */
39 u32 rx_sta
; /* 0x48 */
40 u32 rx_io_data
; /* 0x4c */
41 u32 rx_fbc
; /* 0x50 */
42 u32 int_ctl
; /* 0x54 */
43 u32 int_sta
; /* 0x58 */
44 u32 mac_ctl0
; /* 0x5c */
45 u32 mac_ctl1
; /* 0x60 */
46 u32 mac_ipgt
; /* 0x64 */
47 u32 mac_ipgr
; /* 0x68 */
48 u32 mac_clrt
; /* 0x6c */
49 u32 mac_maxf
; /* 0x70 */
50 u32 mac_supp
; /* 0x74 */
51 u32 mac_test
; /* 0x78 */
52 u32 mac_mcfg
; /* 0x7c */
53 u32 mac_mcmd
; /* 0x80 */
54 u32 mac_madr
; /* 0x84 */
55 u32 mac_mwtd
; /* 0x88 */
56 u32 mac_mrdd
; /* 0x8c */
57 u32 mac_mind
; /* 0x90 */
58 u32 mac_ssrr
; /* 0x94 */
59 u32 mac_a0
; /* 0x98 */
60 u32 mac_a1
; /* 0x9c */
64 struct sunxi_sramc_regs
{
69 /* 0: Disable 1: Aborted frame enable(default) */
70 #define EMAC_TX_AB_M (0x1 << 0)
71 /* 0: CPU 1: DMA(default) */
72 #define EMAC_TX_TM (0x1 << 1)
74 #define EMAC_TX_SETUP (0)
76 /* 0: DRQ asserted 1: DRQ automatically(default) */
77 #define EMAC_RX_DRQ_MODE (0x1 << 1)
78 /* 0: CPU 1: DMA(default) */
79 #define EMAC_RX_TM (0x1 << 2)
80 /* 0: Normal(default) 1: Pass all Frames */
81 #define EMAC_RX_PA (0x1 << 4)
82 /* 0: Normal(default) 1: Pass Control Frames */
83 #define EMAC_RX_PCF (0x1 << 5)
84 /* 0: Normal(default) 1: Pass Frames with CRC Error */
85 #define EMAC_RX_PCRCE (0x1 << 6)
86 /* 0: Normal(default) 1: Pass Frames with Length Error */
87 #define EMAC_RX_PLE (0x1 << 7)
88 /* 0: Normal 1: Pass Frames length out of range(default) */
89 #define EMAC_RX_POR (0x1 << 8)
90 /* 0: Not accept 1: Accept unicast Packets(default) */
91 #define EMAC_RX_UCAD (0x1 << 16)
92 /* 0: Normal(default) 1: DA Filtering */
93 #define EMAC_RX_DAF (0x1 << 17)
94 /* 0: Not accept 1: Accept multicast Packets(default) */
95 #define EMAC_RX_MCO (0x1 << 20)
96 /* 0: Disable(default) 1: Enable Hash filter */
97 #define EMAC_RX_MHF (0x1 << 21)
98 /* 0: Not accept 1: Accept Broadcast Packets(default) */
99 #define EMAC_RX_BCO (0x1 << 22)
100 /* 0: Disable(default) 1: Enable SA Filtering */
101 #define EMAC_RX_SAF (0x1 << 24)
102 /* 0: Normal(default) 1: Inverse Filtering */
103 #define EMAC_RX_SAIF (0x1 << 25)
105 #define EMAC_RX_SETUP (EMAC_RX_POR | EMAC_RX_UCAD | EMAC_RX_DAF | \
106 EMAC_RX_MCO | EMAC_RX_BCO)
108 /* 0: Disable 1: Enable Receive Flow Control(default) */
109 #define EMAC_MAC_CTL0_RFC (0x1 << 2)
110 /* 0: Disable 1: Enable Transmit Flow Control(default) */
111 #define EMAC_MAC_CTL0_TFC (0x1 << 3)
113 #define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC)
115 /* 0: Disable 1: Enable MAC Frame Length Checking(default) */
116 #define EMAC_MAC_CTL1_FLC (0x1 << 1)
117 /* 0: Disable(default) 1: Enable Huge Frame */
118 #define EMAC_MAC_CTL1_HF (0x1 << 2)
119 /* 0: Disable(default) 1: Enable MAC Delayed CRC */
120 #define EMAC_MAC_CTL1_DCRC (0x1 << 3)
121 /* 0: Disable 1: Enable MAC CRC(default) */
122 #define EMAC_MAC_CTL1_CRC (0x1 << 4)
123 /* 0: Disable 1: Enable MAC PAD Short frames(default) */
124 #define EMAC_MAC_CTL1_PC (0x1 << 5)
125 /* 0: Disable(default) 1: Enable MAC PAD Short frames and append CRC */
126 #define EMAC_MAC_CTL1_VC (0x1 << 6)
127 /* 0: Disable(default) 1: Enable MAC auto detect Short frames */
128 #define EMAC_MAC_CTL1_ADP (0x1 << 7)
129 /* 0: Disable(default) 1: Enable */
130 #define EMAC_MAC_CTL1_PRE (0x1 << 8)
131 /* 0: Disable(default) 1: Enable */
132 #define EMAC_MAC_CTL1_LPE (0x1 << 9)
133 /* 0: Disable(default) 1: Enable no back off */
134 #define EMAC_MAC_CTL1_NB (0x1 << 12)
135 /* 0: Disable(default) 1: Enable */
136 #define EMAC_MAC_CTL1_BNB (0x1 << 13)
137 /* 0: Disable(default) 1: Enable */
138 #define EMAC_MAC_CTL1_ED (0x1 << 14)
140 #define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \
143 #define EMAC_MAC_IPGT 0x15
145 #define EMAC_MAC_NBTB_IPG1 0xc
146 #define EMAC_MAC_NBTB_IPG2 0x12
148 #define EMAC_MAC_CW 0x37
149 #define EMAC_MAC_RM 0xf
151 #define EMAC_MAC_MFL 0x0600
154 #define EMAC_CRCERR (0x1 << 4)
155 #define EMAC_LENERR (0x3 << 5)
157 #define EMAC_RX_BUFSIZE 2000
159 struct emac_eth_dev
{
160 struct emac_regs
*regs
;
162 struct phy_device
*phydev
;
165 uchar rx_buf
[EMAC_RX_BUFSIZE
];
174 static void emac_inblk_32bit(void *reg
, void *data
, int count
)
176 int cnt
= (count
+ 3) >> 2;
188 static void emac_outblk_32bit(void *reg
, void *data
, int count
)
190 int cnt
= (count
+ 3) >> 2;
193 const u32
*buf
= data
;
201 /* Read a word from phyxcer */
202 static int emac_mdio_read(struct mii_dev
*bus
, int addr
, int devad
, int reg
)
204 struct emac_eth_dev
*priv
= bus
->priv
;
205 struct emac_regs
*regs
= priv
->regs
;
207 /* issue the phy address and reg */
208 writel(addr
<< 8 | reg
, ®s
->mac_madr
);
210 /* pull up the phy io line */
211 writel(0x1, ®s
->mac_mcmd
);
213 /* Wait read complete */
216 /* push down the phy io line */
217 writel(0x0, ®s
->mac_mcmd
);
220 return readl(®s
->mac_mrdd
);
223 /* Write a word to phyxcer */
224 static int emac_mdio_write(struct mii_dev
*bus
, int addr
, int devad
, int reg
,
227 struct emac_eth_dev
*priv
= bus
->priv
;
228 struct emac_regs
*regs
= priv
->regs
;
230 /* issue the phy address and reg */
231 writel(addr
<< 8 | reg
, ®s
->mac_madr
);
233 /* pull up the phy io line */
234 writel(0x1, ®s
->mac_mcmd
);
236 /* Wait write complete */
239 /* push down the phy io line */
240 writel(0x0, ®s
->mac_mcmd
);
243 writel(value
, ®s
->mac_mwtd
);
248 static int sunxi_emac_init_phy(struct emac_eth_dev
*priv
, void *dev
)
250 int ret
, mask
= 0xffffffff;
252 #ifdef CONFIG_PHY_ADDR
253 mask
= 1 << CONFIG_PHY_ADDR
;
256 priv
->bus
= mdio_alloc();
258 printf("Failed to allocate MDIO bus\n");
262 priv
->bus
->read
= emac_mdio_read
;
263 priv
->bus
->write
= emac_mdio_write
;
264 priv
->bus
->priv
= priv
;
265 strcpy(priv
->bus
->name
, "emac");
267 ret
= mdio_register(priv
->bus
);
271 priv
->phydev
= phy_find_by_mask(priv
->bus
, mask
,
272 PHY_INTERFACE_MODE_MII
);
276 phy_connect_dev(priv
->phydev
, dev
);
277 phy_config(priv
->phydev
);
282 static void emac_setup(struct emac_eth_dev
*priv
)
284 struct emac_regs
*regs
= priv
->regs
;
288 writel(EMAC_TX_SETUP
, ®s
->tx_mode
);
291 writel(EMAC_RX_SETUP
, ®s
->rx_ctl
);
295 writel(EMAC_MAC_CTL0_SETUP
, ®s
->mac_ctl0
);
299 if (priv
->phydev
->duplex
== DUPLEX_FULL
)
300 reg_val
= (0x1 << 0);
301 writel(EMAC_MAC_CTL1_SETUP
| reg_val
, ®s
->mac_ctl1
);
304 writel(EMAC_MAC_IPGT
, ®s
->mac_ipgt
);
307 writel(EMAC_MAC_NBTB_IPG2
| (EMAC_MAC_NBTB_IPG1
<< 8), ®s
->mac_ipgr
);
309 /* Set up Collison window */
310 writel(EMAC_MAC_RM
| (EMAC_MAC_CW
<< 8), ®s
->mac_clrt
);
312 /* Set up Max Frame Length */
313 writel(EMAC_MAC_MFL
, ®s
->mac_maxf
);
316 static void emac_reset(struct emac_eth_dev
*priv
)
318 struct emac_regs
*regs
= priv
->regs
;
320 debug("resetting device\n");
323 writel(0, ®s
->ctl
);
326 writel(1, ®s
->ctl
);
330 static int _sunxi_write_hwaddr(struct emac_eth_dev
*priv
, u8
*enetaddr
)
332 struct emac_regs
*regs
= priv
->regs
;
333 u32 enetaddr_lo
, enetaddr_hi
;
335 enetaddr_lo
= enetaddr
[2] | (enetaddr
[1] << 8) | (enetaddr
[0] << 16);
336 enetaddr_hi
= enetaddr
[5] | (enetaddr
[4] << 8) | (enetaddr
[3] << 16);
338 writel(enetaddr_hi
, ®s
->mac_a1
);
339 writel(enetaddr_lo
, ®s
->mac_a0
);
344 static int _sunxi_emac_eth_init(struct emac_eth_dev
*priv
, u8
*enetaddr
)
346 struct emac_regs
*regs
= priv
->regs
;
352 setbits_le32(®s
->rx_ctl
, 0x8);
358 clrbits_le32(®s
->mac_ctl0
, 0x1 << 15);
360 /* Clear RX counter */
361 writel(0x0, ®s
->rx_fbc
);
367 _sunxi_write_hwaddr(priv
, enetaddr
);
374 ret
= phy_startup(priv
->phydev
);
376 printf("Could not initialize PHY %s\n",
377 priv
->phydev
->dev
->name
);
381 /* Print link status only once */
382 if (!priv
->link_printed
) {
383 printf("ENET Speed is %d Mbps - %s duplex connection\n",
385 priv
->phydev
->duplex
? "FULL" : "HALF");
386 priv
->link_printed
= 1;
389 /* Set EMAC SPEED depend on PHY */
390 if (priv
->phydev
->speed
== SPEED_100
)
391 setbits_le32(®s
->mac_supp
, 1 << 8);
393 clrbits_le32(®s
->mac_supp
, 1 << 8);
395 /* Set duplex depend on phy */
396 if (priv
->phydev
->duplex
== DUPLEX_FULL
)
397 setbits_le32(®s
->mac_ctl1
, 1 << 0);
399 clrbits_le32(®s
->mac_ctl1
, 1 << 0);
402 setbits_le32(®s
->ctl
, 0x7);
407 static int _sunxi_emac_eth_recv(struct emac_eth_dev
*priv
, void *packet
)
409 struct emac_regs
*regs
= priv
->regs
;
410 struct emac_rxhdr rxhdr
;
417 /* Check packet ready or not */
419 /* Race warning: The first packet might arrive with
420 * the interrupts disabled, but the second will fix
422 rxcount
= readl(®s
->rx_fbc
);
425 rxcount
= readl(®s
->rx_fbc
);
430 reg_val
= readl(®s
->rx_io_data
);
431 if (reg_val
!= 0x0143414d) {
433 clrbits_le32(®s
->ctl
, 0x1 << 2);
436 setbits_le32(®s
->rx_ctl
, 0x1 << 3);
437 while (readl(®s
->rx_ctl
) & (0x1 << 3))
441 setbits_le32(®s
->ctl
, 0x1 << 2);
446 /* A packet ready now
451 emac_inblk_32bit(®s
->rx_io_data
, &rxhdr
, sizeof(rxhdr
));
453 rx_len
= rxhdr
.rx_len
;
454 rx_status
= rxhdr
.rx_status
;
456 /* Packet Status check */
459 debug("RX: Bad Packet (runt)\n");
462 /* rx_status is identical to RSR register. */
463 if (0 & rx_status
& (EMAC_CRCERR
| EMAC_LENERR
)) {
465 if (rx_status
& EMAC_CRCERR
)
466 printf("crc error\n");
467 if (rx_status
& EMAC_LENERR
)
468 printf("length error\n");
471 /* Move data from EMAC */
473 if (rx_len
> EMAC_RX_BUFSIZE
) {
474 printf("Received packet is too big (len=%d)\n", rx_len
);
477 emac_inblk_32bit((void *)®s
->rx_io_data
, packet
, rx_len
);
481 return -EIO
; /* Bad packet */
484 static int _sunxi_emac_eth_send(struct emac_eth_dev
*priv
, void *packet
,
487 struct emac_regs
*regs
= priv
->regs
;
489 /* Select channel 0 */
490 writel(0, ®s
->tx_ins
);
493 emac_outblk_32bit((void *)®s
->tx_io_data
, packet
, len
);
496 writel(len
, ®s
->tx_pl0
);
498 /* Start translate from fifo to phy */
499 setbits_le32(®s
->tx_ctl0
, 1);
504 static void sunxi_emac_board_setup(struct emac_eth_dev
*priv
)
506 struct sunxi_ccm_reg
*const ccm
=
507 (struct sunxi_ccm_reg
*)SUNXI_CCM_BASE
;
508 struct sunxi_sramc_regs
*sram
=
509 (struct sunxi_sramc_regs
*)SUNXI_SRAMC_BASE
;
510 struct emac_regs
*regs
= priv
->regs
;
513 /* Map SRAM to EMAC */
514 setbits_le32(&sram
->ctrl1
, 0x5 << 2);
516 /* Configure pin mux settings for MII Ethernet */
517 for (pin
= SUNXI_GPA(0); pin
<= SUNXI_GPA(17); pin
++)
518 sunxi_gpio_set_cfgpin(pin
, SUNXI_GPA_EMAC
);
520 /* Set up clock gating */
521 setbits_le32(&ccm
->ahb_gate0
, 0x1 << AHB_GATE_OFFSET_EMAC
);
524 clrsetbits_le32(®s
->mac_mcfg
, 0xf << 2, 0xd << 2);
527 static int sunxi_emac_eth_start(struct udevice
*dev
)
529 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
531 return _sunxi_emac_eth_init(dev
->priv
, pdata
->enetaddr
);
534 static int sunxi_emac_eth_send(struct udevice
*dev
, void *packet
, int length
)
536 struct emac_eth_dev
*priv
= dev_get_priv(dev
);
538 return _sunxi_emac_eth_send(priv
, packet
, length
);
541 static int sunxi_emac_eth_recv(struct udevice
*dev
, int flags
, uchar
**packetp
)
543 struct emac_eth_dev
*priv
= dev_get_priv(dev
);
546 rx_len
= _sunxi_emac_eth_recv(priv
, priv
->rx_buf
);
547 *packetp
= priv
->rx_buf
;
552 static void sunxi_emac_eth_stop(struct udevice
*dev
)
554 /* Nothing to do here */
557 static int sunxi_emac_eth_probe(struct udevice
*dev
)
559 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
560 struct emac_eth_dev
*priv
= dev_get_priv(dev
);
562 priv
->regs
= (struct emac_regs
*)pdata
->iobase
;
563 sunxi_emac_board_setup(priv
);
565 return sunxi_emac_init_phy(priv
, dev
);
568 static const struct eth_ops sunxi_emac_eth_ops
= {
569 .start
= sunxi_emac_eth_start
,
570 .send
= sunxi_emac_eth_send
,
571 .recv
= sunxi_emac_eth_recv
,
572 .stop
= sunxi_emac_eth_stop
,
575 static int sunxi_emac_eth_ofdata_to_platdata(struct udevice
*dev
)
577 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
579 pdata
->iobase
= devfdt_get_addr(dev
);
584 static const struct udevice_id sunxi_emac_eth_ids
[] = {
585 { .compatible
= "allwinner,sun4i-a10-emac" },
589 U_BOOT_DRIVER(eth_sunxi_emac
) = {
590 .name
= "eth_sunxi_emac",
592 .of_match
= sunxi_emac_eth_ids
,
593 .ofdata_to_platdata
= sunxi_emac_eth_ofdata_to_platdata
,
594 .probe
= sunxi_emac_eth_probe
,
595 .ops
= &sunxi_emac_eth_ops
,
596 .priv_auto_alloc_size
= sizeof(struct emac_eth_dev
),
597 .platdata_auto_alloc_size
= sizeof(struct eth_pdata
),