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git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/net/sunxi_emac.c
2 * sunxi_emac.c -- Allwinner A10 ethernet driver
4 * (C) Copyright 2012, Stefan Roese <sr@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/err.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/gpio.h>
21 u32 tx_mode
; /* 0x04 */
22 u32 tx_flow
; /* 0x08 */
23 u32 tx_ctl0
; /* 0x0c */
24 u32 tx_ctl1
; /* 0x10 */
25 u32 tx_ins
; /* 0x14 */
26 u32 tx_pl0
; /* 0x18 */
27 u32 tx_pl1
; /* 0x1c */
28 u32 tx_sta
; /* 0x20 */
29 u32 tx_io_data
; /* 0x24 */
30 u32 tx_io_data1
;/* 0x28 */
31 u32 tx_tsvl0
; /* 0x2c */
32 u32 tx_tsvh0
; /* 0x30 */
33 u32 tx_tsvl1
; /* 0x34 */
34 u32 tx_tsvh1
; /* 0x38 */
35 u32 rx_ctl
; /* 0x3c */
36 u32 rx_hash0
; /* 0x40 */
37 u32 rx_hash1
; /* 0x44 */
38 u32 rx_sta
; /* 0x48 */
39 u32 rx_io_data
; /* 0x4c */
40 u32 rx_fbc
; /* 0x50 */
41 u32 int_ctl
; /* 0x54 */
42 u32 int_sta
; /* 0x58 */
43 u32 mac_ctl0
; /* 0x5c */
44 u32 mac_ctl1
; /* 0x60 */
45 u32 mac_ipgt
; /* 0x64 */
46 u32 mac_ipgr
; /* 0x68 */
47 u32 mac_clrt
; /* 0x6c */
48 u32 mac_maxf
; /* 0x70 */
49 u32 mac_supp
; /* 0x74 */
50 u32 mac_test
; /* 0x78 */
51 u32 mac_mcfg
; /* 0x7c */
52 u32 mac_mcmd
; /* 0x80 */
53 u32 mac_madr
; /* 0x84 */
54 u32 mac_mwtd
; /* 0x88 */
55 u32 mac_mrdd
; /* 0x8c */
56 u32 mac_mind
; /* 0x90 */
57 u32 mac_ssrr
; /* 0x94 */
58 u32 mac_a0
; /* 0x98 */
59 u32 mac_a1
; /* 0x9c */
63 struct sunxi_sramc_regs
{
68 /* 0: Disable 1: Aborted frame enable(default) */
69 #define EMAC_TX_AB_M (0x1 << 0)
70 /* 0: CPU 1: DMA(default) */
71 #define EMAC_TX_TM (0x1 << 1)
73 #define EMAC_TX_SETUP (0)
75 /* 0: DRQ asserted 1: DRQ automatically(default) */
76 #define EMAC_RX_DRQ_MODE (0x1 << 1)
77 /* 0: CPU 1: DMA(default) */
78 #define EMAC_RX_TM (0x1 << 2)
79 /* 0: Normal(default) 1: Pass all Frames */
80 #define EMAC_RX_PA (0x1 << 4)
81 /* 0: Normal(default) 1: Pass Control Frames */
82 #define EMAC_RX_PCF (0x1 << 5)
83 /* 0: Normal(default) 1: Pass Frames with CRC Error */
84 #define EMAC_RX_PCRCE (0x1 << 6)
85 /* 0: Normal(default) 1: Pass Frames with Length Error */
86 #define EMAC_RX_PLE (0x1 << 7)
87 /* 0: Normal 1: Pass Frames length out of range(default) */
88 #define EMAC_RX_POR (0x1 << 8)
89 /* 0: Not accept 1: Accept unicast Packets(default) */
90 #define EMAC_RX_UCAD (0x1 << 16)
91 /* 0: Normal(default) 1: DA Filtering */
92 #define EMAC_RX_DAF (0x1 << 17)
93 /* 0: Not accept 1: Accept multicast Packets(default) */
94 #define EMAC_RX_MCO (0x1 << 20)
95 /* 0: Disable(default) 1: Enable Hash filter */
96 #define EMAC_RX_MHF (0x1 << 21)
97 /* 0: Not accept 1: Accept Broadcast Packets(default) */
98 #define EMAC_RX_BCO (0x1 << 22)
99 /* 0: Disable(default) 1: Enable SA Filtering */
100 #define EMAC_RX_SAF (0x1 << 24)
101 /* 0: Normal(default) 1: Inverse Filtering */
102 #define EMAC_RX_SAIF (0x1 << 25)
104 #define EMAC_RX_SETUP (EMAC_RX_POR | EMAC_RX_UCAD | EMAC_RX_DAF | \
105 EMAC_RX_MCO | EMAC_RX_BCO)
107 /* 0: Disable 1: Enable Receive Flow Control(default) */
108 #define EMAC_MAC_CTL0_RFC (0x1 << 2)
109 /* 0: Disable 1: Enable Transmit Flow Control(default) */
110 #define EMAC_MAC_CTL0_TFC (0x1 << 3)
112 #define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC)
114 /* 0: Disable 1: Enable MAC Frame Length Checking(default) */
115 #define EMAC_MAC_CTL1_FLC (0x1 << 1)
116 /* 0: Disable(default) 1: Enable Huge Frame */
117 #define EMAC_MAC_CTL1_HF (0x1 << 2)
118 /* 0: Disable(default) 1: Enable MAC Delayed CRC */
119 #define EMAC_MAC_CTL1_DCRC (0x1 << 3)
120 /* 0: Disable 1: Enable MAC CRC(default) */
121 #define EMAC_MAC_CTL1_CRC (0x1 << 4)
122 /* 0: Disable 1: Enable MAC PAD Short frames(default) */
123 #define EMAC_MAC_CTL1_PC (0x1 << 5)
124 /* 0: Disable(default) 1: Enable MAC PAD Short frames and append CRC */
125 #define EMAC_MAC_CTL1_VC (0x1 << 6)
126 /* 0: Disable(default) 1: Enable MAC auto detect Short frames */
127 #define EMAC_MAC_CTL1_ADP (0x1 << 7)
128 /* 0: Disable(default) 1: Enable */
129 #define EMAC_MAC_CTL1_PRE (0x1 << 8)
130 /* 0: Disable(default) 1: Enable */
131 #define EMAC_MAC_CTL1_LPE (0x1 << 9)
132 /* 0: Disable(default) 1: Enable no back off */
133 #define EMAC_MAC_CTL1_NB (0x1 << 12)
134 /* 0: Disable(default) 1: Enable */
135 #define EMAC_MAC_CTL1_BNB (0x1 << 13)
136 /* 0: Disable(default) 1: Enable */
137 #define EMAC_MAC_CTL1_ED (0x1 << 14)
139 #define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \
142 #define EMAC_MAC_IPGT 0x15
144 #define EMAC_MAC_NBTB_IPG1 0xc
145 #define EMAC_MAC_NBTB_IPG2 0x12
147 #define EMAC_MAC_CW 0x37
148 #define EMAC_MAC_RM 0xf
150 #define EMAC_MAC_MFL 0x0600
153 #define EMAC_CRCERR (0x1 << 4)
154 #define EMAC_LENERR (0x3 << 5)
156 #define DMA_CPU_TRRESHOLD 2000
158 struct emac_eth_dev
{
170 static void emac_inblk_32bit(void *reg
, void *data
, int count
)
172 int cnt
= (count
+ 3) >> 2;
184 static void emac_outblk_32bit(void *reg
, void *data
, int count
)
186 int cnt
= (count
+ 3) >> 2;
189 const u32
*buf
= data
;
197 /* Read a word from phyxcer */
198 static int emac_phy_read(const char *devname
, unsigned char addr
,
199 unsigned char reg
, unsigned short *value
)
201 struct eth_device
*dev
= eth_get_dev_by_name(devname
);
202 struct emac_regs
*regs
= (struct emac_regs
*)dev
->iobase
;
204 /* issue the phy address and reg */
205 writel(addr
<< 8 | reg
, ®s
->mac_madr
);
207 /* pull up the phy io line */
208 writel(0x1, ®s
->mac_mcmd
);
210 /* Wait read complete */
213 /* push down the phy io line */
214 writel(0x0, ®s
->mac_mcmd
);
217 *value
= readl(®s
->mac_mrdd
);
222 /* Write a word to phyxcer */
223 static int emac_phy_write(const char *devname
, unsigned char addr
,
224 unsigned char reg
, unsigned short value
)
226 struct eth_device
*dev
= eth_get_dev_by_name(devname
);
227 struct emac_regs
*regs
= (struct emac_regs
*)dev
->iobase
;
229 /* issue the phy address and reg */
230 writel(addr
<< 8 | reg
, ®s
->mac_madr
);
232 /* pull up the phy io line */
233 writel(0x1, ®s
->mac_mcmd
);
235 /* Wait write complete */
238 /* push down the phy io line */
239 writel(0x0, ®s
->mac_mcmd
);
242 writel(value
, ®s
->mac_mwtd
);
247 static void emac_setup(struct eth_device
*dev
)
249 struct emac_regs
*regs
= (struct emac_regs
*)dev
->iobase
;
255 writel(EMAC_TX_SETUP
, ®s
->tx_mode
);
258 writel(EMAC_RX_SETUP
, ®s
->rx_ctl
);
262 writel(EMAC_MAC_CTL0_SETUP
, ®s
->mac_ctl0
);
265 emac_phy_read(dev
->name
, 1, 0, &phy_val
);
266 debug("PHY SETUP, reg 0 value: %x\n", phy_val
);
267 duplex_flag
= !!(phy_val
& (1 << 8));
271 reg_val
= (0x1 << 0);
272 writel(EMAC_MAC_CTL1_SETUP
| reg_val
, ®s
->mac_ctl1
);
275 writel(EMAC_MAC_IPGT
, ®s
->mac_ipgt
);
278 writel(EMAC_MAC_NBTB_IPG2
| (EMAC_MAC_NBTB_IPG1
<< 8), ®s
->mac_ipgr
);
280 /* Set up Collison window */
281 writel(EMAC_MAC_RM
| (EMAC_MAC_CW
<< 8), ®s
->mac_clrt
);
283 /* Set up Max Frame Length */
284 writel(EMAC_MAC_MFL
, ®s
->mac_maxf
);
287 static void emac_reset(struct eth_device
*dev
)
289 struct emac_regs
*regs
= (struct emac_regs
*)dev
->iobase
;
291 debug("resetting device\n");
294 writel(0, ®s
->ctl
);
297 writel(1, ®s
->ctl
);
301 static int sunxi_emac_eth_init(struct eth_device
*dev
, bd_t
*bd
)
303 struct emac_regs
*regs
= (struct emac_regs
*)dev
->iobase
;
304 struct emac_eth_dev
*priv
= dev
->priv
;
310 setbits_le32(®s
->rx_ctl
, 0x8);
316 clrbits_le32(®s
->mac_ctl0
, 0x1 << 15);
318 /* Clear RX counter */
319 writel(0x0, ®s
->rx_fbc
);
325 writel(dev
->enetaddr
[0] << 16 | dev
->enetaddr
[1] << 8 |
326 dev
->enetaddr
[2], ®s
->mac_a1
);
327 writel(dev
->enetaddr
[3] << 16 | dev
->enetaddr
[4] << 8 |
328 dev
->enetaddr
[5], ®s
->mac_a0
);
335 emac_phy_read(dev
->name
, 1, 0, &phy_reg
);
336 emac_phy_write(dev
->name
, 1, 0, phy_reg
& (~(0x1 << 11)));
339 emac_phy_read(dev
->name
, 1, 0, &phy_reg
);
341 priv
->speed
= miiphy_speed(dev
->name
, 0);
342 priv
->duplex
= miiphy_duplex(dev
->name
, 0);
344 /* Print link status only once */
345 if (!priv
->link_printed
) {
346 printf("ENET Speed is %d Mbps - %s duplex connection\n",
347 priv
->speed
, (priv
->duplex
== HALF
) ? "HALF" : "FULL");
348 priv
->link_printed
= 1;
351 /* Set EMAC SPEED depend on PHY */
352 clrsetbits_le32(®s
->mac_supp
, 1 << 8,
353 ((phy_reg
& (0x1 << 13)) >> 13) << 8);
355 /* Set duplex depend on phy */
356 clrsetbits_le32(®s
->mac_ctl1
, 1 << 0,
357 ((phy_reg
& (0x1 << 8)) >> 8) << 0);
360 setbits_le32(®s
->ctl
, 0x7);
365 static void sunxi_emac_eth_halt(struct eth_device
*dev
)
367 /* Nothing to do here */
370 static int sunxi_emac_eth_recv(struct eth_device
*dev
)
372 struct emac_regs
*regs
= (struct emac_regs
*)dev
->iobase
;
373 struct emac_rxhdr rxhdr
;
380 /* Check packet ready or not */
382 /* Race warning: The first packet might arrive with
383 * the interrupts disabled, but the second will fix
385 rxcount
= readl(®s
->rx_fbc
);
388 rxcount
= readl(®s
->rx_fbc
);
393 reg_val
= readl(®s
->rx_io_data
);
394 if (reg_val
!= 0x0143414d) {
396 clrbits_le32(®s
->ctl
, 0x1 << 2);
399 setbits_le32(®s
->rx_ctl
, 0x1 << 3);
400 while (readl(®s
->rx_ctl
) & (0x1 << 3))
404 setbits_le32(®s
->ctl
, 0x1 << 2);
409 /* A packet ready now
414 emac_inblk_32bit(®s
->rx_io_data
, &rxhdr
, sizeof(rxhdr
));
416 rx_len
= rxhdr
.rx_len
;
417 rx_status
= rxhdr
.rx_status
;
419 /* Packet Status check */
422 debug("RX: Bad Packet (runt)\n");
425 /* rx_status is identical to RSR register. */
426 if (0 & rx_status
& (EMAC_CRCERR
| EMAC_LENERR
)) {
428 if (rx_status
& EMAC_CRCERR
)
429 printf("crc error\n");
430 if (rx_status
& EMAC_LENERR
)
431 printf("length error\n");
434 /* Move data from EMAC */
436 if (rx_len
> DMA_CPU_TRRESHOLD
) {
437 printf("Received packet is too big (len=%d)\n", rx_len
);
439 emac_inblk_32bit((void *)®s
->rx_io_data
,
440 NetRxPackets
[0], rx_len
);
442 /* Pass to upper layer */
443 NetReceive(NetRxPackets
[0], rx_len
);
451 static int sunxi_emac_eth_send(struct eth_device
*dev
, void *packet
, int len
)
453 struct emac_regs
*regs
= (struct emac_regs
*)dev
->iobase
;
455 /* Select channel 0 */
456 writel(0, ®s
->tx_ins
);
459 emac_outblk_32bit((void *)®s
->tx_io_data
, packet
, len
);
462 writel(len
, ®s
->tx_pl0
);
464 /* Start translate from fifo to phy */
465 setbits_le32(®s
->tx_ctl0
, 1);
470 int sunxi_emac_initialize(void)
472 struct sunxi_ccm_reg
*const ccm
=
473 (struct sunxi_ccm_reg
*)SUNXI_CCM_BASE
;
474 struct sunxi_sramc_regs
*sram
=
475 (struct sunxi_sramc_regs
*)SUNXI_SRAMC_BASE
;
476 struct emac_regs
*regs
=
477 (struct emac_regs
*)SUNXI_EMAC_BASE
;
478 struct eth_device
*dev
;
479 struct emac_eth_dev
*priv
;
482 dev
= malloc(sizeof(*dev
));
486 priv
= (struct emac_eth_dev
*)malloc(sizeof(struct emac_eth_dev
));
492 memset(dev
, 0, sizeof(*dev
));
493 memset(priv
, 0, sizeof(struct emac_eth_dev
));
495 /* Map SRAM to EMAC */
496 setbits_le32(&sram
->ctrl1
, 0x5 << 2);
498 /* Configure pin mux settings for MII Ethernet */
499 for (pin
= SUNXI_GPA(0); pin
<= SUNXI_GPA(17); pin
++)
500 sunxi_gpio_set_cfgpin(pin
, SUNXI_GPA0_EMAC
);
502 /* Set up clock gating */
503 setbits_le32(&ccm
->ahb_gate0
, 0x1 << AHB_GATE_OFFSET_EMAC
);
506 clrsetbits_le32(®s
->mac_mcfg
, 0xf << 2, 0xd << 2);
508 dev
->iobase
= (int)regs
;
510 dev
->init
= sunxi_emac_eth_init
;
511 dev
->halt
= sunxi_emac_eth_halt
;
512 dev
->send
= sunxi_emac_eth_send
;
513 dev
->recv
= sunxi_emac_eth_recv
;
514 strcpy(dev
->name
, "emac");
518 miiphy_register(dev
->name
, emac_phy_read
, emac_phy_write
);