drivers/net/sunxi_emac.c

   1 /*
   2  * sunxi_emac.c -- Allwinner A10 ethernet driver
   3  *
   4  * (C) Copyright 2012, Stefan Roese <sr@denx.de>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <linux/err.h>
  11 #include <malloc.h>
  12 #include <miiphy.h>
  13 #include <net.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/gpio.h>
  17
  18 /* EMAC register  */
  19 struct emac_regs {
  20         u32 ctl;        /* 0x00 */
  21         u32 tx_mode;    /* 0x04 */
  22         u32 tx_flow;    /* 0x08 */
  23         u32 tx_ctl0;    /* 0x0c */
  24         u32 tx_ctl1;    /* 0x10 */
  25         u32 tx_ins;     /* 0x14 */
  26         u32 tx_pl0;     /* 0x18 */
  27         u32 tx_pl1;     /* 0x1c */
  28         u32 tx_sta;     /* 0x20 */
  29         u32 tx_io_data; /* 0x24 */
  30         u32 tx_io_data1;/* 0x28 */
  31         u32 tx_tsvl0;   /* 0x2c */
  32         u32 tx_tsvh0;   /* 0x30 */
  33         u32 tx_tsvl1;   /* 0x34 */
  34         u32 tx_tsvh1;   /* 0x38 */
  35         u32 rx_ctl;     /* 0x3c */
  36         u32 rx_hash0;   /* 0x40 */
  37         u32 rx_hash1;   /* 0x44 */
  38         u32 rx_sta;     /* 0x48 */
  39         u32 rx_io_data; /* 0x4c */
  40         u32 rx_fbc;     /* 0x50 */
  41         u32 int_ctl;    /* 0x54 */
  42         u32 int_sta;    /* 0x58 */
  43         u32 mac_ctl0;   /* 0x5c */
  44         u32 mac_ctl1;   /* 0x60 */
  45         u32 mac_ipgt;   /* 0x64 */
  46         u32 mac_ipgr;   /* 0x68 */
  47         u32 mac_clrt;   /* 0x6c */
  48         u32 mac_maxf;   /* 0x70 */
  49         u32 mac_supp;   /* 0x74 */
  50         u32 mac_test;   /* 0x78 */
  51         u32 mac_mcfg;   /* 0x7c */
  52         u32 mac_mcmd;   /* 0x80 */
  53         u32 mac_madr;   /* 0x84 */
  54         u32 mac_mwtd;   /* 0x88 */
  55         u32 mac_mrdd;   /* 0x8c */
  56         u32 mac_mind;   /* 0x90 */
  57         u32 mac_ssrr;   /* 0x94 */
  58         u32 mac_a0;     /* 0x98 */
  59         u32 mac_a1;     /* 0x9c */
  60 };
  61
  62 /* SRAMC register  */
  63 struct sunxi_sramc_regs {
  64         u32 ctrl0;
  65         u32 ctrl1;
  66 };
  67
  68 /* 0: Disable       1: Aborted frame enable(default) */
  69 #define EMAC_TX_AB_M            (0x1 << 0)
  70 /* 0: CPU           1: DMA(default) */
  71 #define EMAC_TX_TM              (0x1 << 1)
  72
  73 #define EMAC_TX_SETUP           (0)
  74
  75 /* 0: DRQ asserted  1: DRQ automatically(default) */
  76 #define EMAC_RX_DRQ_MODE        (0x1 << 1)
  77 /* 0: CPU           1: DMA(default) */
  78 #define EMAC_RX_TM              (0x1 << 2)
  79 /* 0: Normal(default)        1: Pass all Frames */
  80 #define EMAC_RX_PA              (0x1 << 4)
  81 /* 0: Normal(default)        1: Pass Control Frames */
  82 #define EMAC_RX_PCF             (0x1 << 5)
  83 /* 0: Normal(default)        1: Pass Frames with CRC Error */
  84 #define EMAC_RX_PCRCE           (0x1 << 6)
  85 /* 0: Normal(default)        1: Pass Frames with Length Error */
  86 #define EMAC_RX_PLE             (0x1 << 7)
  87 /* 0: Normal                 1: Pass Frames length out of range(default) */
  88 #define EMAC_RX_POR             (0x1 << 8)
  89 /* 0: Not accept             1: Accept unicast Packets(default) */
  90 #define EMAC_RX_UCAD            (0x1 << 16)
  91 /* 0: Normal(default)        1: DA Filtering */
  92 #define EMAC_RX_DAF             (0x1 << 17)
  93 /* 0: Not accept             1: Accept multicast Packets(default) */
  94 #define EMAC_RX_MCO             (0x1 << 20)
  95 /* 0: Disable(default)       1: Enable Hash filter */
  96 #define EMAC_RX_MHF             (0x1 << 21)
  97 /* 0: Not accept             1: Accept Broadcast Packets(default) */
  98 #define EMAC_RX_BCO             (0x1 << 22)
  99 /* 0: Disable(default)       1: Enable SA Filtering */
 100 #define EMAC_RX_SAF             (0x1 << 24)
 101 /* 0: Normal(default)        1: Inverse Filtering */
 102 #define EMAC_RX_SAIF            (0x1 << 25)
 103
 104 #define EMAC_RX_SETUP           (EMAC_RX_POR | EMAC_RX_UCAD | EMAC_RX_DAF | \
 105                                  EMAC_RX_MCO | EMAC_RX_BCO)
 106
 107 /* 0: Disable                1: Enable Receive Flow Control(default) */
 108 #define EMAC_MAC_CTL0_RFC       (0x1 << 2)
 109 /* 0: Disable                1: Enable Transmit Flow Control(default) */
 110 #define EMAC_MAC_CTL0_TFC       (0x1 << 3)
 111
 112 #define EMAC_MAC_CTL0_SETUP     (EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC)
 113
 114 /* 0: Disable                1: Enable MAC Frame Length Checking(default) */
 115 #define EMAC_MAC_CTL1_FLC       (0x1 << 1)
 116 /* 0: Disable(default)       1: Enable Huge Frame */
 117 #define EMAC_MAC_CTL1_HF        (0x1 << 2)
 118 /* 0: Disable(default)       1: Enable MAC Delayed CRC */
 119 #define EMAC_MAC_CTL1_DCRC      (0x1 << 3)
 120 /* 0: Disable                1: Enable MAC CRC(default) */
 121 #define EMAC_MAC_CTL1_CRC       (0x1 << 4)
 122 /* 0: Disable                1: Enable MAC PAD Short frames(default) */
 123 #define EMAC_MAC_CTL1_PC        (0x1 << 5)
 124 /* 0: Disable(default)       1: Enable MAC PAD Short frames and append CRC */
 125 #define EMAC_MAC_CTL1_VC        (0x1 << 6)
 126 /* 0: Disable(default)       1: Enable MAC auto detect Short frames */
 127 #define EMAC_MAC_CTL1_ADP       (0x1 << 7)
 128 /* 0: Disable(default)       1: Enable */
 129 #define EMAC_MAC_CTL1_PRE       (0x1 << 8)
 130 /* 0: Disable(default)       1: Enable */
 131 #define EMAC_MAC_CTL1_LPE       (0x1 << 9)
 132 /* 0: Disable(default)       1: Enable no back off */
 133 #define EMAC_MAC_CTL1_NB        (0x1 << 12)
 134 /* 0: Disable(default)       1: Enable */
 135 #define EMAC_MAC_CTL1_BNB       (0x1 << 13)
 136 /* 0: Disable(default)       1: Enable */
 137 #define EMAC_MAC_CTL1_ED        (0x1 << 14)
 138
 139 #define EMAC_MAC_CTL1_SETUP     (EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \
 140                                  EMAC_MAC_CTL1_PC)
 141
 142 #define EMAC_MAC_IPGT           0x15
 143
 144 #define EMAC_MAC_NBTB_IPG1      0xc
 145 #define EMAC_MAC_NBTB_IPG2      0x12
 146
 147 #define EMAC_MAC_CW             0x37
 148 #define EMAC_MAC_RM             0xf
 149
 150 #define EMAC_MAC_MFL            0x0600
 151
 152 /* Receive status */
 153 #define EMAC_CRCERR             (0x1 << 4)
 154 #define EMAC_LENERR             (0x3 << 5)
 155
 156 #define EMAC_RX_BUFSIZE         2000
 157
 158 struct emac_eth_dev {
 159         struct emac_regs *regs;
 160         struct mii_dev *bus;
 161         struct phy_device *phydev;
 162         int link_printed;
 163 };
 164
 165 struct emac_rxhdr {
 166         s16 rx_len;
 167         u16 rx_status;
 168 };
 169
 170 static void emac_inblk_32bit(void *reg, void *data, int count)
 171 {
 172         int cnt = (count + 3) >> 2;
 173
 174         if (cnt) {
 175                 u32 *buf = data;
 176
 177                 do {
 178                         u32 x = readl(reg);
 179                         *buf++ = x;
 180                 } while (--cnt);
 181         }
 182 }
 183
 184 static void emac_outblk_32bit(void *reg, void *data, int count)
 185 {
 186         int cnt = (count + 3) >> 2;
 187
 188         if (cnt) {
 189                 const u32 *buf = data;
 190
 191                 do {
 192                         writel(*buf++, reg);
 193                 } while (--cnt);
 194         }
 195 }
 196
 197 /* Read a word from phyxcer */
 198 static int emac_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 199 {
 200         struct emac_eth_dev *priv = bus->priv;
 201         struct emac_regs *regs = priv->regs;
 202
 203         /* issue the phy address and reg */
 204         writel(addr << 8 | reg, &regs->mac_madr);
 205
 206         /* pull up the phy io line */
 207         writel(0x1, &regs->mac_mcmd);
 208
 209         /* Wait read complete */
 210         mdelay(1);
 211
 212         /* push down the phy io line */
 213         writel(0x0, &regs->mac_mcmd);
 214
 215         /* And read data */
 216         return readl(&regs->mac_mrdd);
 217 }
 218
 219 /* Write a word to phyxcer */
 220 static int emac_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
 221                           u16 value)
 222 {
 223         struct emac_eth_dev *priv = bus->priv;
 224         struct emac_regs *regs = priv->regs;
 225
 226         /* issue the phy address and reg */
 227         writel(addr << 8 | reg, &regs->mac_madr);
 228
 229         /* pull up the phy io line */
 230         writel(0x1, &regs->mac_mcmd);
 231
 232         /* Wait write complete */
 233         mdelay(1);
 234
 235         /* push down the phy io line */
 236         writel(0x0, &regs->mac_mcmd);
 237
 238         /* and write data */
 239         writel(value, &regs->mac_mwtd);
 240
 241         return 0;
 242 }
 243
 244 static int sunxi_emac_init_phy(struct emac_eth_dev *priv, void *dev)
 245 {
 246         int ret, mask = 0xffffffff;
 247
 248 #ifdef CONFIG_PHY_ADDR
 249         mask = 1 << CONFIG_PHY_ADDR;
 250 #endif
 251
 252         priv->bus = mdio_alloc();
 253         if (!priv->bus) {
 254                 printf("Failed to allocate MDIO bus\n");
 255                 return -ENOMEM;
 256         }
 257
 258         priv->bus->read = emac_mdio_read;
 259         priv->bus->write = emac_mdio_write;
 260         priv->bus->priv = priv;
 261         strcpy(priv->bus->name, "emac");
 262
 263         ret = mdio_register(priv->bus);
 264         if (ret)
 265                 return ret;
 266
 267         priv->phydev = phy_find_by_mask(priv->bus, mask,
 268                                         PHY_INTERFACE_MODE_MII);
 269         if (!priv->phydev)
 270                 return -ENODEV;
 271
 272         phy_connect_dev(priv->phydev, dev);
 273         phy_config(priv->phydev);
 274
 275         return 0;
 276 }
 277
 278 static void emac_setup(struct emac_eth_dev *priv)
 279 {
 280         struct emac_regs *regs = priv->regs;
 281         u32 reg_val;
 282
 283         /* Set up TX */
 284         writel(EMAC_TX_SETUP, &regs->tx_mode);
 285
 286         /* Set up RX */
 287         writel(EMAC_RX_SETUP, &regs->rx_ctl);
 288
 289         /* Set MAC */
 290         /* Set MAC CTL0 */
 291         writel(EMAC_MAC_CTL0_SETUP, &regs->mac_ctl0);
 292
 293         /* Set MAC CTL1 */
 294         reg_val = 0;
 295         if (priv->phydev->duplex == DUPLEX_FULL)
 296                 reg_val = (0x1 << 0);
 297         writel(EMAC_MAC_CTL1_SETUP | reg_val, &regs->mac_ctl1);
 298
 299         /* Set up IPGT */
 300         writel(EMAC_MAC_IPGT, &regs->mac_ipgt);
 301
 302         /* Set up IPGR */
 303         writel(EMAC_MAC_NBTB_IPG2 | (EMAC_MAC_NBTB_IPG1 << 8), &regs->mac_ipgr);
 304
 305         /* Set up Collison window */
 306         writel(EMAC_MAC_RM | (EMAC_MAC_CW << 8), &regs->mac_clrt);
 307
 308         /* Set up Max Frame Length */
 309         writel(EMAC_MAC_MFL, &regs->mac_maxf);
 310 }
 311
 312 static void emac_reset(struct emac_eth_dev *priv)
 313 {
 314         struct emac_regs *regs = priv->regs;
 315
 316         debug("resetting device\n");
 317
 318         /* RESET device */
 319         writel(0, &regs->ctl);
 320         udelay(200);
 321
 322         writel(1, &regs->ctl);
 323         udelay(200);
 324 }
 325
 326 static int _sunxi_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
 327 {
 328         struct emac_regs *regs = priv->regs;
 329         int ret;
 330
 331         /* Init EMAC */
 332
 333         /* Flush RX FIFO */
 334         setbits_le32(&regs->rx_ctl, 0x8);
 335         udelay(1);
 336
 337         /* Init MAC */
 338
 339         /* Soft reset MAC */
 340         clrbits_le32(&regs->mac_ctl0, 0x1 << 15);
 341
 342         /* Clear RX counter */
 343         writel(0x0, &regs->rx_fbc);
 344         udelay(1);
 345
 346         /* Set up EMAC */
 347         emac_setup(priv);
 348
 349         writel(enetaddr[0] << 16 | enetaddr[1] << 8 | enetaddr[2],
 350                &regs->mac_a1);
 351         writel(enetaddr[3] << 16 | enetaddr[4] << 8 | enetaddr[5],
 352                &regs->mac_a0);
 353
 354         mdelay(1);
 355
 356         emac_reset(priv);
 357
 358         /* PHY POWER UP */
 359         ret = phy_startup(priv->phydev);
 360         if (ret) {
 361                 printf("Could not initialize PHY %s\n",
 362                        priv->phydev->dev->name);
 363                 return ret;
 364         }
 365
 366         /* Print link status only once */
 367         if (!priv->link_printed) {
 368                 printf("ENET Speed is %d Mbps - %s duplex connection\n",
 369                        priv->phydev->speed,
 370                        priv->phydev->duplex ? "FULL" : "HALF");
 371                 priv->link_printed = 1;
 372         }
 373
 374         /* Set EMAC SPEED depend on PHY */
 375         if (priv->phydev->speed == SPEED_100)
 376                 setbits_le32(&regs->mac_supp, 1 << 8);
 377         else
 378                 clrbits_le32(&regs->mac_supp, 1 << 8);
 379
 380         /* Set duplex depend on phy */
 381         if (priv->phydev->duplex == DUPLEX_FULL)
 382                 setbits_le32(&regs->mac_ctl1, 1 << 0);
 383         else
 384                 clrbits_le32(&regs->mac_ctl1, 1 << 0);
 385
 386         /* Enable RX/TX */
 387         setbits_le32(&regs->ctl, 0x7);
 388
 389         return 0;
 390 }
 391
 392 static int _sunxi_emac_eth_recv(struct emac_eth_dev *priv, void *packet)
 393 {
 394         struct emac_regs *regs = priv->regs;
 395         struct emac_rxhdr rxhdr;
 396         u32 rxcount;
 397         u32 reg_val;
 398         int rx_len;
 399         int rx_status;
 400         int good_packet;
 401
 402         /* Check packet ready or not */
 403
 404         /* Race warning: The first packet might arrive with
 405          * the interrupts disabled, but the second will fix
 406          */
 407         rxcount = readl(&regs->rx_fbc);
 408         if (!rxcount) {
 409                 /* Had one stuck? */
 410                 rxcount = readl(&regs->rx_fbc);
 411                 if (!rxcount)
 412                         return -EAGAIN;
 413         }
 414
 415         reg_val = readl(&regs->rx_io_data);
 416         if (reg_val != 0x0143414d) {
 417                 /* Disable RX */
 418                 clrbits_le32(&regs->ctl, 0x1 << 2);
 419
 420                 /* Flush RX FIFO */
 421                 setbits_le32(&regs->rx_ctl, 0x1 << 3);
 422                 while (readl(&regs->rx_ctl) & (0x1 << 3))
 423                         ;
 424
 425                 /* Enable RX */
 426                 setbits_le32(&regs->ctl, 0x1 << 2);
 427
 428                 return -EAGAIN;
 429         }
 430
 431         /* A packet ready now
 432          * Get status/length
 433          */
 434         good_packet = 1;
 435
 436         emac_inblk_32bit(&regs->rx_io_data, &rxhdr, sizeof(rxhdr));
 437
 438         rx_len = rxhdr.rx_len;
 439         rx_status = rxhdr.rx_status;
 440
 441         /* Packet Status check */
 442         if (rx_len < 0x40) {
 443                 good_packet = 0;
 444                 debug("RX: Bad Packet (runt)\n");
 445         }
 446
 447         /* rx_status is identical to RSR register. */
 448         if (0 & rx_status & (EMAC_CRCERR | EMAC_LENERR)) {
 449                 good_packet = 0;
 450                 if (rx_status & EMAC_CRCERR)
 451                         printf("crc error\n");
 452                 if (rx_status & EMAC_LENERR)
 453                         printf("length error\n");
 454         }
 455
 456         /* Move data from EMAC */
 457         if (good_packet) {
 458                 if (rx_len > EMAC_RX_BUFSIZE) {
 459                         printf("Received packet is too big (len=%d)\n", rx_len);
 460                         return -EMSGSIZE;
 461                 }
 462                 emac_inblk_32bit((void *)&regs->rx_io_data, packet, rx_len);
 463                 return rx_len;
 464         }
 465
 466         return -EIO; /* Bad packet */
 467 }
 468
 469 static int _sunxi_emac_eth_send(struct emac_eth_dev *priv, void *packet,
 470                                 int len)
 471 {
 472         struct emac_regs *regs = priv->regs;
 473
 474         /* Select channel 0 */
 475         writel(0, &regs->tx_ins);
 476
 477         /* Write packet */
 478         emac_outblk_32bit((void *)&regs->tx_io_data, packet, len);
 479
 480         /* Set TX len */
 481         writel(len, &regs->tx_pl0);
 482
 483         /* Start translate from fifo to phy */
 484         setbits_le32(&regs->tx_ctl0, 1);
 485
 486         return 0;
 487 }
 488
 489 static void sunxi_emac_board_setup(struct emac_eth_dev *priv)
 490 {
 491         struct sunxi_ccm_reg *const ccm =
 492                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 493         struct sunxi_sramc_regs *sram =
 494                 (struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
 495         struct emac_regs *regs = priv->regs;
 496         int pin;
 497
 498         /* Map SRAM to EMAC */
 499         setbits_le32(&sram->ctrl1, 0x5 << 2);
 500
 501         /* Configure pin mux settings for MII Ethernet */
 502         for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
 503                 sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC);
 504
 505         /* Set up clock gating */
 506         setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC);
 507
 508         /* Set MII clock */
 509         clrsetbits_le32(&regs->mac_mcfg, 0xf << 2, 0xd << 2);
 510 }
 511
 512 static int sunxi_emac_eth_init(struct eth_device *dev, bd_t *bis)
 513 {
 514         return _sunxi_emac_eth_init(dev->priv, dev->enetaddr);
 515 }
 516
 517 static void sunxi_emac_eth_halt(struct eth_device *dev)
 518 {
 519         /* Nothing to do here */
 520 }
 521
 522 static int sunxi_emac_eth_recv(struct eth_device *dev)
 523 {
 524         int rx_len;
 525
 526         rx_len = _sunxi_emac_eth_recv(dev->priv, net_rx_packets[0]);
 527         if (rx_len <= 0)
 528                 return 0;
 529
 530         /* Pass to upper layer */
 531         net_process_received_packet(net_rx_packets[0], rx_len);
 532
 533         return rx_len;
 534 }
 535
 536 static int sunxi_emac_eth_send(struct eth_device *dev, void *packet, int length)
 537 {
 538         return _sunxi_emac_eth_send(dev->priv, packet, length);
 539 }
 540
 541 int sunxi_emac_initialize(void)
 542 {
 543         struct emac_regs *regs =
 544                 (struct emac_regs *)SUNXI_EMAC_BASE;
 545         struct eth_device *dev;
 546         struct emac_eth_dev *priv;
 547
 548         dev = malloc(sizeof(*dev));
 549         if (dev == NULL)
 550                 return -ENOMEM;
 551
 552         priv = (struct emac_eth_dev *)malloc(sizeof(struct emac_eth_dev));
 553         if (!priv) {
 554                 free(dev);
 555                 return -ENOMEM;
 556         }
 557
 558         memset(dev, 0, sizeof(*dev));
 559         memset(priv, 0, sizeof(struct emac_eth_dev));
 560
 561         priv->regs = regs;
 562         dev->iobase = (int)regs;
 563         dev->priv = priv;
 564         dev->init = sunxi_emac_eth_init;
 565         dev->halt = sunxi_emac_eth_halt;
 566         dev->send = sunxi_emac_eth_send;
 567         dev->recv = sunxi_emac_eth_recv;
 568         strcpy(dev->name, "emac");
 569
 570         sunxi_emac_board_setup(priv);
 571
 572         eth_register(dev);
 573
 574         return sunxi_emac_init_phy(priv, dev);
 575 }