drivers/net/tsec.c

   1 /*
   2  * Freescale Three Speed Ethernet Controller driver
   3  *
   4  * This software may be used and distributed according to the
   5  * terms of the GNU Public License, Version 2, incorporated
   6  * herein by reference.
   7  *
   8  * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
   9  * (C) Copyright 2003, Motorola, Inc.
  10  * author Andy Fleming
  11  *
  12  */
  13
  14 #include <config.h>
  15 #include <common.h>
  16 #include <malloc.h>
  17 #include <net.h>
  18 #include <command.h>
  19 #include <tsec.h>
  20 #include <fsl_mdio.h>
  21 #include <asm/errno.h>
  22 #include <asm/processor.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 #define TX_BUF_CNT              2
  27
  28 static uint rx_idx;             /* index of the current RX buffer */
  29 static uint tx_idx;             /* index of the current TX buffer */
  30
  31 #ifdef __GNUC__
  32 static struct txbd8 __iomem txbd[TX_BUF_CNT] __aligned(8);
  33 static struct rxbd8 __iomem rxbd[PKTBUFSRX] __aligned(8);
  34
  35 #else
  36 #error "rtx must be 64-bit aligned"
  37 #endif
  38
  39 static int tsec_send(struct eth_device *dev, void *packet, int length);
  40
  41 /* Default initializations for TSEC controllers. */
  42
  43 static struct tsec_info_struct tsec_info[] = {
  44 #ifdef CONFIG_TSEC1
  45         STD_TSEC_INFO(1),       /* TSEC1 */
  46 #endif
  47 #ifdef CONFIG_TSEC2
  48         STD_TSEC_INFO(2),       /* TSEC2 */
  49 #endif
  50 #ifdef CONFIG_MPC85XX_FEC
  51         {
  52                 .regs = TSEC_GET_REGS(2, 0x2000),
  53                 .devname = CONFIG_MPC85XX_FEC_NAME,
  54                 .phyaddr = FEC_PHY_ADDR,
  55                 .flags = FEC_FLAGS,
  56                 .mii_devname = DEFAULT_MII_NAME
  57         },                      /* FEC */
  58 #endif
  59 #ifdef CONFIG_TSEC3
  60         STD_TSEC_INFO(3),       /* TSEC3 */
  61 #endif
  62 #ifdef CONFIG_TSEC4
  63         STD_TSEC_INFO(4),       /* TSEC4 */
  64 #endif
  65 };
  66
  67 #define TBIANA_SETTINGS ( \
  68                 TBIANA_ASYMMETRIC_PAUSE \
  69                 | TBIANA_SYMMETRIC_PAUSE \
  70                 | TBIANA_FULL_DUPLEX \
  71                 )
  72
  73 /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
  74 #ifndef CONFIG_TSEC_TBICR_SETTINGS
  75 #define CONFIG_TSEC_TBICR_SETTINGS ( \
  76                 TBICR_PHY_RESET \
  77                 | TBICR_ANEG_ENABLE \
  78                 | TBICR_FULL_DUPLEX \
  79                 | TBICR_SPEED1_SET \
  80                 )
  81 #endif /* CONFIG_TSEC_TBICR_SETTINGS */
  82
  83 /* Configure the TBI for SGMII operation */
  84 static void tsec_configure_serdes(struct tsec_private *priv)
  85 {
  86         /* Access TBI PHY registers at given TSEC register offset as opposed
  87          * to the register offset used for external PHY accesses */
  88         tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
  89                         0, TBI_ANA, TBIANA_SETTINGS);
  90         tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
  91                         0, TBI_TBICON, TBICON_CLK_SELECT);
  92         tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
  93                         0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
  94 }
  95
  96 #ifdef CONFIG_MCAST_TFTP
  97
  98 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
  99
 100 /* Set the appropriate hash bit for the given addr */
 101
 102 /* The algorithm works like so:
 103  * 1) Take the Destination Address (ie the multicast address), and
 104  * do a CRC on it (little endian), and reverse the bits of the
 105  * result.
 106  * 2) Use the 8 most significant bits as a hash into a 256-entry
 107  * table.  The table is controlled through 8 32-bit registers:
 108  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is entry
 109  * 255.  This means that the 3 most significant bits in the
 110  * hash index which gaddr register to use, and the 5 other bits
 111  * indicate which bit (assuming an IBM numbering scheme, which
 112  * for PowerPC (tm) is usually the case) in the register holds
 113  * the entry. */
 114 static int
 115 tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
 116 {
 117         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 118         struct tsec __iomem *regs = priv->regs;
 119         u32 result, value;
 120         u8 whichbit, whichreg;
 121
 122         result = ether_crc(MAC_ADDR_LEN, mcast_mac);
 123         whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
 124         whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
 125
 126         value = 1 << (31-whichbit);
 127
 128         if (set)
 129                 setbits_be32(&regs->hash.gaddr0 + whichreg, value);
 130         else
 131                 clrbits_be32(&regs->hash.gaddr0 + whichreg, value);
 132
 133         return 0;
 134 }
 135 #endif /* Multicast TFTP ? */
 136
 137 /* Initialized required registers to appropriate values, zeroing
 138  * those we don't care about (unless zero is bad, in which case,
 139  * choose a more appropriate value)
 140  */
 141 static void init_registers(struct tsec __iomem *regs)
 142 {
 143         /* Clear IEVENT */
 144         out_be32(&regs->ievent, IEVENT_INIT_CLEAR);
 145
 146         out_be32(&regs->imask, IMASK_INIT_CLEAR);
 147
 148         out_be32(&regs->hash.iaddr0, 0);
 149         out_be32(&regs->hash.iaddr1, 0);
 150         out_be32(&regs->hash.iaddr2, 0);
 151         out_be32(&regs->hash.iaddr3, 0);
 152         out_be32(&regs->hash.iaddr4, 0);
 153         out_be32(&regs->hash.iaddr5, 0);
 154         out_be32(&regs->hash.iaddr6, 0);
 155         out_be32(&regs->hash.iaddr7, 0);
 156
 157         out_be32(&regs->hash.gaddr0, 0);
 158         out_be32(&regs->hash.gaddr1, 0);
 159         out_be32(&regs->hash.gaddr2, 0);
 160         out_be32(&regs->hash.gaddr3, 0);
 161         out_be32(&regs->hash.gaddr4, 0);
 162         out_be32(&regs->hash.gaddr5, 0);
 163         out_be32(&regs->hash.gaddr6, 0);
 164         out_be32(&regs->hash.gaddr7, 0);
 165
 166         out_be32(&regs->rctrl, 0x00000000);
 167
 168         /* Init RMON mib registers */
 169         memset((void *)&regs->rmon, 0, sizeof(regs->rmon));
 170
 171         out_be32(&regs->rmon.cam1, 0xffffffff);
 172         out_be32(&regs->rmon.cam2, 0xffffffff);
 173
 174         out_be32(&regs->mrblr, MRBLR_INIT_SETTINGS);
 175
 176         out_be32(&regs->minflr, MINFLR_INIT_SETTINGS);
 177
 178         out_be32(&regs->attr, ATTR_INIT_SETTINGS);
 179         out_be32(&regs->attreli, ATTRELI_INIT_SETTINGS);
 180
 181 }
 182
 183 /* Configure maccfg2 based on negotiated speed and duplex
 184  * reported by PHY handling code
 185  */
 186 static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
 187 {
 188         struct tsec __iomem *regs = priv->regs;
 189         u32 ecntrl, maccfg2;
 190
 191         if (!phydev->link) {
 192                 printf("%s: No link.\n", phydev->dev->name);
 193                 return;
 194         }
 195
 196         /* clear all bits relative with interface mode */
 197         ecntrl = in_be32(&regs->ecntrl);
 198         ecntrl &= ~ECNTRL_R100;
 199
 200         maccfg2 = in_be32(&regs->maccfg2);
 201         maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
 202
 203         if (phydev->duplex)
 204                 maccfg2 |= MACCFG2_FULL_DUPLEX;
 205
 206         switch (phydev->speed) {
 207         case 1000:
 208                 maccfg2 |= MACCFG2_GMII;
 209                 break;
 210         case 100:
 211         case 10:
 212                 maccfg2 |= MACCFG2_MII;
 213
 214                 /* Set R100 bit in all modes although
 215                  * it is only used in RGMII mode
 216                  */
 217                 if (phydev->speed == 100)
 218                         ecntrl |= ECNTRL_R100;
 219                 break;
 220         default:
 221                 printf("%s: Speed was bad\n", phydev->dev->name);
 222                 break;
 223         }
 224
 225         out_be32(&regs->ecntrl, ecntrl);
 226         out_be32(&regs->maccfg2, maccfg2);
 227
 228         printf("Speed: %d, %s duplex%s\n", phydev->speed,
 229                         (phydev->duplex) ? "full" : "half",
 230                         (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
 231 }
 232
 233 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
 234 /*
 235  * When MACCFG1[Rx_EN] is enabled during system boot as part
 236  * of the eTSEC port initialization sequence,
 237  * the eTSEC Rx logic may not be properly initialized.
 238  */
 239 void redundant_init(struct eth_device *dev)
 240 {
 241         struct tsec_private *priv = dev->priv;
 242         struct tsec __iomem *regs = priv->regs;
 243         uint t, count = 0;
 244         int fail = 1;
 245         static const u8 pkt[] = {
 246                 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
 247                 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
 248                 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
 249                 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
 250                 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
 251                 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
 252                 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
 253                 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
 254                 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
 255                 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
 256                 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
 257                 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
 258                 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
 259                 0x71, 0x72};
 260
 261         /* Enable promiscuous mode */
 262         setbits_be32(&regs->rctrl, 0x8);
 263         /* Enable loopback mode */
 264         setbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
 265         /* Enable transmit and receive */
 266         setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
 267
 268         /* Tell the DMA it is clear to go */
 269         setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
 270         out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
 271         out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
 272         clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
 273
 274         do {
 275                 uint16_t status;
 276                 tsec_send(dev, (void *)pkt, sizeof(pkt));
 277
 278                 /* Wait for buffer to be received */
 279                 for (t = 0; in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY; t++) {
 280                         if (t >= 10 * TOUT_LOOP) {
 281                                 printf("%s: tsec: rx error\n", dev->name);
 282                                 break;
 283                         }
 284                 }
 285
 286                 if (!memcmp(pkt, (void *)NetRxPackets[rx_idx], sizeof(pkt)))
 287                         fail = 0;
 288
 289                 out_be16(&rxbd[rx_idx].length, 0);
 290                 status = RXBD_EMPTY;
 291                 if ((rx_idx + 1) == PKTBUFSRX)
 292                         status |= RXBD_WRAP;
 293                 out_be16(&rxbd[rx_idx].status, status);
 294                 rx_idx = (rx_idx + 1) % PKTBUFSRX;
 295
 296                 if (in_be32(&regs->ievent) & IEVENT_BSY) {
 297                         out_be32(&regs->ievent, IEVENT_BSY);
 298                         out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
 299                 }
 300                 if (fail) {
 301                         printf("loopback recv packet error!\n");
 302                         clrbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
 303                         udelay(1000);
 304                         setbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
 305                 }
 306         } while ((count++ < 4) && (fail == 1));
 307
 308         if (fail)
 309                 panic("eTSEC init fail!\n");
 310         /* Disable promiscuous mode */
 311         clrbits_be32(&regs->rctrl, 0x8);
 312         /* Disable loopback mode */
 313         clrbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
 314 }
 315 #endif
 316
 317 /* Set up the buffers and their descriptors, and bring up the
 318  * interface
 319  */
 320 static void startup_tsec(struct eth_device *dev)
 321 {
 322         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 323         struct tsec __iomem *regs = priv->regs;
 324         uint16_t status;
 325         int i;
 326
 327         /* reset the indices to zero */
 328         rx_idx = 0;
 329         tx_idx = 0;
 330 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
 331         uint svr;
 332 #endif
 333
 334         /* Point to the buffer descriptors */
 335         out_be32(&regs->tbase, (u32)&txbd[0]);
 336         out_be32(&regs->rbase, (u32)&rxbd[0]);
 337
 338         /* Initialize the Rx Buffer descriptors */
 339         for (i = 0; i < PKTBUFSRX; i++) {
 340                 out_be16(&rxbd[i].status, RXBD_EMPTY);
 341                 out_be16(&rxbd[i].length, 0);
 342                 out_be32(&rxbd[i].bufptr, (u32)NetRxPackets[i]);
 343         }
 344         status = in_be16(&rxbd[PKTBUFSRX - 1].status);
 345         out_be16(&rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
 346
 347         /* Initialize the TX Buffer Descriptors */
 348         for (i = 0; i < TX_BUF_CNT; i++) {
 349                 out_be16(&txbd[i].status, 0);
 350                 out_be16(&txbd[i].length, 0);
 351                 out_be32(&txbd[i].bufptr, 0);
 352         }
 353         status = in_be16(&txbd[TX_BUF_CNT - 1].status);
 354         out_be16(&txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
 355
 356 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
 357         svr = get_svr();
 358         if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
 359                 redundant_init(dev);
 360 #endif
 361         /* Enable Transmit and Receive */
 362         setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
 363
 364         /* Tell the DMA it is clear to go */
 365         setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
 366         out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
 367         out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
 368         clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
 369 }
 370
 371 /* This returns the status bits of the device.  The return value
 372  * is never checked, and this is what the 8260 driver did, so we
 373  * do the same.  Presumably, this would be zero if there were no
 374  * errors
 375  */
 376 static int tsec_send(struct eth_device *dev, void *packet, int length)
 377 {
 378         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 379         struct tsec __iomem *regs = priv->regs;
 380         uint16_t status;
 381         int result = 0;
 382         int i;
 383
 384         /* Find an empty buffer descriptor */
 385         for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) {
 386                 if (i >= TOUT_LOOP) {
 387                         debug("%s: tsec: tx buffers full\n", dev->name);
 388                         return result;
 389                 }
 390         }
 391
 392         out_be32(&txbd[tx_idx].bufptr, (u32)packet);
 393         out_be16(&txbd[tx_idx].length, length);
 394         status = in_be16(&txbd[tx_idx].status);
 395         out_be16(&txbd[tx_idx].status, status |
 396                 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
 397
 398         /* Tell the DMA to go */
 399         out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
 400
 401         /* Wait for buffer to be transmitted */
 402         for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) {
 403                 if (i >= TOUT_LOOP) {
 404                         debug("%s: tsec: tx error\n", dev->name);
 405                         return result;
 406                 }
 407         }
 408
 409         tx_idx = (tx_idx + 1) % TX_BUF_CNT;
 410         result = in_be16(&txbd[tx_idx].status) & TXBD_STATS;
 411
 412         return result;
 413 }
 414
 415 static int tsec_recv(struct eth_device *dev)
 416 {
 417         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 418         struct tsec __iomem *regs = priv->regs;
 419
 420         while (!(in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY)) {
 421                 int length = in_be16(&rxbd[rx_idx].length);
 422                 uint16_t status = in_be16(&rxbd[rx_idx].status);
 423
 424                 /* Send the packet up if there were no errors */
 425                 if (!(status & RXBD_STATS))
 426                         NetReceive(NetRxPackets[rx_idx], length - 4);
 427                 else
 428                         printf("Got error %x\n", (status & RXBD_STATS));
 429
 430                 out_be16(&rxbd[rx_idx].length, 0);
 431
 432                 status = RXBD_EMPTY;
 433                 /* Set the wrap bit if this is the last element in the list */
 434                 if ((rx_idx + 1) == PKTBUFSRX)
 435                         status |= RXBD_WRAP;
 436                 out_be16(&rxbd[rx_idx].status, status);
 437
 438                 rx_idx = (rx_idx + 1) % PKTBUFSRX;
 439         }
 440
 441         if (in_be32(&regs->ievent) & IEVENT_BSY) {
 442                 out_be32(&regs->ievent, IEVENT_BSY);
 443                 out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
 444         }
 445
 446         return -1;
 447
 448 }
 449
 450 /* Stop the interface */
 451 static void tsec_halt(struct eth_device *dev)
 452 {
 453         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 454         struct tsec __iomem *regs = priv->regs;
 455
 456         clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
 457         setbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
 458
 459         while ((in_be32(&regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
 460                         != (IEVENT_GRSC | IEVENT_GTSC))
 461                 ;
 462
 463         clrbits_be32(&regs->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
 464
 465         /* Shut down the PHY, as needed */
 466         phy_shutdown(priv->phydev);
 467 }
 468
 469 /* Initializes data structures and registers for the controller,
 470  * and brings the interface up.  Returns the link status, meaning
 471  * that it returns success if the link is up, failure otherwise.
 472  * This allows u-boot to find the first active controller.
 473  */
 474 static int tsec_init(struct eth_device *dev, bd_t * bd)
 475 {
 476         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 477         struct tsec __iomem *regs = priv->regs;
 478         u32 tempval;
 479         int ret;
 480
 481         /* Make sure the controller is stopped */
 482         tsec_halt(dev);
 483
 484         /* Init MACCFG2.  Defaults to GMII */
 485         out_be32(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
 486
 487         /* Init ECNTRL */
 488         out_be32(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
 489
 490         /* Copy the station address into the address registers.
 491          * For a station address of 0x12345678ABCD in transmission
 492          * order (BE), MACnADDR1 is set to 0xCDAB7856 and
 493          * MACnADDR2 is set to 0x34120000.
 494          */
 495         tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) |
 496                   (dev->enetaddr[3] << 8)  |  dev->enetaddr[2];
 497
 498         out_be32(&regs->macstnaddr1, tempval);
 499
 500         tempval = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16);
 501
 502         out_be32(&regs->macstnaddr2, tempval);
 503
 504         /* Clear out (for the most part) the other registers */
 505         init_registers(regs);
 506
 507         /* Ready the device for tx/rx */
 508         startup_tsec(dev);
 509
 510         /* Start up the PHY */
 511         ret = phy_startup(priv->phydev);
 512         if (ret) {
 513                 printf("Could not initialize PHY %s\n",
 514                        priv->phydev->dev->name);
 515                 return ret;
 516         }
 517
 518         adjust_link(priv, priv->phydev);
 519
 520         /* If there's no link, fail */
 521         return priv->phydev->link ? 0 : -1;
 522 }
 523
 524 static phy_interface_t tsec_get_interface(struct tsec_private *priv)
 525 {
 526         struct tsec __iomem *regs = priv->regs;
 527         u32 ecntrl;
 528
 529         ecntrl = in_be32(&regs->ecntrl);
 530
 531         if (ecntrl & ECNTRL_SGMII_MODE)
 532                 return PHY_INTERFACE_MODE_SGMII;
 533
 534         if (ecntrl & ECNTRL_TBI_MODE) {
 535                 if (ecntrl & ECNTRL_REDUCED_MODE)
 536                         return PHY_INTERFACE_MODE_RTBI;
 537                 else
 538                         return PHY_INTERFACE_MODE_TBI;
 539         }
 540
 541         if (ecntrl & ECNTRL_REDUCED_MODE) {
 542                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
 543                         return PHY_INTERFACE_MODE_RMII;
 544                 else {
 545                         phy_interface_t interface = priv->interface;
 546
 547                         /*
 548                          * This isn't autodetected, so it must
 549                          * be set by the platform code.
 550                          */
 551                         if ((interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 552                                  (interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
 553                                  (interface == PHY_INTERFACE_MODE_RGMII_RXID))
 554                                 return interface;
 555
 556                         return PHY_INTERFACE_MODE_RGMII;
 557                 }
 558         }
 559
 560         if (priv->flags & TSEC_GIGABIT)
 561                 return PHY_INTERFACE_MODE_GMII;
 562
 563         return PHY_INTERFACE_MODE_MII;
 564 }
 565
 566
 567 /* Discover which PHY is attached to the device, and configure it
 568  * properly.  If the PHY is not recognized, then return 0
 569  * (failure).  Otherwise, return 1
 570  */
 571 static int init_phy(struct eth_device *dev)
 572 {
 573         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 574         struct phy_device *phydev;
 575         struct tsec __iomem *regs = priv->regs;
 576         u32 supported = (SUPPORTED_10baseT_Half |
 577                         SUPPORTED_10baseT_Full |
 578                         SUPPORTED_100baseT_Half |
 579                         SUPPORTED_100baseT_Full);
 580
 581         if (priv->flags & TSEC_GIGABIT)
 582                 supported |= SUPPORTED_1000baseT_Full;
 583
 584         /* Assign a Physical address to the TBI */
 585         out_be32(&regs->tbipa, CONFIG_SYS_TBIPA_VALUE);
 586
 587         priv->interface = tsec_get_interface(priv);
 588
 589         if (priv->interface == PHY_INTERFACE_MODE_SGMII)
 590                 tsec_configure_serdes(priv);
 591
 592         phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
 593
 594         phydev->supported &= supported;
 595         phydev->advertising = phydev->supported;
 596
 597         priv->phydev = phydev;
 598
 599         phy_config(phydev);
 600
 601         return 1;
 602 }
 603
 604 /* Initialize device structure. Returns success if PHY
 605  * initialization succeeded (i.e. if it recognizes the PHY)
 606  */
 607 static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
 608 {
 609         struct eth_device *dev;
 610         int i;
 611         struct tsec_private *priv;
 612
 613         dev = (struct eth_device *)malloc(sizeof *dev);
 614
 615         if (NULL == dev)
 616                 return 0;
 617
 618         memset(dev, 0, sizeof *dev);
 619
 620         priv = (struct tsec_private *)malloc(sizeof(*priv));
 621
 622         if (NULL == priv)
 623                 return 0;
 624
 625         priv->regs = tsec_info->regs;
 626         priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
 627
 628         priv->phyaddr = tsec_info->phyaddr;
 629         priv->flags = tsec_info->flags;
 630
 631         sprintf(dev->name, tsec_info->devname);
 632         priv->interface = tsec_info->interface;
 633         priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
 634         dev->iobase = 0;
 635         dev->priv = priv;
 636         dev->init = tsec_init;
 637         dev->halt = tsec_halt;
 638         dev->send = tsec_send;
 639         dev->recv = tsec_recv;
 640 #ifdef CONFIG_MCAST_TFTP
 641         dev->mcast = tsec_mcast_addr;
 642 #endif
 643
 644         /* Tell u-boot to get the addr from the env */
 645         for (i = 0; i < 6; i++)
 646                 dev->enetaddr[i] = 0;
 647
 648         eth_register(dev);
 649
 650         /* Reset the MAC */
 651         setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
 652         udelay(2);  /* Soft Reset must be asserted for 3 TX clocks */
 653         clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
 654
 655         /* Try to initialize PHY here, and return */
 656         return init_phy(dev);
 657 }
 658
 659 /*
 660  * Initialize all the TSEC devices
 661  *
 662  * Returns the number of TSEC devices that were initialized
 663  */
 664 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
 665 {
 666         int i;
 667         int ret, count = 0;
 668
 669         for (i = 0; i < num; i++) {
 670                 ret = tsec_initialize(bis, &tsecs[i]);
 671                 if (ret > 0)
 672                         count += ret;
 673         }
 674
 675         return count;
 676 }
 677
 678 int tsec_standard_init(bd_t *bis)
 679 {
 680         struct fsl_pq_mdio_info info;
 681
 682         info.regs = TSEC_GET_MDIO_REGS_BASE(1);
 683         info.name = DEFAULT_MII_NAME;
 684
 685         fsl_pq_mdio_init(bis, &info);
 686
 687         return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
 688 }