2 * Freescale Three Speed Ethernet Controller driver
4 * This software may be used and distributed according to the
5 * terms of the GNU Public License, Version 2, incorporated
8 * Copyright 2004-2009 Freescale Semiconductor, Inc.
9 * (C) Copyright 2003, Motorola, Inc.
20 #include <asm/errno.h>
24 DECLARE_GLOBAL_DATA_PTR
;
28 static uint rxIdx
; /* index of the current RX buffer */
29 static uint txIdx
; /* index of the current TX buffer */
31 typedef volatile struct rtxbd
{
32 txbd8_t txbd
[TX_BUF_CNT
];
33 rxbd8_t rxbd
[PKTBUFSRX
];
36 #define MAXCONTROLLERS (8)
38 static struct tsec_private
*privlist
[MAXCONTROLLERS
];
39 static int num_tsecs
= 0;
42 static RTXBD rtx
__attribute__ ((aligned(8)));
44 #error "rtx must be 64-bit aligned"
47 static int tsec_send(struct eth_device
*dev
,
48 volatile void *packet
, int length
);
49 static int tsec_recv(struct eth_device
*dev
);
50 static int tsec_init(struct eth_device
*dev
, bd_t
* bd
);
51 static void tsec_halt(struct eth_device
*dev
);
52 static void init_registers(volatile tsec_t
* regs
);
53 static void startup_tsec(struct eth_device
*dev
);
54 static int init_phy(struct eth_device
*dev
);
55 void write_phy_reg(struct tsec_private
*priv
, uint regnum
, uint value
);
56 uint
read_phy_reg(struct tsec_private
*priv
, uint regnum
);
57 struct phy_info
*get_phy_info(struct eth_device
*dev
);
58 void phy_run_commands(struct tsec_private
*priv
, struct phy_cmd
*cmd
);
59 static void adjust_link(struct eth_device
*dev
);
60 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
61 && !defined(BITBANGMII)
62 static int tsec_miiphy_write(char *devname
, unsigned char addr
,
63 unsigned char reg
, unsigned short value
);
64 static int tsec_miiphy_read(char *devname
, unsigned char addr
,
65 unsigned char reg
, unsigned short *value
);
67 #ifdef CONFIG_MCAST_TFTP
68 static int tsec_mcast_addr (struct eth_device
*dev
, u8 mcast_mac
, u8 set
);
71 /* Default initializations for TSEC controllers. */
73 static struct tsec_info_struct tsec_info
[] = {
75 STD_TSEC_INFO(1), /* TSEC1 */
78 STD_TSEC_INFO(2), /* TSEC2 */
80 #ifdef CONFIG_MPC85XX_FEC
82 .regs
= (tsec_t
*)(TSEC_BASE_ADDR
+ 0x2000),
83 .miiregs
= (tsec_mdio_t
*)(MDIO_BASE_ADDR
),
84 .devname
= CONFIG_MPC85XX_FEC_NAME
,
85 .phyaddr
= FEC_PHY_ADDR
,
90 STD_TSEC_INFO(3), /* TSEC3 */
93 STD_TSEC_INFO(4), /* TSEC4 */
97 int tsec_eth_init(bd_t
*bis
, struct tsec_info_struct
*tsecs
, int num
)
101 for (i
= 0; i
< num
; i
++)
102 tsec_initialize(bis
, &tsecs
[i
]);
107 int tsec_standard_init(bd_t
*bis
)
109 return tsec_eth_init(bis
, tsec_info
, ARRAY_SIZE(tsec_info
));
112 /* Initialize device structure. Returns success if PHY
113 * initialization succeeded (i.e. if it recognizes the PHY)
115 int tsec_initialize(bd_t
* bis
, struct tsec_info_struct
*tsec_info
)
117 struct eth_device
*dev
;
119 struct tsec_private
*priv
;
121 dev
= (struct eth_device
*)malloc(sizeof *dev
);
126 memset(dev
, 0, sizeof *dev
);
128 priv
= (struct tsec_private
*)malloc(sizeof(*priv
));
133 privlist
[num_tsecs
++] = priv
;
134 priv
->regs
= tsec_info
->regs
;
135 priv
->phyregs
= tsec_info
->miiregs
;
136 priv
->phyregs_sgmii
= tsec_info
->miiregs_sgmii
;
138 priv
->phyaddr
= tsec_info
->phyaddr
;
139 priv
->flags
= tsec_info
->flags
;
141 sprintf(dev
->name
, tsec_info
->devname
);
144 dev
->init
= tsec_init
;
145 dev
->halt
= tsec_halt
;
146 dev
->send
= tsec_send
;
147 dev
->recv
= tsec_recv
;
148 #ifdef CONFIG_MCAST_TFTP
149 dev
->mcast
= tsec_mcast_addr
;
152 /* Tell u-boot to get the addr from the env */
153 for (i
= 0; i
< 6; i
++)
154 dev
->enetaddr
[i
] = 0;
159 priv
->regs
->maccfg1
|= MACCFG1_SOFT_RESET
;
160 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
161 priv
->regs
->maccfg1
&= ~(MACCFG1_SOFT_RESET
);
163 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
164 && !defined(BITBANGMII)
165 miiphy_register(dev
->name
, tsec_miiphy_read
, tsec_miiphy_write
);
168 /* Try to initialize PHY here, and return */
169 return init_phy(dev
);
172 /* Initializes data structures and registers for the controller,
173 * and brings the interface up. Returns the link status, meaning
174 * that it returns success if the link is up, failure otherwise.
175 * This allows u-boot to find the first active controller.
177 int tsec_init(struct eth_device
*dev
, bd_t
* bd
)
180 char tmpbuf
[MAC_ADDR_LEN
];
182 struct tsec_private
*priv
= (struct tsec_private
*)dev
->priv
;
183 volatile tsec_t
*regs
= priv
->regs
;
185 /* Make sure the controller is stopped */
188 /* Init MACCFG2. Defaults to GMII */
189 regs
->maccfg2
= MACCFG2_INIT_SETTINGS
;
192 regs
->ecntrl
= ECNTRL_INIT_SETTINGS
;
194 /* Copy the station address into the address registers.
195 * Backwards, because little endian MACS are dumb */
196 for (i
= 0; i
< MAC_ADDR_LEN
; i
++) {
197 tmpbuf
[MAC_ADDR_LEN
- 1 - i
] = dev
->enetaddr
[i
];
199 tempval
= (tmpbuf
[0] << 24) | (tmpbuf
[1] << 16) | (tmpbuf
[2] << 8) |
202 regs
->macstnaddr1
= tempval
;
204 tempval
= *((uint
*) (tmpbuf
+ 4));
206 regs
->macstnaddr2
= tempval
;
208 /* reset the indices to zero */
212 /* Clear out (for the most part) the other registers */
213 init_registers(regs
);
215 /* Ready the device for tx/rx */
218 /* If there's no link, fail */
219 return (priv
->link
? 0 : -1);
222 /* Writes the given phy's reg with value, using the specified MDIO regs */
223 static void tsec_local_mdio_write(volatile tsec_mdio_t
*phyregs
, uint addr
,
224 uint reg
, uint value
)
226 int timeout
= 1000000;
228 phyregs
->miimadd
= (addr
<< 8) | reg
;
229 phyregs
->miimcon
= value
;
233 while ((phyregs
->miimind
& MIIMIND_BUSY
) && timeout
--) ;
237 /* Provide the default behavior of writing the PHY of this ethernet device */
238 #define write_phy_reg(priv, regnum, value) tsec_local_mdio_write(priv->phyregs,priv->phyaddr,regnum,value)
240 /* Reads register regnum on the device's PHY through the
241 * specified registers. It lowers and raises the read
242 * command, and waits for the data to become valid (miimind
243 * notvalid bit cleared), and the bus to cease activity (miimind
244 * busy bit cleared), and then returns the value
246 uint
tsec_local_mdio_read(volatile tsec_mdio_t
*phyregs
, uint phyid
, uint regnum
)
250 /* Put the address of the phy, and the register
251 * number into MIIMADD */
252 phyregs
->miimadd
= (phyid
<< 8) | regnum
;
254 /* Clear the command register, and wait */
255 phyregs
->miimcom
= 0;
258 /* Initiate a read command, and wait */
259 phyregs
->miimcom
= MIIM_READ_COMMAND
;
262 /* Wait for the the indication that the read is done */
263 while ((phyregs
->miimind
& (MIIMIND_NOTVALID
| MIIMIND_BUSY
))) ;
265 /* Grab the value read from the PHY */
266 value
= phyregs
->miimstat
;
271 /* #define to provide old read_phy_reg functionality without duplicating code */
272 #define read_phy_reg(priv,regnum) tsec_local_mdio_read(priv->phyregs,priv->phyaddr,regnum)
274 #define TBIANA_SETTINGS ( \
275 TBIANA_ASYMMETRIC_PAUSE \
276 | TBIANA_SYMMETRIC_PAUSE \
277 | TBIANA_FULL_DUPLEX \
280 #define TBICR_SETTINGS ( \
282 | TBICR_ANEG_ENABLE \
283 | TBICR_FULL_DUPLEX \
286 /* Configure the TBI for SGMII operation */
287 static void tsec_configure_serdes(struct tsec_private
*priv
)
289 /* Access TBI PHY registers at given TSEC register offset as opposed to the
290 * register offset used for external PHY accesses */
291 tsec_local_mdio_write(priv
->phyregs_sgmii
, priv
->regs
->tbipa
, TBI_ANA
,
293 tsec_local_mdio_write(priv
->phyregs_sgmii
, priv
->regs
->tbipa
, TBI_TBICON
,
295 tsec_local_mdio_write(priv
->phyregs_sgmii
, priv
->regs
->tbipa
, TBI_CR
,
299 /* Discover which PHY is attached to the device, and configure it
300 * properly. If the PHY is not recognized, then return 0
301 * (failure). Otherwise, return 1
303 static int init_phy(struct eth_device
*dev
)
305 struct tsec_private
*priv
= (struct tsec_private
*)dev
->priv
;
306 struct phy_info
*curphy
;
307 volatile tsec_t
*regs
= priv
->regs
;
309 /* Assign a Physical address to the TBI */
310 regs
->tbipa
= CONFIG_SYS_TBIPA_VALUE
;
313 /* Reset MII (due to new addresses) */
314 priv
->phyregs
->miimcfg
= MIIMCFG_RESET
;
316 priv
->phyregs
->miimcfg
= MIIMCFG_INIT_VALUE
;
318 while (priv
->phyregs
->miimind
& MIIMIND_BUSY
) ;
320 /* Get the cmd structure corresponding to the attached
322 curphy
= get_phy_info(dev
);
324 if (curphy
== NULL
) {
325 priv
->phyinfo
= NULL
;
326 printf("%s: No PHY found\n", dev
->name
);
331 if (regs
->ecntrl
& ECNTRL_SGMII_MODE
)
332 tsec_configure_serdes(priv
);
334 priv
->phyinfo
= curphy
;
336 phy_run_commands(priv
, priv
->phyinfo
->config
);
342 * Returns which value to write to the control register.
343 * For 10/100, the value is slightly different
345 uint
mii_cr_init(uint mii_reg
, struct tsec_private
* priv
)
347 if (priv
->flags
& TSEC_GIGABIT
)
348 return MIIM_CONTROL_INIT
;
354 * Wait for auto-negotiation to complete, then determine link
356 uint
mii_parse_sr(uint mii_reg
, struct tsec_private
* priv
)
359 * Wait if the link is up, and autonegotiation is in progress
360 * (ie - we're capable and it's not done)
362 mii_reg
= read_phy_reg(priv
, MIIM_STATUS
);
363 if ((mii_reg
& PHY_BMSR_AUTN_ABLE
) && !(mii_reg
& PHY_BMSR_AUTN_COMP
)) {
366 puts("Waiting for PHY auto negotiation to complete");
367 while (!(mii_reg
& PHY_BMSR_AUTN_COMP
)) {
371 if (i
> PHY_AUTONEGOTIATE_TIMEOUT
) {
372 puts(" TIMEOUT !\n");
378 puts("user interrupt!\n");
383 if ((i
++ % 1000) == 0) {
386 udelay(1000); /* 1 ms */
387 mii_reg
= read_phy_reg(priv
, MIIM_STATUS
);
391 /* Link status bit is latched low, read it again */
392 mii_reg
= read_phy_reg(priv
, MIIM_STATUS
);
394 udelay(500000); /* another 500 ms (results in faster booting) */
397 priv
->link
= mii_reg
& MIIM_STATUS_LINK
? 1 : 0;
402 /* Generic function which updates the speed and duplex. If
403 * autonegotiation is enabled, it uses the AND of the link
404 * partner's advertised capabilities and our advertised
405 * capabilities. If autonegotiation is disabled, we use the
406 * appropriate bits in the control register.
408 * Stolen from Linux's mii.c and phy_device.c
410 uint
mii_parse_link(uint mii_reg
, struct tsec_private
*priv
)
412 /* We're using autonegotiation */
413 if (mii_reg
& PHY_BMSR_AUTN_ABLE
) {
417 /* Check for gigabit capability */
418 if (mii_reg
& PHY_BMSR_EXT
) {
419 /* We want a list of states supported by
420 * both PHYs in the link
422 gblpa
= read_phy_reg(priv
, PHY_1000BTSR
);
423 gblpa
&= read_phy_reg(priv
, PHY_1000BTCR
) << 2;
426 /* Set the baseline so we only have to set them
427 * if they're different
432 /* Check the gigabit fields */
433 if (gblpa
& (PHY_1000BTSR_1000FD
| PHY_1000BTSR_1000HD
)) {
436 if (gblpa
& PHY_1000BTSR_1000FD
)
443 lpa
= read_phy_reg(priv
, PHY_ANAR
);
444 lpa
&= read_phy_reg(priv
, PHY_ANLPAR
);
446 if (lpa
& (PHY_ANLPAR_TXFD
| PHY_ANLPAR_TX
)) {
449 if (lpa
& PHY_ANLPAR_TXFD
)
452 } else if (lpa
& PHY_ANLPAR_10FD
)
455 uint bmcr
= read_phy_reg(priv
, PHY_BMCR
);
460 if (bmcr
& PHY_BMCR_DPLX
)
463 if (bmcr
& PHY_BMCR_1000_MBPS
)
465 else if (bmcr
& PHY_BMCR_100_MBPS
)
473 * "Ethernet@Wirespeed" needs to be enabled to achieve link in certain
474 * circumstances. eg a gigabit TSEC connected to a gigabit switch with
475 * a 4-wire ethernet cable. Both ends advertise gigabit, but can't
476 * link. "Ethernet@Wirespeed" reduces advertised speed until link
479 uint
mii_BCM54xx_wirespeed(uint mii_reg
, struct tsec_private
*priv
)
481 return (read_phy_reg(priv
, mii_reg
) & 0x8FFF) | 0x8010;
485 * Parse the BCM54xx status register for speed and duplex information.
486 * The linux sungem_phy has this information, but in a table format.
488 uint
mii_parse_BCM54xx_sr(uint mii_reg
, struct tsec_private
*priv
)
491 switch((mii_reg
& MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK
) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT
){
494 printf("Enet starting in 10BT/HD\n");
500 printf("Enet starting in 10BT/FD\n");
506 printf("Enet starting in 100BT/HD\n");
512 printf("Enet starting in 100BT/FD\n");
518 printf("Enet starting in 1000BT/HD\n");
524 printf("Enet starting in 1000BT/FD\n");
530 printf("Auto-neg error, defaulting to 10BT/HD\n");
539 /* Parse the 88E1011's status register for speed and duplex
542 uint
mii_parse_88E1011_psr(uint mii_reg
, struct tsec_private
* priv
)
546 mii_reg
= read_phy_reg(priv
, MIIM_88E1011_PHY_STATUS
);
548 if ((mii_reg
& MIIM_88E1011_PHYSTAT_LINK
) &&
549 !(mii_reg
& MIIM_88E1011_PHYSTAT_SPDDONE
)) {
552 puts("Waiting for PHY realtime link");
553 while (!(mii_reg
& MIIM_88E1011_PHYSTAT_SPDDONE
)) {
554 /* Timeout reached ? */
555 if (i
> PHY_AUTONEGOTIATE_TIMEOUT
) {
556 puts(" TIMEOUT !\n");
561 if ((i
++ % 1000) == 0) {
564 udelay(1000); /* 1 ms */
565 mii_reg
= read_phy_reg(priv
, MIIM_88E1011_PHY_STATUS
);
568 udelay(500000); /* another 500 ms (results in faster booting) */
570 if (mii_reg
& MIIM_88E1011_PHYSTAT_LINK
)
576 if (mii_reg
& MIIM_88E1011_PHYSTAT_DUPLEX
)
581 speed
= (mii_reg
& MIIM_88E1011_PHYSTAT_SPEED
);
584 case MIIM_88E1011_PHYSTAT_GBIT
:
587 case MIIM_88E1011_PHYSTAT_100
:
597 /* Parse the RTL8211B's status register for speed and duplex
600 uint
mii_parse_RTL8211B_sr(uint mii_reg
, struct tsec_private
* priv
)
604 mii_reg
= read_phy_reg(priv
, MIIM_RTL8211B_PHY_STATUS
);
605 if (!(mii_reg
& MIIM_RTL8211B_PHYSTAT_SPDDONE
)) {
608 /* in case of timeout ->link is cleared */
610 puts("Waiting for PHY realtime link");
611 while (!(mii_reg
& MIIM_RTL8211B_PHYSTAT_SPDDONE
)) {
612 /* Timeout reached ? */
613 if (i
> PHY_AUTONEGOTIATE_TIMEOUT
) {
614 puts(" TIMEOUT !\n");
619 if ((i
++ % 1000) == 0) {
622 udelay(1000); /* 1 ms */
623 mii_reg
= read_phy_reg(priv
, MIIM_RTL8211B_PHY_STATUS
);
626 udelay(500000); /* another 500 ms (results in faster booting) */
628 if (mii_reg
& MIIM_RTL8211B_PHYSTAT_LINK
)
634 if (mii_reg
& MIIM_RTL8211B_PHYSTAT_DUPLEX
)
639 speed
= (mii_reg
& MIIM_RTL8211B_PHYSTAT_SPEED
);
642 case MIIM_RTL8211B_PHYSTAT_GBIT
:
645 case MIIM_RTL8211B_PHYSTAT_100
:
655 /* Parse the cis8201's status register for speed and duplex
658 uint
mii_parse_cis8201(uint mii_reg
, struct tsec_private
* priv
)
662 if (mii_reg
& MIIM_CIS8201_AUXCONSTAT_DUPLEX
)
667 speed
= mii_reg
& MIIM_CIS8201_AUXCONSTAT_SPEED
;
669 case MIIM_CIS8201_AUXCONSTAT_GBIT
:
672 case MIIM_CIS8201_AUXCONSTAT_100
:
683 /* Parse the vsc8244's status register for speed and duplex
686 uint
mii_parse_vsc8244(uint mii_reg
, struct tsec_private
* priv
)
690 if (mii_reg
& MIIM_VSC8244_AUXCONSTAT_DUPLEX
)
695 speed
= mii_reg
& MIIM_VSC8244_AUXCONSTAT_SPEED
;
697 case MIIM_VSC8244_AUXCONSTAT_GBIT
:
700 case MIIM_VSC8244_AUXCONSTAT_100
:
711 /* Parse the DM9161's status register for speed and duplex
714 uint
mii_parse_dm9161_scsr(uint mii_reg
, struct tsec_private
* priv
)
716 if (mii_reg
& (MIIM_DM9161_SCSR_100F
| MIIM_DM9161_SCSR_100H
))
721 if (mii_reg
& (MIIM_DM9161_SCSR_100F
| MIIM_DM9161_SCSR_10F
))
730 * Hack to write all 4 PHYs with the LED values
732 uint
mii_cis8204_fixled(uint mii_reg
, struct tsec_private
* priv
)
735 volatile tsec_mdio_t
*regbase
= priv
->phyregs
;
736 int timeout
= 1000000;
738 for (phyid
= 0; phyid
< 4; phyid
++) {
739 regbase
->miimadd
= (phyid
<< 8) | mii_reg
;
740 regbase
->miimcon
= MIIM_CIS8204_SLEDCON_INIT
;
744 while ((regbase
->miimind
& MIIMIND_BUSY
) && timeout
--) ;
747 return MIIM_CIS8204_SLEDCON_INIT
;
750 uint
mii_cis8204_setmode(uint mii_reg
, struct tsec_private
* priv
)
752 if (priv
->flags
& TSEC_REDUCED
)
753 return MIIM_CIS8204_EPHYCON_INIT
| MIIM_CIS8204_EPHYCON_RGMII
;
755 return MIIM_CIS8204_EPHYCON_INIT
;
758 uint
mii_m88e1111s_setmode(uint mii_reg
, struct tsec_private
*priv
)
760 uint mii_data
= read_phy_reg(priv
, mii_reg
);
762 if (priv
->flags
& TSEC_REDUCED
)
763 mii_data
= (mii_data
& 0xfff0) | 0x000b;
767 /* Initialized required registers to appropriate values, zeroing
768 * those we don't care about (unless zero is bad, in which case,
769 * choose a more appropriate value)
771 static void init_registers(volatile tsec_t
* regs
)
774 regs
->ievent
= IEVENT_INIT_CLEAR
;
776 regs
->imask
= IMASK_INIT_CLEAR
;
778 regs
->hash
.iaddr0
= 0;
779 regs
->hash
.iaddr1
= 0;
780 regs
->hash
.iaddr2
= 0;
781 regs
->hash
.iaddr3
= 0;
782 regs
->hash
.iaddr4
= 0;
783 regs
->hash
.iaddr5
= 0;
784 regs
->hash
.iaddr6
= 0;
785 regs
->hash
.iaddr7
= 0;
787 regs
->hash
.gaddr0
= 0;
788 regs
->hash
.gaddr1
= 0;
789 regs
->hash
.gaddr2
= 0;
790 regs
->hash
.gaddr3
= 0;
791 regs
->hash
.gaddr4
= 0;
792 regs
->hash
.gaddr5
= 0;
793 regs
->hash
.gaddr6
= 0;
794 regs
->hash
.gaddr7
= 0;
796 regs
->rctrl
= 0x00000000;
798 /* Init RMON mib registers */
799 memset((void *)&(regs
->rmon
), 0, sizeof(rmon_mib_t
));
801 regs
->rmon
.cam1
= 0xffffffff;
802 regs
->rmon
.cam2
= 0xffffffff;
804 regs
->mrblr
= MRBLR_INIT_SETTINGS
;
806 regs
->minflr
= MINFLR_INIT_SETTINGS
;
808 regs
->attr
= ATTR_INIT_SETTINGS
;
809 regs
->attreli
= ATTRELI_INIT_SETTINGS
;
813 /* Configure maccfg2 based on negotiated speed and duplex
814 * reported by PHY handling code
816 static void adjust_link(struct eth_device
*dev
)
818 struct tsec_private
*priv
= (struct tsec_private
*)dev
->priv
;
819 volatile tsec_t
*regs
= priv
->regs
;
822 if (priv
->duplexity
!= 0)
823 regs
->maccfg2
|= MACCFG2_FULL_DUPLEX
;
825 regs
->maccfg2
&= ~(MACCFG2_FULL_DUPLEX
);
827 switch (priv
->speed
) {
829 regs
->maccfg2
= ((regs
->maccfg2
& ~(MACCFG2_IF
))
834 regs
->maccfg2
= ((regs
->maccfg2
& ~(MACCFG2_IF
))
837 /* Set R100 bit in all modes although
838 * it is only used in RGMII mode
840 if (priv
->speed
== 100)
841 regs
->ecntrl
|= ECNTRL_R100
;
843 regs
->ecntrl
&= ~(ECNTRL_R100
);
846 printf("%s: Speed was bad\n", dev
->name
);
850 printf("Speed: %d, %s duplex\n", priv
->speed
,
851 (priv
->duplexity
) ? "full" : "half");
854 printf("%s: No link.\n", dev
->name
);
858 /* Set up the buffers and their descriptors, and bring up the
861 static void startup_tsec(struct eth_device
*dev
)
864 struct tsec_private
*priv
= (struct tsec_private
*)dev
->priv
;
865 volatile tsec_t
*regs
= priv
->regs
;
867 /* Point to the buffer descriptors */
868 regs
->tbase
= (unsigned int)(&rtx
.txbd
[txIdx
]);
869 regs
->rbase
= (unsigned int)(&rtx
.rxbd
[rxIdx
]);
871 /* Initialize the Rx Buffer descriptors */
872 for (i
= 0; i
< PKTBUFSRX
; i
++) {
873 rtx
.rxbd
[i
].status
= RXBD_EMPTY
;
874 rtx
.rxbd
[i
].length
= 0;
875 rtx
.rxbd
[i
].bufPtr
= (uint
) NetRxPackets
[i
];
877 rtx
.rxbd
[PKTBUFSRX
- 1].status
|= RXBD_WRAP
;
879 /* Initialize the TX Buffer Descriptors */
880 for (i
= 0; i
< TX_BUF_CNT
; i
++) {
881 rtx
.txbd
[i
].status
= 0;
882 rtx
.txbd
[i
].length
= 0;
883 rtx
.txbd
[i
].bufPtr
= 0;
885 rtx
.txbd
[TX_BUF_CNT
- 1].status
|= TXBD_WRAP
;
887 /* Start up the PHY */
889 phy_run_commands(priv
, priv
->phyinfo
->startup
);
893 /* Enable Transmit and Receive */
894 regs
->maccfg1
|= (MACCFG1_RX_EN
| MACCFG1_TX_EN
);
896 /* Tell the DMA it is clear to go */
897 regs
->dmactrl
|= DMACTRL_INIT_SETTINGS
;
898 regs
->tstat
= TSTAT_CLEAR_THALT
;
899 regs
->rstat
= RSTAT_CLEAR_RHALT
;
900 regs
->dmactrl
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
903 /* This returns the status bits of the device. The return value
904 * is never checked, and this is what the 8260 driver did, so we
905 * do the same. Presumably, this would be zero if there were no
908 static int tsec_send(struct eth_device
*dev
, volatile void *packet
, int length
)
912 struct tsec_private
*priv
= (struct tsec_private
*)dev
->priv
;
913 volatile tsec_t
*regs
= priv
->regs
;
915 /* Find an empty buffer descriptor */
916 for (i
= 0; rtx
.txbd
[txIdx
].status
& TXBD_READY
; i
++) {
917 if (i
>= TOUT_LOOP
) {
918 debug("%s: tsec: tx buffers full\n", dev
->name
);
923 rtx
.txbd
[txIdx
].bufPtr
= (uint
) packet
;
924 rtx
.txbd
[txIdx
].length
= length
;
925 rtx
.txbd
[txIdx
].status
|=
926 (TXBD_READY
| TXBD_LAST
| TXBD_CRC
| TXBD_INTERRUPT
);
928 /* Tell the DMA to go */
929 regs
->tstat
= TSTAT_CLEAR_THALT
;
931 /* Wait for buffer to be transmitted */
932 for (i
= 0; rtx
.txbd
[txIdx
].status
& TXBD_READY
; i
++) {
933 if (i
>= TOUT_LOOP
) {
934 debug("%s: tsec: tx error\n", dev
->name
);
939 txIdx
= (txIdx
+ 1) % TX_BUF_CNT
;
940 result
= rtx
.txbd
[txIdx
].status
& TXBD_STATS
;
945 static int tsec_recv(struct eth_device
*dev
)
948 struct tsec_private
*priv
= (struct tsec_private
*)dev
->priv
;
949 volatile tsec_t
*regs
= priv
->regs
;
951 while (!(rtx
.rxbd
[rxIdx
].status
& RXBD_EMPTY
)) {
953 length
= rtx
.rxbd
[rxIdx
].length
;
955 /* Send the packet up if there were no errors */
956 if (!(rtx
.rxbd
[rxIdx
].status
& RXBD_STATS
)) {
957 NetReceive(NetRxPackets
[rxIdx
], length
- 4);
959 printf("Got error %x\n",
960 (rtx
.rxbd
[rxIdx
].status
& RXBD_STATS
));
963 rtx
.rxbd
[rxIdx
].length
= 0;
965 /* Set the wrap bit if this is the last element in the list */
966 rtx
.rxbd
[rxIdx
].status
=
967 RXBD_EMPTY
| (((rxIdx
+ 1) == PKTBUFSRX
) ? RXBD_WRAP
: 0);
969 rxIdx
= (rxIdx
+ 1) % PKTBUFSRX
;
972 if (regs
->ievent
& IEVENT_BSY
) {
973 regs
->ievent
= IEVENT_BSY
;
974 regs
->rstat
= RSTAT_CLEAR_RHALT
;
981 /* Stop the interface */
982 static void tsec_halt(struct eth_device
*dev
)
984 struct tsec_private
*priv
= (struct tsec_private
*)dev
->priv
;
985 volatile tsec_t
*regs
= priv
->regs
;
987 regs
->dmactrl
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
988 regs
->dmactrl
|= (DMACTRL_GRS
| DMACTRL_GTS
);
990 while (!(regs
->ievent
& (IEVENT_GRSC
| IEVENT_GTSC
))) ;
992 regs
->maccfg1
&= ~(MACCFG1_TX_EN
| MACCFG1_RX_EN
);
994 /* Shut down the PHY, as needed */
996 phy_run_commands(priv
, priv
->phyinfo
->shutdown
);
999 struct phy_info phy_info_M88E1149S
= {
1003 (struct phy_cmd
[]){ /* config */
1004 /* Reset and configure the PHY */
1005 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
1007 {0x1e, 0x200c, NULL
},
1010 {0x1e, 0x100, NULL
},
1011 {MIIM_GBIT_CONTROL
, MIIM_GBIT_CONTROL_INIT
, NULL
},
1012 {MIIM_ANAR
, MIIM_ANAR_INIT
, NULL
},
1013 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
1014 {MIIM_CONTROL
, MIIM_CONTROL_INIT
, &mii_cr_init
},
1017 (struct phy_cmd
[]){ /* startup */
1018 /* Status is read once to clear old link state */
1019 {MIIM_STATUS
, miim_read
, NULL
},
1020 /* Auto-negotiate */
1021 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
1022 /* Read the status */
1023 {MIIM_88E1011_PHY_STATUS
, miim_read
,
1024 &mii_parse_88E1011_psr
},
1027 (struct phy_cmd
[]){ /* shutdown */
1032 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */
1033 struct phy_info phy_info_BCM5461S
= {
1034 0x02060c1, /* 5461 ID */
1035 "Broadcom BCM5461S",
1036 0, /* not clear to me what minor revisions we can shift away */
1037 (struct phy_cmd
[]) { /* config */
1038 /* Reset and configure the PHY */
1039 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
1040 {MIIM_GBIT_CONTROL
, MIIM_GBIT_CONTROL_INIT
, NULL
},
1041 {MIIM_ANAR
, MIIM_ANAR_INIT
, NULL
},
1042 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
1043 {MIIM_CONTROL
, MIIM_CONTROL_INIT
, &mii_cr_init
},
1046 (struct phy_cmd
[]) { /* startup */
1047 /* Status is read once to clear old link state */
1048 {MIIM_STATUS
, miim_read
, NULL
},
1049 /* Auto-negotiate */
1050 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
1051 /* Read the status */
1052 {MIIM_BCM54xx_AUXSTATUS
, miim_read
, &mii_parse_BCM54xx_sr
},
1055 (struct phy_cmd
[]) { /* shutdown */
1060 struct phy_info phy_info_BCM5464S
= {
1061 0x02060b1, /* 5464 ID */
1062 "Broadcom BCM5464S",
1063 0, /* not clear to me what minor revisions we can shift away */
1064 (struct phy_cmd
[]) { /* config */
1065 /* Reset and configure the PHY */
1066 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
1067 {MIIM_GBIT_CONTROL
, MIIM_GBIT_CONTROL_INIT
, NULL
},
1068 {MIIM_ANAR
, MIIM_ANAR_INIT
, NULL
},
1069 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
1070 {MIIM_CONTROL
, MIIM_CONTROL_INIT
, &mii_cr_init
},
1073 (struct phy_cmd
[]) { /* startup */
1074 /* Status is read once to clear old link state */
1075 {MIIM_STATUS
, miim_read
, NULL
},
1076 /* Auto-negotiate */
1077 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
1078 /* Read the status */
1079 {MIIM_BCM54xx_AUXSTATUS
, miim_read
, &mii_parse_BCM54xx_sr
},
1082 (struct phy_cmd
[]) { /* shutdown */
1087 struct phy_info phy_info_BCM5482S
= {
1089 "Broadcom BCM5482S",
1091 (struct phy_cmd
[]) { /* config */
1092 /* Reset and configure the PHY */
1093 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
1094 /* Setup read from auxilary control shadow register 7 */
1095 {MIIM_BCM54xx_AUXCNTL
, MIIM_BCM54xx_AUXCNTL_ENCODE(7), NULL
},
1096 /* Read Misc Control register and or in Ethernet@Wirespeed */
1097 {MIIM_BCM54xx_AUXCNTL
, 0, &mii_BCM54xx_wirespeed
},
1098 {MIIM_CONTROL
, MIIM_CONTROL_INIT
, &mii_cr_init
},
1101 (struct phy_cmd
[]) { /* startup */
1102 /* Status is read once to clear old link state */
1103 {MIIM_STATUS
, miim_read
, NULL
},
1104 /* Auto-negotiate */
1105 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
1106 /* Read the status */
1107 {MIIM_BCM54xx_AUXSTATUS
, miim_read
, &mii_parse_BCM54xx_sr
},
1110 (struct phy_cmd
[]) { /* shutdown */
1115 struct phy_info phy_info_M88E1011S
= {
1119 (struct phy_cmd
[]){ /* config */
1120 /* Reset and configure the PHY */
1121 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
1123 {0x1e, 0x200c, NULL
},
1126 {0x1e, 0x100, NULL
},
1127 {MIIM_GBIT_CONTROL
, MIIM_GBIT_CONTROL_INIT
, NULL
},
1128 {MIIM_ANAR
, MIIM_ANAR_INIT
, NULL
},
1129 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
1130 {MIIM_CONTROL
, MIIM_CONTROL_INIT
, &mii_cr_init
},
1133 (struct phy_cmd
[]){ /* startup */
1134 /* Status is read once to clear old link state */
1135 {MIIM_STATUS
, miim_read
, NULL
},
1136 /* Auto-negotiate */
1137 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
1138 /* Read the status */
1139 {MIIM_88E1011_PHY_STATUS
, miim_read
,
1140 &mii_parse_88E1011_psr
},
1143 (struct phy_cmd
[]){ /* shutdown */
1148 struct phy_info phy_info_M88E1111S
= {
1152 (struct phy_cmd
[]){ /* config */
1153 /* Reset and configure the PHY */
1154 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
1155 {0x1b, 0x848f, &mii_m88e1111s_setmode
},
1156 {0x14, 0x0cd2, NULL
}, /* Delay RGMII TX and RX */
1157 {MIIM_GBIT_CONTROL
, MIIM_GBIT_CONTROL_INIT
, NULL
},
1158 {MIIM_ANAR
, MIIM_ANAR_INIT
, NULL
},
1159 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
1160 {MIIM_CONTROL
, MIIM_CONTROL_INIT
, &mii_cr_init
},
1163 (struct phy_cmd
[]){ /* startup */
1164 /* Status is read once to clear old link state */
1165 {MIIM_STATUS
, miim_read
, NULL
},
1166 /* Auto-negotiate */
1167 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
1168 /* Read the status */
1169 {MIIM_88E1011_PHY_STATUS
, miim_read
,
1170 &mii_parse_88E1011_psr
},
1173 (struct phy_cmd
[]){ /* shutdown */
1178 struct phy_info phy_info_M88E1118
= {
1182 (struct phy_cmd
[]){ /* config */
1183 /* Reset and configure the PHY */
1184 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
1185 {0x16, 0x0002, NULL
}, /* Change Page Number */
1186 {0x15, 0x1070, NULL
}, /* Delay RGMII TX and RX */
1187 {0x16, 0x0003, NULL
}, /* Change Page Number */
1188 {0x10, 0x021e, NULL
}, /* Adjust LED control */
1189 {0x16, 0x0000, NULL
}, /* Change Page Number */
1190 {MIIM_GBIT_CONTROL
, MIIM_GBIT_CONTROL_INIT
, NULL
},
1191 {MIIM_ANAR
, MIIM_ANAR_INIT
, NULL
},
1192 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
1193 {MIIM_CONTROL
, MIIM_CONTROL_INIT
, &mii_cr_init
},
1196 (struct phy_cmd
[]){ /* startup */
1197 {0x16, 0x0000, NULL
}, /* Change Page Number */
1198 /* Status is read once to clear old link state */
1199 {MIIM_STATUS
, miim_read
, NULL
},
1200 /* Auto-negotiate */
1201 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
1202 /* Read the status */
1203 {MIIM_88E1011_PHY_STATUS
, miim_read
,
1204 &mii_parse_88E1011_psr
},
1207 (struct phy_cmd
[]){ /* shutdown */
1213 * Since to access LED register we need do switch the page, we
1214 * do LED configuring in the miim_read-like function as follows
1216 uint
mii_88E1121_set_led (uint mii_reg
, struct tsec_private
*priv
)
1220 /* Switch the page to access the led register */
1221 pg
= read_phy_reg(priv
, MIIM_88E1121_PHY_PAGE
);
1222 write_phy_reg(priv
, MIIM_88E1121_PHY_PAGE
, MIIM_88E1121_PHY_LED_PAGE
);
1224 /* Configure leds */
1225 write_phy_reg(priv
, MIIM_88E1121_PHY_LED_CTRL
,
1226 MIIM_88E1121_PHY_LED_DEF
);
1228 /* Restore the page pointer */
1229 write_phy_reg(priv
, MIIM_88E1121_PHY_PAGE
, pg
);
1233 struct phy_info phy_info_M88E1121R
= {
1237 (struct phy_cmd
[]){ /* config */
1238 /* Reset and configure the PHY */
1239 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
1240 {MIIM_GBIT_CONTROL
, MIIM_GBIT_CONTROL_INIT
, NULL
},
1241 {MIIM_ANAR
, MIIM_ANAR_INIT
, NULL
},
1242 /* Configure leds */
1243 {MIIM_88E1121_PHY_LED_CTRL
, miim_read
,
1244 &mii_88E1121_set_led
},
1245 {MIIM_CONTROL
, MIIM_CONTROL_INIT
, &mii_cr_init
},
1246 /* Disable IRQs and de-assert interrupt */
1247 {MIIM_88E1121_PHY_IRQ_EN
, 0, NULL
},
1248 {MIIM_88E1121_PHY_IRQ_STATUS
, miim_read
, NULL
},
1251 (struct phy_cmd
[]){ /* startup */
1252 /* Status is read once to clear old link state */
1253 {MIIM_STATUS
, miim_read
, NULL
},
1254 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
1255 {MIIM_STATUS
, miim_read
, &mii_parse_link
},
1258 (struct phy_cmd
[]){ /* shutdown */
1263 static unsigned int m88e1145_setmode(uint mii_reg
, struct tsec_private
*priv
)
1265 uint mii_data
= read_phy_reg(priv
, mii_reg
);
1267 /* Setting MIIM_88E1145_PHY_EXT_CR */
1268 if (priv
->flags
& TSEC_REDUCED
)
1270 MIIM_M88E1145_RGMII_RX_DELAY
| MIIM_M88E1145_RGMII_TX_DELAY
;
1275 static struct phy_info phy_info_M88E1145
= {
1279 (struct phy_cmd
[]){ /* config */
1281 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
1289 /* Configure the PHY */
1290 {MIIM_GBIT_CONTROL
, MIIM_GBIT_CONTROL_INIT
, NULL
},
1291 {MIIM_ANAR
, MIIM_ANAR_INIT
, NULL
},
1292 {MIIM_88E1011_PHY_SCR
, MIIM_88E1011_PHY_MDI_X_AUTO
,
1294 {MIIM_88E1145_PHY_EXT_CR
, 0, &m88e1145_setmode
},
1295 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
1296 {MIIM_CONTROL
, MIIM_CONTROL_INIT
, NULL
},
1299 (struct phy_cmd
[]){ /* startup */
1300 /* Status is read once to clear old link state */
1301 {MIIM_STATUS
, miim_read
, NULL
},
1302 /* Auto-negotiate */
1303 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
1304 {MIIM_88E1111_PHY_LED_CONTROL
,
1305 MIIM_88E1111_PHY_LED_DIRECT
, NULL
},
1306 /* Read the Status */
1307 {MIIM_88E1011_PHY_STATUS
, miim_read
,
1308 &mii_parse_88E1011_psr
},
1311 (struct phy_cmd
[]){ /* shutdown */
1316 struct phy_info phy_info_cis8204
= {
1320 (struct phy_cmd
[]){ /* config */
1321 /* Override PHY config settings */
1322 {MIIM_CIS8201_AUX_CONSTAT
,
1323 MIIM_CIS8201_AUXCONSTAT_INIT
, NULL
},
1324 /* Configure some basic stuff */
1325 {MIIM_CONTROL
, MIIM_CONTROL_INIT
, &mii_cr_init
},
1326 {MIIM_CIS8204_SLED_CON
, MIIM_CIS8204_SLEDCON_INIT
,
1327 &mii_cis8204_fixled
},
1328 {MIIM_CIS8204_EPHY_CON
, MIIM_CIS8204_EPHYCON_INIT
,
1329 &mii_cis8204_setmode
},
1332 (struct phy_cmd
[]){ /* startup */
1333 /* Read the Status (2x to make sure link is right) */
1334 {MIIM_STATUS
, miim_read
, NULL
},
1335 /* Auto-negotiate */
1336 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
1337 /* Read the status */
1338 {MIIM_CIS8201_AUX_CONSTAT
, miim_read
,
1339 &mii_parse_cis8201
},
1342 (struct phy_cmd
[]){ /* shutdown */
1348 struct phy_info phy_info_cis8201
= {
1352 (struct phy_cmd
[]){ /* config */
1353 /* Override PHY config settings */
1354 {MIIM_CIS8201_AUX_CONSTAT
,
1355 MIIM_CIS8201_AUXCONSTAT_INIT
, NULL
},
1356 /* Set up the interface mode */
1357 {MIIM_CIS8201_EXT_CON1
, MIIM_CIS8201_EXTCON1_INIT
,
1359 /* Configure some basic stuff */
1360 {MIIM_CONTROL
, MIIM_CONTROL_INIT
, &mii_cr_init
},
1363 (struct phy_cmd
[]){ /* startup */
1364 /* Read the Status (2x to make sure link is right) */
1365 {MIIM_STATUS
, miim_read
, NULL
},
1366 /* Auto-negotiate */
1367 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
1368 /* Read the status */
1369 {MIIM_CIS8201_AUX_CONSTAT
, miim_read
,
1370 &mii_parse_cis8201
},
1373 (struct phy_cmd
[]){ /* shutdown */
1377 struct phy_info phy_info_VSC8211
= {
1381 (struct phy_cmd
[]) { /* config */
1382 /* Override PHY config settings */
1383 {MIIM_CIS8201_AUX_CONSTAT
,
1384 MIIM_CIS8201_AUXCONSTAT_INIT
, NULL
},
1385 /* Set up the interface mode */
1386 {MIIM_CIS8201_EXT_CON1
,
1387 MIIM_CIS8201_EXTCON1_INIT
, NULL
},
1388 /* Configure some basic stuff */
1389 {MIIM_CONTROL
, MIIM_CONTROL_INIT
, &mii_cr_init
},
1392 (struct phy_cmd
[]) { /* startup */
1393 /* Read the Status (2x to make sure link is right) */
1394 {MIIM_STATUS
, miim_read
, NULL
},
1395 /* Auto-negotiate */
1396 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
1397 /* Read the status */
1398 {MIIM_CIS8201_AUX_CONSTAT
, miim_read
,
1399 &mii_parse_cis8201
},
1402 (struct phy_cmd
[]) { /* shutdown */
1406 struct phy_info phy_info_VSC8244
= {
1410 (struct phy_cmd
[]){ /* config */
1411 /* Override PHY config settings */
1412 /* Configure some basic stuff */
1413 {MIIM_CONTROL
, MIIM_CONTROL_INIT
, &mii_cr_init
},
1416 (struct phy_cmd
[]){ /* startup */
1417 /* Read the Status (2x to make sure link is right) */
1418 {MIIM_STATUS
, miim_read
, NULL
},
1419 /* Auto-negotiate */
1420 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
1421 /* Read the status */
1422 {MIIM_VSC8244_AUX_CONSTAT
, miim_read
,
1423 &mii_parse_vsc8244
},
1426 (struct phy_cmd
[]){ /* shutdown */
1431 struct phy_info phy_info_VSC8641
= {
1435 (struct phy_cmd
[]){ /* config */
1436 /* Configure some basic stuff */
1437 {MIIM_CONTROL
, MIIM_CONTROL_INIT
, &mii_cr_init
},
1440 (struct phy_cmd
[]){ /* startup */
1441 /* Read the Status (2x to make sure link is right) */
1442 {MIIM_STATUS
, miim_read
, NULL
},
1443 /* Auto-negotiate */
1444 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
1445 /* Read the status */
1446 {MIIM_VSC8244_AUX_CONSTAT
, miim_read
,
1447 &mii_parse_vsc8244
},
1450 (struct phy_cmd
[]){ /* shutdown */
1455 struct phy_info phy_info_VSC8221
= {
1459 (struct phy_cmd
[]){ /* config */
1460 /* Configure some basic stuff */
1461 {MIIM_CONTROL
, MIIM_CONTROL_INIT
, &mii_cr_init
},
1464 (struct phy_cmd
[]){ /* startup */
1465 /* Read the Status (2x to make sure link is right) */
1466 {MIIM_STATUS
, miim_read
, NULL
},
1467 /* Auto-negotiate */
1468 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
1469 /* Read the status */
1470 {MIIM_VSC8244_AUX_CONSTAT
, miim_read
,
1471 &mii_parse_vsc8244
},
1474 (struct phy_cmd
[]){ /* shutdown */
1479 struct phy_info phy_info_VSC8601
= {
1483 (struct phy_cmd
[]){ /* config */
1484 /* Override PHY config settings */
1485 /* Configure some basic stuff */
1486 {MIIM_CONTROL
, MIIM_CONTROL_INIT
, &mii_cr_init
},
1487 #ifdef CONFIG_SYS_VSC8601_SKEWFIX
1488 {MIIM_VSC8601_EPHY_CON
,MIIM_VSC8601_EPHY_CON_INIT_SKEW
,NULL
},
1489 #if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX)
1490 {MIIM_EXT_PAGE_ACCESS
,1,NULL
},
1491 #define VSC8101_SKEW (CONFIG_SYS_VSC8601_SKEW_TX<<14)|(CONFIG_SYS_VSC8601_SKEW_RX<<12)
1492 {MIIM_VSC8601_SKEW_CTRL
,VSC8101_SKEW
,NULL
},
1493 {MIIM_EXT_PAGE_ACCESS
,0,NULL
},
1496 {MIIM_ANAR
, MIIM_ANAR_INIT
, NULL
},
1497 {MIIM_CONTROL
, MIIM_CONTROL_RESTART
, &mii_cr_init
},
1500 (struct phy_cmd
[]){ /* startup */
1501 /* Read the Status (2x to make sure link is right) */
1502 {MIIM_STATUS
, miim_read
, NULL
},
1503 /* Auto-negotiate */
1504 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
1505 /* Read the status */
1506 {MIIM_VSC8244_AUX_CONSTAT
, miim_read
,
1507 &mii_parse_vsc8244
},
1510 (struct phy_cmd
[]){ /* shutdown */
1516 struct phy_info phy_info_dm9161
= {
1520 (struct phy_cmd
[]){ /* config */
1521 {MIIM_CONTROL
, MIIM_DM9161_CR_STOP
, NULL
},
1522 /* Do not bypass the scrambler/descrambler */
1523 {MIIM_DM9161_SCR
, MIIM_DM9161_SCR_INIT
, NULL
},
1524 /* Clear 10BTCSR to default */
1525 {MIIM_DM9161_10BTCSR
, MIIM_DM9161_10BTCSR_INIT
,
1527 /* Configure some basic stuff */
1528 {MIIM_CONTROL
, MIIM_CR_INIT
, NULL
},
1529 /* Restart Auto Negotiation */
1530 {MIIM_CONTROL
, MIIM_DM9161_CR_RSTAN
, NULL
},
1533 (struct phy_cmd
[]){ /* startup */
1534 /* Status is read once to clear old link state */
1535 {MIIM_STATUS
, miim_read
, NULL
},
1536 /* Auto-negotiate */
1537 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
1538 /* Read the status */
1539 {MIIM_DM9161_SCSR
, miim_read
,
1540 &mii_parse_dm9161_scsr
},
1543 (struct phy_cmd
[]){ /* shutdown */
1547 /* a generic flavor. */
1548 struct phy_info phy_info_generic
= {
1550 "Unknown/Generic PHY",
1552 (struct phy_cmd
[]) { /* config */
1553 {PHY_BMCR
, PHY_BMCR_RESET
, NULL
},
1554 {PHY_BMCR
, PHY_BMCR_AUTON
|PHY_BMCR_RST_NEG
, NULL
},
1557 (struct phy_cmd
[]) { /* startup */
1558 {PHY_BMSR
, miim_read
, NULL
},
1559 {PHY_BMSR
, miim_read
, &mii_parse_sr
},
1560 {PHY_BMSR
, miim_read
, &mii_parse_link
},
1563 (struct phy_cmd
[]) { /* shutdown */
1569 uint
mii_parse_lxt971_sr2(uint mii_reg
, struct tsec_private
*priv
)
1573 speed
= mii_reg
& MIIM_LXT971_SR2_SPEED_MASK
;
1576 case MIIM_LXT971_SR2_10HDX
:
1578 priv
->duplexity
= 0;
1580 case MIIM_LXT971_SR2_10FDX
:
1582 priv
->duplexity
= 1;
1584 case MIIM_LXT971_SR2_100HDX
:
1586 priv
->duplexity
= 0;
1590 priv
->duplexity
= 1;
1594 priv
->duplexity
= 0;
1600 static struct phy_info phy_info_lxt971
= {
1604 (struct phy_cmd
[]){ /* config */
1605 {MIIM_CR
, MIIM_CR_INIT
, mii_cr_init
}, /* autonegotiate */
1608 (struct phy_cmd
[]){ /* startup - enable interrupts */
1609 /* { 0x12, 0x00f2, NULL }, */
1610 {MIIM_STATUS
, miim_read
, NULL
},
1611 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
1612 {MIIM_LXT971_SR2
, miim_read
, &mii_parse_lxt971_sr2
},
1615 (struct phy_cmd
[]){ /* shutdown - disable interrupts */
1620 /* Parse the DP83865's link and auto-neg status register for speed and duplex
1623 uint
mii_parse_dp83865_lanr(uint mii_reg
, struct tsec_private
*priv
)
1625 switch (mii_reg
& MIIM_DP83865_SPD_MASK
) {
1627 case MIIM_DP83865_SPD_1000
:
1631 case MIIM_DP83865_SPD_100
:
1641 if (mii_reg
& MIIM_DP83865_DPX_FULL
)
1642 priv
->duplexity
= 1;
1644 priv
->duplexity
= 0;
1649 struct phy_info phy_info_dp83865
= {
1653 (struct phy_cmd
[]){ /* config */
1654 {MIIM_CONTROL
, MIIM_DP83865_CR_INIT
, NULL
},
1657 (struct phy_cmd
[]){ /* startup */
1658 /* Status is read once to clear old link state */
1659 {MIIM_STATUS
, miim_read
, NULL
},
1660 /* Auto-negotiate */
1661 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
1662 /* Read the link and auto-neg status */
1663 {MIIM_DP83865_LANR
, miim_read
,
1664 &mii_parse_dp83865_lanr
},
1667 (struct phy_cmd
[]){ /* shutdown */
1672 struct phy_info phy_info_rtl8211b
= {
1676 (struct phy_cmd
[]){ /* config */
1677 /* Reset and configure the PHY */
1678 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
1679 {MIIM_GBIT_CONTROL
, MIIM_GBIT_CONTROL_INIT
, NULL
},
1680 {MIIM_ANAR
, MIIM_ANAR_INIT
, NULL
},
1681 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
1682 {MIIM_CONTROL
, MIIM_CONTROL_INIT
, &mii_cr_init
},
1685 (struct phy_cmd
[]){ /* startup */
1686 /* Status is read once to clear old link state */
1687 {MIIM_STATUS
, miim_read
, NULL
},
1688 /* Auto-negotiate */
1689 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
1690 /* Read the status */
1691 {MIIM_RTL8211B_PHY_STATUS
, miim_read
, &mii_parse_RTL8211B_sr
},
1694 (struct phy_cmd
[]){ /* shutdown */
1699 struct phy_info
*phy_info
[] = {
1705 &phy_info_M88E1011S
,
1706 &phy_info_M88E1111S
,
1708 &phy_info_M88E1121R
,
1710 &phy_info_M88E1149S
,
1720 &phy_info_generic
, /* must be last; has ID 0 and 32 bit mask */
1724 /* Grab the identifier of the device's PHY, and search through
1725 * all of the known PHYs to see if one matches. If so, return
1726 * it, if not, return NULL
1728 struct phy_info
*get_phy_info(struct eth_device
*dev
)
1730 struct tsec_private
*priv
= (struct tsec_private
*)dev
->priv
;
1731 uint phy_reg
, phy_ID
;
1733 struct phy_info
*theInfo
= NULL
;
1735 /* Grab the bits from PHYIR1, and put them in the upper half */
1736 phy_reg
= read_phy_reg(priv
, MIIM_PHYIR1
);
1737 phy_ID
= (phy_reg
& 0xffff) << 16;
1739 /* Grab the bits from PHYIR2, and put them in the lower half */
1740 phy_reg
= read_phy_reg(priv
, MIIM_PHYIR2
);
1741 phy_ID
|= (phy_reg
& 0xffff);
1743 /* loop through all the known PHY types, and find one that */
1744 /* matches the ID we read from the PHY. */
1745 for (i
= 0; phy_info
[i
]; i
++) {
1746 if (phy_info
[i
]->id
== (phy_ID
>> phy_info
[i
]->shift
)) {
1747 theInfo
= phy_info
[i
];
1752 if (theInfo
== &phy_info_generic
) {
1753 printf("%s: No support for PHY id %x; assuming generic\n", dev
->name
, phy_ID
);
1755 debug("%s: PHY is %s (%x)\n", dev
->name
, theInfo
->name
, phy_ID
);
1761 /* Execute the given series of commands on the given device's
1762 * PHY, running functions as necessary
1764 void phy_run_commands(struct tsec_private
*priv
, struct phy_cmd
*cmd
)
1768 volatile tsec_mdio_t
*phyregs
= priv
->phyregs
;
1770 phyregs
->miimcfg
= MIIMCFG_RESET
;
1772 phyregs
->miimcfg
= MIIMCFG_INIT_VALUE
;
1774 while (phyregs
->miimind
& MIIMIND_BUSY
) ;
1776 for (i
= 0; cmd
->mii_reg
!= miim_end
; i
++) {
1777 if (cmd
->mii_data
== miim_read
) {
1778 result
= read_phy_reg(priv
, cmd
->mii_reg
);
1780 if (cmd
->funct
!= NULL
)
1781 (*(cmd
->funct
)) (result
, priv
);
1784 if (cmd
->funct
!= NULL
)
1785 result
= (*(cmd
->funct
)) (cmd
->mii_reg
, priv
);
1787 result
= cmd
->mii_data
;
1789 write_phy_reg(priv
, cmd
->mii_reg
, result
);
1796 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
1797 && !defined(BITBANGMII)
1800 * Read a MII PHY register.
1805 static int tsec_miiphy_read(char *devname
, unsigned char addr
,
1806 unsigned char reg
, unsigned short *value
)
1809 struct tsec_private
*priv
= privlist
[0];
1812 printf("Can't read PHY at address %d\n", addr
);
1816 ret
= (unsigned short)tsec_local_mdio_read(priv
->phyregs
, addr
, reg
);
1823 * Write a MII PHY register.
1828 static int tsec_miiphy_write(char *devname
, unsigned char addr
,
1829 unsigned char reg
, unsigned short value
)
1831 struct tsec_private
*priv
= privlist
[0];
1834 printf("Can't write PHY at address %d\n", addr
);
1838 tsec_local_mdio_write(priv
->phyregs
, addr
, reg
, value
);
1845 #ifdef CONFIG_MCAST_TFTP
1847 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
1849 /* Set the appropriate hash bit for the given addr */
1851 /* The algorithm works like so:
1852 * 1) Take the Destination Address (ie the multicast address), and
1853 * do a CRC on it (little endian), and reverse the bits of the
1855 * 2) Use the 8 most significant bits as a hash into a 256-entry
1856 * table. The table is controlled through 8 32-bit registers:
1857 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
1858 * gaddr7. This means that the 3 most significant bits in the
1859 * hash index which gaddr register to use, and the 5 other bits
1860 * indicate which bit (assuming an IBM numbering scheme, which
1861 * for PowerPC (tm) is usually the case) in the tregister holds
1864 tsec_mcast_addr (struct eth_device
*dev
, u8 mcast_mac
, u8 set
)
1866 struct tsec_private
*priv
= privlist
[1];
1867 volatile tsec_t
*regs
= priv
->regs
;
1868 volatile u32
*reg_array
, value
;
1869 u8 result
, whichbit
, whichreg
;
1871 result
= (u8
)((ether_crc(MAC_ADDR_LEN
,mcast_mac
) >> 24) & 0xff);
1872 whichbit
= result
& 0x1f; /* the 5 LSB = which bit to set */
1873 whichreg
= result
>> 5; /* the 3 MSB = which reg to set it in */
1874 value
= (1 << (31-whichbit
));
1876 reg_array
= &(regs
->hash
.gaddr0
);
1879 reg_array
[whichreg
] |= value
;
1881 reg_array
[whichreg
] &= ~value
;
1885 #endif /* Multicast TFTP ? */