2 * Freescale Three Speed Ethernet Controller driver
4 * This software may be used and distributed according to the
5 * terms of the GNU Public License, Version 2, incorporated
8 * Copyright 2004, 2007 Freescale Semiconductor, Inc.
9 * (C) Copyright 2003, Motorola, Inc.
20 #if defined(CONFIG_TSEC_ENET)
24 DECLARE_GLOBAL_DATA_PTR
;
28 static uint rxIdx
; /* index of the current RX buffer */
29 static uint txIdx
; /* index of the current TX buffer */
31 typedef volatile struct rtxbd
{
32 txbd8_t txbd
[TX_BUF_CNT
];
33 rxbd8_t rxbd
[PKTBUFSRX
];
36 struct tsec_info_struct
{
39 unsigned int phyregidx
;
42 /* The tsec_info structure contains 3 values which the
43 * driver uses to determine how to operate a given ethernet
44 * device. The information needed is:
45 * phyaddr - The address of the PHY which is attached to
48 * flags - This variable indicates whether the device
49 * supports gigabit speed ethernet, and whether it should be
52 * phyregidx - This variable specifies which ethernet device
53 * controls the MII Management registers which are connected
54 * to the PHY. For now, only TSEC1 (index 0) has
55 * access to the PHYs, so all of the entries have "0".
57 * The values specified in the table are taken from the board's
58 * config file in include/configs/. When implementing a new
59 * board with ethernet capability, it is necessary to define:
63 * for n = 1,2,3, etc. And for FEC:
67 static struct tsec_info_struct tsec_info
[] = {
69 {TSEC1_PHY_ADDR
, TSEC1_FLAGS
, TSEC1_PHYIDX
},
74 {TSEC2_PHY_ADDR
, TSEC2_FLAGS
, TSEC2_PHYIDX
},
78 #ifdef CONFIG_MPC85XX_FEC
79 {FEC_PHY_ADDR
, FEC_FLAGS
, FEC_PHYIDX
},
82 {TSEC3_PHY_ADDR
, TSEC3_FLAGS
, TSEC3_PHYIDX
},
87 {TSEC4_PHY_ADDR
, TSEC4_FLAGS
, TSEC4_PHYIDX
},
90 #endif /* CONFIG_TSEC4 */
91 #endif /* CONFIG_MPC85XX_FEC */
94 #define MAXCONTROLLERS (4)
96 static int relocated
= 0;
98 static struct tsec_private
*privlist
[MAXCONTROLLERS
];
101 static RTXBD rtx
__attribute__ ((aligned(8)));
103 #error "rtx must be 64-bit aligned"
106 static int tsec_send(struct eth_device
*dev
,
107 volatile void *packet
, int length
);
108 static int tsec_recv(struct eth_device
*dev
);
109 static int tsec_init(struct eth_device
*dev
, bd_t
* bd
);
110 static void tsec_halt(struct eth_device
*dev
);
111 static void init_registers(volatile tsec_t
* regs
);
112 static void startup_tsec(struct eth_device
*dev
);
113 static int init_phy(struct eth_device
*dev
);
114 void write_phy_reg(struct tsec_private
*priv
, uint regnum
, uint value
);
115 uint
read_phy_reg(struct tsec_private
*priv
, uint regnum
);
116 struct phy_info
*get_phy_info(struct eth_device
*dev
);
117 void phy_run_commands(struct tsec_private
*priv
, struct phy_cmd
*cmd
);
118 static void adjust_link(struct eth_device
*dev
);
119 static void relocate_cmds(void);
120 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
121 && !defined(BITBANGMII)
122 static int tsec_miiphy_write(char *devname
, unsigned char addr
,
123 unsigned char reg
, unsigned short value
);
124 static int tsec_miiphy_read(char *devname
, unsigned char addr
,
125 unsigned char reg
, unsigned short *value
);
127 #ifdef CONFIG_MCAST_TFTP
128 static int tsec_mcast_addr (struct eth_device
*dev
, u8 mcast_mac
, u8 set
);
131 /* Initialize device structure. Returns success if PHY
132 * initialization succeeded (i.e. if it recognizes the PHY)
134 int tsec_initialize(bd_t
* bis
, int index
, char *devname
)
136 struct eth_device
*dev
;
138 struct tsec_private
*priv
;
140 dev
= (struct eth_device
*)malloc(sizeof *dev
);
145 memset(dev
, 0, sizeof *dev
);
147 priv
= (struct tsec_private
*)malloc(sizeof(*priv
));
152 privlist
[index
] = priv
;
153 priv
->regs
= (volatile tsec_t
*)(TSEC_BASE_ADDR
+ index
* TSEC_SIZE
);
154 priv
->phyregs
= (volatile tsec_t
*)(TSEC_BASE_ADDR
+
155 tsec_info
[index
].phyregidx
*
158 priv
->phyaddr
= tsec_info
[index
].phyaddr
;
159 priv
->flags
= tsec_info
[index
].flags
;
161 sprintf(dev
->name
, devname
);
164 dev
->init
= tsec_init
;
165 dev
->halt
= tsec_halt
;
166 dev
->send
= tsec_send
;
167 dev
->recv
= tsec_recv
;
168 #ifdef CONFIG_MCAST_TFTP
169 dev
->mcast
= tsec_mcast_addr
;
172 /* Tell u-boot to get the addr from the env */
173 for (i
= 0; i
< 6; i
++)
174 dev
->enetaddr
[i
] = 0;
179 priv
->regs
->maccfg1
|= MACCFG1_SOFT_RESET
;
180 priv
->regs
->maccfg1
&= ~(MACCFG1_SOFT_RESET
);
182 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
183 && !defined(BITBANGMII)
184 miiphy_register(dev
->name
, tsec_miiphy_read
, tsec_miiphy_write
);
187 /* Try to initialize PHY here, and return */
188 return init_phy(dev
);
191 /* Initializes data structures and registers for the controller,
192 * and brings the interface up. Returns the link status, meaning
193 * that it returns success if the link is up, failure otherwise.
194 * This allows u-boot to find the first active controller.
196 int tsec_init(struct eth_device
*dev
, bd_t
* bd
)
199 char tmpbuf
[MAC_ADDR_LEN
];
201 struct tsec_private
*priv
= (struct tsec_private
*)dev
->priv
;
202 volatile tsec_t
*regs
= priv
->regs
;
204 /* Make sure the controller is stopped */
207 /* Init MACCFG2. Defaults to GMII */
208 regs
->maccfg2
= MACCFG2_INIT_SETTINGS
;
211 regs
->ecntrl
= ECNTRL_INIT_SETTINGS
;
213 /* Copy the station address into the address registers.
214 * Backwards, because little endian MACS are dumb */
215 for (i
= 0; i
< MAC_ADDR_LEN
; i
++) {
216 tmpbuf
[MAC_ADDR_LEN
- 1 - i
] = dev
->enetaddr
[i
];
218 regs
->macstnaddr1
= *((uint
*) (tmpbuf
));
220 tempval
= *((uint
*) (tmpbuf
+ 4));
222 regs
->macstnaddr2
= tempval
;
224 /* reset the indices to zero */
228 /* Clear out (for the most part) the other registers */
229 init_registers(regs
);
231 /* Ready the device for tx/rx */
234 /* If there's no link, fail */
239 /* Write value to the device's PHY through the registers
240 * specified in priv, modifying the register specified in regnum.
241 * It will wait for the write to be done (or for a timeout to
242 * expire) before exiting
244 void write_phy_reg(struct tsec_private
*priv
, uint regnum
, uint value
)
246 volatile tsec_t
*regbase
= priv
->phyregs
;
247 uint phyid
= priv
->phyaddr
;
248 int timeout
= 1000000;
250 regbase
->miimadd
= (phyid
<< 8) | regnum
;
251 regbase
->miimcon
= value
;
255 while ((regbase
->miimind
& MIIMIND_BUSY
) && timeout
--) ;
258 /* Reads register regnum on the device's PHY through the
259 * registers specified in priv. It lowers and raises the read
260 * command, and waits for the data to become valid (miimind
261 * notvalid bit cleared), and the bus to cease activity (miimind
262 * busy bit cleared), and then returns the value
264 uint
read_phy_reg(struct tsec_private
*priv
, uint regnum
)
267 volatile tsec_t
*regbase
= priv
->phyregs
;
268 uint phyid
= priv
->phyaddr
;
270 /* Put the address of the phy, and the register
271 * number into MIIMADD */
272 regbase
->miimadd
= (phyid
<< 8) | regnum
;
274 /* Clear the command register, and wait */
275 regbase
->miimcom
= 0;
278 /* Initiate a read command, and wait */
279 regbase
->miimcom
= MIIM_READ_COMMAND
;
282 /* Wait for the the indication that the read is done */
283 while ((regbase
->miimind
& (MIIMIND_NOTVALID
| MIIMIND_BUSY
))) ;
285 /* Grab the value read from the PHY */
286 value
= regbase
->miimstat
;
291 /* Discover which PHY is attached to the device, and configure it
292 * properly. If the PHY is not recognized, then return 0
293 * (failure). Otherwise, return 1
295 static int init_phy(struct eth_device
*dev
)
297 struct tsec_private
*priv
= (struct tsec_private
*)dev
->priv
;
298 struct phy_info
*curphy
;
299 volatile tsec_t
*regs
= (volatile tsec_t
*)(TSEC_BASE_ADDR
);
301 /* Assign a Physical address to the TBI */
302 regs
->tbipa
= CFG_TBIPA_VALUE
;
303 regs
= (volatile tsec_t
*)(TSEC_BASE_ADDR
+ TSEC_SIZE
);
304 regs
->tbipa
= CFG_TBIPA_VALUE
;
307 /* Reset MII (due to new addresses) */
308 priv
->phyregs
->miimcfg
= MIIMCFG_RESET
;
310 priv
->phyregs
->miimcfg
= MIIMCFG_INIT_VALUE
;
312 while (priv
->phyregs
->miimind
& MIIMIND_BUSY
) ;
317 /* Get the cmd structure corresponding to the attached
319 curphy
= get_phy_info(dev
);
321 if (curphy
== NULL
) {
322 priv
->phyinfo
= NULL
;
323 printf("%s: No PHY found\n", dev
->name
);
328 priv
->phyinfo
= curphy
;
330 phy_run_commands(priv
, priv
->phyinfo
->config
);
336 * Returns which value to write to the control register.
337 * For 10/100, the value is slightly different
339 uint
mii_cr_init(uint mii_reg
, struct tsec_private
* priv
)
341 if (priv
->flags
& TSEC_GIGABIT
)
342 return MIIM_CONTROL_INIT
;
347 /* Parse the status register for link, and then do
350 uint
mii_parse_sr(uint mii_reg
, struct tsec_private
* priv
)
353 * Wait if the link is up, and autonegotiation is in progress
354 * (ie - we're capable and it's not done)
356 mii_reg
= read_phy_reg(priv
, MIIM_STATUS
);
357 if ((mii_reg
& MIIM_STATUS_LINK
) && (mii_reg
& PHY_BMSR_AUTN_ABLE
)
358 && !(mii_reg
& PHY_BMSR_AUTN_COMP
)) {
361 puts("Waiting for PHY auto negotiation to complete");
362 while (!(mii_reg
& PHY_BMSR_AUTN_COMP
)) {
366 if (i
> PHY_AUTONEGOTIATE_TIMEOUT
) {
367 puts(" TIMEOUT !\n");
372 if ((i
++ % 1000) == 0) {
375 udelay(1000); /* 1 ms */
376 mii_reg
= read_phy_reg(priv
, MIIM_STATUS
);
380 udelay(500000); /* another 500 ms (results in faster booting) */
382 if (mii_reg
& MIIM_STATUS_LINK
)
391 /* Generic function which updates the speed and duplex. If
392 * autonegotiation is enabled, it uses the AND of the link
393 * partner's advertised capabilities and our advertised
394 * capabilities. If autonegotiation is disabled, we use the
395 * appropriate bits in the control register.
397 * Stolen from Linux's mii.c and phy_device.c
399 uint
mii_parse_link(uint mii_reg
, struct tsec_private
*priv
)
401 /* We're using autonegotiation */
402 if (mii_reg
& PHY_BMSR_AUTN_ABLE
) {
406 /* Check for gigabit capability */
407 if (mii_reg
& PHY_BMSR_EXT
) {
408 /* We want a list of states supported by
409 * both PHYs in the link
411 gblpa
= read_phy_reg(priv
, PHY_1000BTSR
);
412 gblpa
&= read_phy_reg(priv
, PHY_1000BTCR
) << 2;
415 /* Set the baseline so we only have to set them
416 * if they're different
421 /* Check the gigabit fields */
422 if (gblpa
& (PHY_1000BTSR_1000FD
| PHY_1000BTSR_1000HD
)) {
425 if (gblpa
& PHY_1000BTSR_1000FD
)
432 lpa
= read_phy_reg(priv
, PHY_ANAR
);
433 lpa
&= read_phy_reg(priv
, PHY_ANLPAR
);
435 if (lpa
& (PHY_ANLPAR_TXFD
| PHY_ANLPAR_TX
)) {
438 if (lpa
& PHY_ANLPAR_TXFD
)
441 } else if (lpa
& PHY_ANLPAR_10FD
)
444 uint bmcr
= read_phy_reg(priv
, PHY_BMCR
);
449 if (bmcr
& PHY_BMCR_DPLX
)
452 if (bmcr
& PHY_BMCR_1000_MBPS
)
454 else if (bmcr
& PHY_BMCR_100_MBPS
)
462 * Parse the BCM54xx status register for speed and duplex information.
463 * The linux sungem_phy has this information, but in a table format.
465 uint
mii_parse_BCM54xx_sr(uint mii_reg
, struct tsec_private
*priv
)
468 switch((mii_reg
& MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK
) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT
){
471 printf("Enet starting in 10BT/HD\n");
477 printf("Enet starting in 10BT/FD\n");
483 printf("Enet starting in 100BT/HD\n");
489 printf("Enet starting in 100BT/FD\n");
495 printf("Enet starting in 1000BT/HD\n");
501 printf("Enet starting in 1000BT/FD\n");
507 printf("Auto-neg error, defaulting to 10BT/HD\n");
516 /* Parse the 88E1011's status register for speed and duplex
519 uint
mii_parse_88E1011_psr(uint mii_reg
, struct tsec_private
* priv
)
523 mii_reg
= read_phy_reg(priv
, MIIM_88E1011_PHY_STATUS
);
525 if ((mii_reg
& MIIM_88E1011_PHYSTAT_LINK
) &&
526 !(mii_reg
& MIIM_88E1011_PHYSTAT_SPDDONE
)) {
529 puts("Waiting for PHY realtime link");
530 while (!(mii_reg
& MIIM_88E1011_PHYSTAT_SPDDONE
)) {
531 /* Timeout reached ? */
532 if (i
> PHY_AUTONEGOTIATE_TIMEOUT
) {
533 puts(" TIMEOUT !\n");
538 if ((i
++ % 1000) == 0) {
541 udelay(1000); /* 1 ms */
542 mii_reg
= read_phy_reg(priv
, MIIM_88E1011_PHY_STATUS
);
545 udelay(500000); /* another 500 ms (results in faster booting) */
547 if (mii_reg
& MIIM_88E1011_PHYSTAT_LINK
)
553 if (mii_reg
& MIIM_88E1011_PHYSTAT_DUPLEX
)
558 speed
= (mii_reg
& MIIM_88E1011_PHYSTAT_SPEED
);
561 case MIIM_88E1011_PHYSTAT_GBIT
:
564 case MIIM_88E1011_PHYSTAT_100
:
574 /* Parse the cis8201's status register for speed and duplex
577 uint
mii_parse_cis8201(uint mii_reg
, struct tsec_private
* priv
)
581 if (mii_reg
& MIIM_CIS8201_AUXCONSTAT_DUPLEX
)
586 speed
= mii_reg
& MIIM_CIS8201_AUXCONSTAT_SPEED
;
588 case MIIM_CIS8201_AUXCONSTAT_GBIT
:
591 case MIIM_CIS8201_AUXCONSTAT_100
:
602 /* Parse the vsc8244's status register for speed and duplex
605 uint
mii_parse_vsc8244(uint mii_reg
, struct tsec_private
* priv
)
609 if (mii_reg
& MIIM_VSC8244_AUXCONSTAT_DUPLEX
)
614 speed
= mii_reg
& MIIM_VSC8244_AUXCONSTAT_SPEED
;
616 case MIIM_VSC8244_AUXCONSTAT_GBIT
:
619 case MIIM_VSC8244_AUXCONSTAT_100
:
630 /* Parse the DM9161's status register for speed and duplex
633 uint
mii_parse_dm9161_scsr(uint mii_reg
, struct tsec_private
* priv
)
635 if (mii_reg
& (MIIM_DM9161_SCSR_100F
| MIIM_DM9161_SCSR_100H
))
640 if (mii_reg
& (MIIM_DM9161_SCSR_100F
| MIIM_DM9161_SCSR_10F
))
649 * Hack to write all 4 PHYs with the LED values
651 uint
mii_cis8204_fixled(uint mii_reg
, struct tsec_private
* priv
)
654 volatile tsec_t
*regbase
= priv
->phyregs
;
655 int timeout
= 1000000;
657 for (phyid
= 0; phyid
< 4; phyid
++) {
658 regbase
->miimadd
= (phyid
<< 8) | mii_reg
;
659 regbase
->miimcon
= MIIM_CIS8204_SLEDCON_INIT
;
663 while ((regbase
->miimind
& MIIMIND_BUSY
) && timeout
--) ;
666 return MIIM_CIS8204_SLEDCON_INIT
;
669 uint
mii_cis8204_setmode(uint mii_reg
, struct tsec_private
* priv
)
671 if (priv
->flags
& TSEC_REDUCED
)
672 return MIIM_CIS8204_EPHYCON_INIT
| MIIM_CIS8204_EPHYCON_RGMII
;
674 return MIIM_CIS8204_EPHYCON_INIT
;
677 /* Initialized required registers to appropriate values, zeroing
678 * those we don't care about (unless zero is bad, in which case,
679 * choose a more appropriate value)
681 static void init_registers(volatile tsec_t
* regs
)
684 regs
->ievent
= IEVENT_INIT_CLEAR
;
686 regs
->imask
= IMASK_INIT_CLEAR
;
688 regs
->hash
.iaddr0
= 0;
689 regs
->hash
.iaddr1
= 0;
690 regs
->hash
.iaddr2
= 0;
691 regs
->hash
.iaddr3
= 0;
692 regs
->hash
.iaddr4
= 0;
693 regs
->hash
.iaddr5
= 0;
694 regs
->hash
.iaddr6
= 0;
695 regs
->hash
.iaddr7
= 0;
697 regs
->hash
.gaddr0
= 0;
698 regs
->hash
.gaddr1
= 0;
699 regs
->hash
.gaddr2
= 0;
700 regs
->hash
.gaddr3
= 0;
701 regs
->hash
.gaddr4
= 0;
702 regs
->hash
.gaddr5
= 0;
703 regs
->hash
.gaddr6
= 0;
704 regs
->hash
.gaddr7
= 0;
706 regs
->rctrl
= 0x00000000;
708 /* Init RMON mib registers */
709 memset((void *)&(regs
->rmon
), 0, sizeof(rmon_mib_t
));
711 regs
->rmon
.cam1
= 0xffffffff;
712 regs
->rmon
.cam2
= 0xffffffff;
714 regs
->mrblr
= MRBLR_INIT_SETTINGS
;
716 regs
->minflr
= MINFLR_INIT_SETTINGS
;
718 regs
->attr
= ATTR_INIT_SETTINGS
;
719 regs
->attreli
= ATTRELI_INIT_SETTINGS
;
723 /* Configure maccfg2 based on negotiated speed and duplex
724 * reported by PHY handling code
726 static void adjust_link(struct eth_device
*dev
)
728 struct tsec_private
*priv
= (struct tsec_private
*)dev
->priv
;
729 volatile tsec_t
*regs
= priv
->regs
;
732 if (priv
->duplexity
!= 0)
733 regs
->maccfg2
|= MACCFG2_FULL_DUPLEX
;
735 regs
->maccfg2
&= ~(MACCFG2_FULL_DUPLEX
);
737 switch (priv
->speed
) {
739 regs
->maccfg2
= ((regs
->maccfg2
& ~(MACCFG2_IF
))
744 regs
->maccfg2
= ((regs
->maccfg2
& ~(MACCFG2_IF
))
747 /* Set R100 bit in all modes although
748 * it is only used in RGMII mode
750 if (priv
->speed
== 100)
751 regs
->ecntrl
|= ECNTRL_R100
;
753 regs
->ecntrl
&= ~(ECNTRL_R100
);
756 printf("%s: Speed was bad\n", dev
->name
);
760 printf("Speed: %d, %s duplex\n", priv
->speed
,
761 (priv
->duplexity
) ? "full" : "half");
764 printf("%s: No link.\n", dev
->name
);
768 /* Set up the buffers and their descriptors, and bring up the
771 static void startup_tsec(struct eth_device
*dev
)
774 struct tsec_private
*priv
= (struct tsec_private
*)dev
->priv
;
775 volatile tsec_t
*regs
= priv
->regs
;
777 /* Point to the buffer descriptors */
778 regs
->tbase
= (unsigned int)(&rtx
.txbd
[txIdx
]);
779 regs
->rbase
= (unsigned int)(&rtx
.rxbd
[rxIdx
]);
781 /* Initialize the Rx Buffer descriptors */
782 for (i
= 0; i
< PKTBUFSRX
; i
++) {
783 rtx
.rxbd
[i
].status
= RXBD_EMPTY
;
784 rtx
.rxbd
[i
].length
= 0;
785 rtx
.rxbd
[i
].bufPtr
= (uint
) NetRxPackets
[i
];
787 rtx
.rxbd
[PKTBUFSRX
- 1].status
|= RXBD_WRAP
;
789 /* Initialize the TX Buffer Descriptors */
790 for (i
= 0; i
< TX_BUF_CNT
; i
++) {
791 rtx
.txbd
[i
].status
= 0;
792 rtx
.txbd
[i
].length
= 0;
793 rtx
.txbd
[i
].bufPtr
= 0;
795 rtx
.txbd
[TX_BUF_CNT
- 1].status
|= TXBD_WRAP
;
797 /* Start up the PHY */
799 phy_run_commands(priv
, priv
->phyinfo
->startup
);
803 /* Enable Transmit and Receive */
804 regs
->maccfg1
|= (MACCFG1_RX_EN
| MACCFG1_TX_EN
);
806 /* Tell the DMA it is clear to go */
807 regs
->dmactrl
|= DMACTRL_INIT_SETTINGS
;
808 regs
->tstat
= TSTAT_CLEAR_THALT
;
809 regs
->rstat
= RSTAT_CLEAR_RHALT
;
810 regs
->dmactrl
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
813 /* This returns the status bits of the device. The return value
814 * is never checked, and this is what the 8260 driver did, so we
815 * do the same. Presumably, this would be zero if there were no
818 static int tsec_send(struct eth_device
*dev
, volatile void *packet
, int length
)
822 struct tsec_private
*priv
= (struct tsec_private
*)dev
->priv
;
823 volatile tsec_t
*regs
= priv
->regs
;
825 /* Find an empty buffer descriptor */
826 for (i
= 0; rtx
.txbd
[txIdx
].status
& TXBD_READY
; i
++) {
827 if (i
>= TOUT_LOOP
) {
828 debug("%s: tsec: tx buffers full\n", dev
->name
);
833 rtx
.txbd
[txIdx
].bufPtr
= (uint
) packet
;
834 rtx
.txbd
[txIdx
].length
= length
;
835 rtx
.txbd
[txIdx
].status
|=
836 (TXBD_READY
| TXBD_LAST
| TXBD_CRC
| TXBD_INTERRUPT
);
838 /* Tell the DMA to go */
839 regs
->tstat
= TSTAT_CLEAR_THALT
;
841 /* Wait for buffer to be transmitted */
842 for (i
= 0; rtx
.txbd
[txIdx
].status
& TXBD_READY
; i
++) {
843 if (i
>= TOUT_LOOP
) {
844 debug("%s: tsec: tx error\n", dev
->name
);
849 txIdx
= (txIdx
+ 1) % TX_BUF_CNT
;
850 result
= rtx
.txbd
[txIdx
].status
& TXBD_STATS
;
855 static int tsec_recv(struct eth_device
*dev
)
858 struct tsec_private
*priv
= (struct tsec_private
*)dev
->priv
;
859 volatile tsec_t
*regs
= priv
->regs
;
861 while (!(rtx
.rxbd
[rxIdx
].status
& RXBD_EMPTY
)) {
863 length
= rtx
.rxbd
[rxIdx
].length
;
865 /* Send the packet up if there were no errors */
866 if (!(rtx
.rxbd
[rxIdx
].status
& RXBD_STATS
)) {
867 NetReceive(NetRxPackets
[rxIdx
], length
- 4);
869 printf("Got error %x\n",
870 (rtx
.rxbd
[rxIdx
].status
& RXBD_STATS
));
873 rtx
.rxbd
[rxIdx
].length
= 0;
875 /* Set the wrap bit if this is the last element in the list */
876 rtx
.rxbd
[rxIdx
].status
=
877 RXBD_EMPTY
| (((rxIdx
+ 1) == PKTBUFSRX
) ? RXBD_WRAP
: 0);
879 rxIdx
= (rxIdx
+ 1) % PKTBUFSRX
;
882 if (regs
->ievent
& IEVENT_BSY
) {
883 regs
->ievent
= IEVENT_BSY
;
884 regs
->rstat
= RSTAT_CLEAR_RHALT
;
891 /* Stop the interface */
892 static void tsec_halt(struct eth_device
*dev
)
894 struct tsec_private
*priv
= (struct tsec_private
*)dev
->priv
;
895 volatile tsec_t
*regs
= priv
->regs
;
897 regs
->dmactrl
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
898 regs
->dmactrl
|= (DMACTRL_GRS
| DMACTRL_GTS
);
900 while (!(regs
->ievent
& (IEVENT_GRSC
| IEVENT_GTSC
))) ;
902 regs
->maccfg1
&= ~(MACCFG1_TX_EN
| MACCFG1_RX_EN
);
904 /* Shut down the PHY, as needed */
906 phy_run_commands(priv
, priv
->phyinfo
->shutdown
);
909 struct phy_info phy_info_M88E1149S
= {
913 (struct phy_cmd
[]){ /* config */
914 /* Reset and configure the PHY */
915 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
917 {0x1e, 0x200c, NULL
},
921 {MIIM_GBIT_CONTROL
, MIIM_GBIT_CONTROL_INIT
, NULL
},
922 {MIIM_ANAR
, MIIM_ANAR_INIT
, NULL
},
923 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
924 {MIIM_CONTROL
, MIIM_CONTROL_INIT
, &mii_cr_init
},
927 (struct phy_cmd
[]){ /* startup */
928 /* Status is read once to clear old link state */
929 {MIIM_STATUS
, miim_read
, NULL
},
931 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
932 /* Read the status */
933 {MIIM_88E1011_PHY_STATUS
, miim_read
,
934 &mii_parse_88E1011_psr
},
937 (struct phy_cmd
[]){ /* shutdown */
942 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */
943 struct phy_info phy_info_BCM5461S
= {
944 0x02060c1, /* 5461 ID */
946 0, /* not clear to me what minor revisions we can shift away */
947 (struct phy_cmd
[]) { /* config */
948 /* Reset and configure the PHY */
949 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
950 {MIIM_GBIT_CONTROL
, MIIM_GBIT_CONTROL_INIT
, NULL
},
951 {MIIM_ANAR
, MIIM_ANAR_INIT
, NULL
},
952 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
953 {MIIM_CONTROL
, MIIM_CONTROL_INIT
, &mii_cr_init
},
956 (struct phy_cmd
[]) { /* startup */
957 /* Status is read once to clear old link state */
958 {MIIM_STATUS
, miim_read
, NULL
},
960 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
961 /* Read the status */
962 {MIIM_BCM54xx_AUXSTATUS
, miim_read
, &mii_parse_BCM54xx_sr
},
965 (struct phy_cmd
[]) { /* shutdown */
970 struct phy_info phy_info_BCM5464S
= {
971 0x02060b1, /* 5464 ID */
973 0, /* not clear to me what minor revisions we can shift away */
974 (struct phy_cmd
[]) { /* config */
975 /* Reset and configure the PHY */
976 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
977 {MIIM_GBIT_CONTROL
, MIIM_GBIT_CONTROL_INIT
, NULL
},
978 {MIIM_ANAR
, MIIM_ANAR_INIT
, NULL
},
979 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
980 {MIIM_CONTROL
, MIIM_CONTROL_INIT
, &mii_cr_init
},
983 (struct phy_cmd
[]) { /* startup */
984 /* Status is read once to clear old link state */
985 {MIIM_STATUS
, miim_read
, NULL
},
987 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
988 /* Read the status */
989 {MIIM_BCM54xx_AUXSTATUS
, miim_read
, &mii_parse_BCM54xx_sr
},
992 (struct phy_cmd
[]) { /* shutdown */
997 struct phy_info phy_info_M88E1011S
= {
1001 (struct phy_cmd
[]){ /* config */
1002 /* Reset and configure the PHY */
1003 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
1005 {0x1e, 0x200c, NULL
},
1008 {0x1e, 0x100, NULL
},
1009 {MIIM_GBIT_CONTROL
, MIIM_GBIT_CONTROL_INIT
, NULL
},
1010 {MIIM_ANAR
, MIIM_ANAR_INIT
, NULL
},
1011 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
1012 {MIIM_CONTROL
, MIIM_CONTROL_INIT
, &mii_cr_init
},
1015 (struct phy_cmd
[]){ /* startup */
1016 /* Status is read once to clear old link state */
1017 {MIIM_STATUS
, miim_read
, NULL
},
1018 /* Auto-negotiate */
1019 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
1020 /* Read the status */
1021 {MIIM_88E1011_PHY_STATUS
, miim_read
,
1022 &mii_parse_88E1011_psr
},
1025 (struct phy_cmd
[]){ /* shutdown */
1030 struct phy_info phy_info_M88E1111S
= {
1034 (struct phy_cmd
[]){ /* config */
1035 /* Reset and configure the PHY */
1036 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
1037 {0x14, 0x0cd2, NULL
}, /* Delay RGMII TX and RX */
1038 {MIIM_GBIT_CONTROL
, MIIM_GBIT_CONTROL_INIT
, NULL
},
1039 {MIIM_ANAR
, MIIM_ANAR_INIT
, NULL
},
1040 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
1041 {MIIM_CONTROL
, MIIM_CONTROL_INIT
, &mii_cr_init
},
1044 (struct phy_cmd
[]){ /* startup */
1045 /* Status is read once to clear old link state */
1046 {MIIM_STATUS
, miim_read
, NULL
},
1047 /* Auto-negotiate */
1048 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
1049 /* Read the status */
1050 {MIIM_88E1011_PHY_STATUS
, miim_read
,
1051 &mii_parse_88E1011_psr
},
1054 (struct phy_cmd
[]){ /* shutdown */
1059 static unsigned int m88e1145_setmode(uint mii_reg
, struct tsec_private
*priv
)
1061 uint mii_data
= read_phy_reg(priv
, mii_reg
);
1063 /* Setting MIIM_88E1145_PHY_EXT_CR */
1064 if (priv
->flags
& TSEC_REDUCED
)
1066 MIIM_M88E1145_RGMII_RX_DELAY
| MIIM_M88E1145_RGMII_TX_DELAY
;
1071 static struct phy_info phy_info_M88E1145
= {
1075 (struct phy_cmd
[]){ /* config */
1077 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
1085 /* Configure the PHY */
1086 {MIIM_GBIT_CONTROL
, MIIM_GBIT_CONTROL_INIT
, NULL
},
1087 {MIIM_ANAR
, MIIM_ANAR_INIT
, NULL
},
1088 {MIIM_88E1011_PHY_SCR
, MIIM_88E1011_PHY_MDI_X_AUTO
,
1090 {MIIM_88E1145_PHY_EXT_CR
, 0, &m88e1145_setmode
},
1091 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
1092 {MIIM_CONTROL
, MIIM_CONTROL_INIT
, NULL
},
1095 (struct phy_cmd
[]){ /* startup */
1096 /* Status is read once to clear old link state */
1097 {MIIM_STATUS
, miim_read
, NULL
},
1098 /* Auto-negotiate */
1099 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
1100 {MIIM_88E1111_PHY_LED_CONTROL
,
1101 MIIM_88E1111_PHY_LED_DIRECT
, NULL
},
1102 /* Read the Status */
1103 {MIIM_88E1011_PHY_STATUS
, miim_read
,
1104 &mii_parse_88E1011_psr
},
1107 (struct phy_cmd
[]){ /* shutdown */
1112 struct phy_info phy_info_cis8204
= {
1116 (struct phy_cmd
[]){ /* config */
1117 /* Override PHY config settings */
1118 {MIIM_CIS8201_AUX_CONSTAT
,
1119 MIIM_CIS8201_AUXCONSTAT_INIT
, NULL
},
1120 /* Configure some basic stuff */
1121 {MIIM_CONTROL
, MIIM_CONTROL_INIT
, &mii_cr_init
},
1122 {MIIM_CIS8204_SLED_CON
, MIIM_CIS8204_SLEDCON_INIT
,
1123 &mii_cis8204_fixled
},
1124 {MIIM_CIS8204_EPHY_CON
, MIIM_CIS8204_EPHYCON_INIT
,
1125 &mii_cis8204_setmode
},
1128 (struct phy_cmd
[]){ /* startup */
1129 /* Read the Status (2x to make sure link is right) */
1130 {MIIM_STATUS
, miim_read
, NULL
},
1131 /* Auto-negotiate */
1132 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
1133 /* Read the status */
1134 {MIIM_CIS8201_AUX_CONSTAT
, miim_read
,
1135 &mii_parse_cis8201
},
1138 (struct phy_cmd
[]){ /* shutdown */
1144 struct phy_info phy_info_cis8201
= {
1148 (struct phy_cmd
[]){ /* config */
1149 /* Override PHY config settings */
1150 {MIIM_CIS8201_AUX_CONSTAT
,
1151 MIIM_CIS8201_AUXCONSTAT_INIT
, NULL
},
1152 /* Set up the interface mode */
1153 {MIIM_CIS8201_EXT_CON1
, MIIM_CIS8201_EXTCON1_INIT
,
1155 /* Configure some basic stuff */
1156 {MIIM_CONTROL
, MIIM_CONTROL_INIT
, &mii_cr_init
},
1159 (struct phy_cmd
[]){ /* startup */
1160 /* Read the Status (2x to make sure link is right) */
1161 {MIIM_STATUS
, miim_read
, NULL
},
1162 /* Auto-negotiate */
1163 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
1164 /* Read the status */
1165 {MIIM_CIS8201_AUX_CONSTAT
, miim_read
,
1166 &mii_parse_cis8201
},
1169 (struct phy_cmd
[]){ /* shutdown */
1173 struct phy_info phy_info_VSC8244
= {
1177 (struct phy_cmd
[]){ /* config */
1178 /* Override PHY config settings */
1179 /* Configure some basic stuff */
1180 {MIIM_CONTROL
, MIIM_CONTROL_INIT
, &mii_cr_init
},
1183 (struct phy_cmd
[]){ /* startup */
1184 /* Read the Status (2x to make sure link is right) */
1185 {MIIM_STATUS
, miim_read
, NULL
},
1186 /* Auto-negotiate */
1187 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
1188 /* Read the status */
1189 {MIIM_VSC8244_AUX_CONSTAT
, miim_read
,
1190 &mii_parse_vsc8244
},
1193 (struct phy_cmd
[]){ /* shutdown */
1198 struct phy_info phy_info_dm9161
= {
1202 (struct phy_cmd
[]){ /* config */
1203 {MIIM_CONTROL
, MIIM_DM9161_CR_STOP
, NULL
},
1204 /* Do not bypass the scrambler/descrambler */
1205 {MIIM_DM9161_SCR
, MIIM_DM9161_SCR_INIT
, NULL
},
1206 /* Clear 10BTCSR to default */
1207 {MIIM_DM9161_10BTCSR
, MIIM_DM9161_10BTCSR_INIT
,
1209 /* Configure some basic stuff */
1210 {MIIM_CONTROL
, MIIM_CR_INIT
, NULL
},
1211 /* Restart Auto Negotiation */
1212 {MIIM_CONTROL
, MIIM_DM9161_CR_RSTAN
, NULL
},
1215 (struct phy_cmd
[]){ /* startup */
1216 /* Status is read once to clear old link state */
1217 {MIIM_STATUS
, miim_read
, NULL
},
1218 /* Auto-negotiate */
1219 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
1220 /* Read the status */
1221 {MIIM_DM9161_SCSR
, miim_read
,
1222 &mii_parse_dm9161_scsr
},
1225 (struct phy_cmd
[]){ /* shutdown */
1229 /* a generic flavor. */
1230 struct phy_info phy_info_generic
= {
1232 "Unknown/Generic PHY",
1234 (struct phy_cmd
[]) { /* config */
1235 {PHY_BMCR
, PHY_BMCR_RESET
, NULL
},
1236 {PHY_BMCR
, PHY_BMCR_AUTON
|PHY_BMCR_RST_NEG
, NULL
},
1239 (struct phy_cmd
[]) { /* startup */
1240 {PHY_BMSR
, miim_read
, NULL
},
1241 {PHY_BMSR
, miim_read
, &mii_parse_sr
},
1242 {PHY_BMSR
, miim_read
, &mii_parse_link
},
1245 (struct phy_cmd
[]) { /* shutdown */
1251 uint
mii_parse_lxt971_sr2(uint mii_reg
, struct tsec_private
*priv
)
1255 speed
= mii_reg
& MIIM_LXT971_SR2_SPEED_MASK
;
1258 case MIIM_LXT971_SR2_10HDX
:
1260 priv
->duplexity
= 0;
1262 case MIIM_LXT971_SR2_10FDX
:
1264 priv
->duplexity
= 1;
1266 case MIIM_LXT971_SR2_100HDX
:
1268 priv
->duplexity
= 0;
1272 priv
->duplexity
= 1;
1276 priv
->duplexity
= 0;
1282 static struct phy_info phy_info_lxt971
= {
1286 (struct phy_cmd
[]){ /* config */
1287 {MIIM_CR
, MIIM_CR_INIT
, mii_cr_init
}, /* autonegotiate */
1290 (struct phy_cmd
[]){ /* startup - enable interrupts */
1291 /* { 0x12, 0x00f2, NULL }, */
1292 {MIIM_STATUS
, miim_read
, NULL
},
1293 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
1294 {MIIM_LXT971_SR2
, miim_read
, &mii_parse_lxt971_sr2
},
1297 (struct phy_cmd
[]){ /* shutdown - disable interrupts */
1302 /* Parse the DP83865's link and auto-neg status register for speed and duplex
1305 uint
mii_parse_dp83865_lanr(uint mii_reg
, struct tsec_private
*priv
)
1307 switch (mii_reg
& MIIM_DP83865_SPD_MASK
) {
1309 case MIIM_DP83865_SPD_1000
:
1313 case MIIM_DP83865_SPD_100
:
1323 if (mii_reg
& MIIM_DP83865_DPX_FULL
)
1324 priv
->duplexity
= 1;
1326 priv
->duplexity
= 0;
1331 struct phy_info phy_info_dp83865
= {
1335 (struct phy_cmd
[]){ /* config */
1336 {MIIM_CONTROL
, MIIM_DP83865_CR_INIT
, NULL
},
1339 (struct phy_cmd
[]){ /* startup */
1340 /* Status is read once to clear old link state */
1341 {MIIM_STATUS
, miim_read
, NULL
},
1342 /* Auto-negotiate */
1343 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
1344 /* Read the link and auto-neg status */
1345 {MIIM_DP83865_LANR
, miim_read
,
1346 &mii_parse_dp83865_lanr
},
1349 (struct phy_cmd
[]){ /* shutdown */
1354 struct phy_info
*phy_info
[] = {
1359 &phy_info_M88E1011S
,
1360 &phy_info_M88E1111S
,
1362 &phy_info_M88E1149S
,
1371 /* Grab the identifier of the device's PHY, and search through
1372 * all of the known PHYs to see if one matches. If so, return
1373 * it, if not, return NULL
1375 struct phy_info
*get_phy_info(struct eth_device
*dev
)
1377 struct tsec_private
*priv
= (struct tsec_private
*)dev
->priv
;
1378 uint phy_reg
, phy_ID
;
1380 struct phy_info
*theInfo
= NULL
;
1382 /* Grab the bits from PHYIR1, and put them in the upper half */
1383 phy_reg
= read_phy_reg(priv
, MIIM_PHYIR1
);
1384 phy_ID
= (phy_reg
& 0xffff) << 16;
1386 /* Grab the bits from PHYIR2, and put them in the lower half */
1387 phy_reg
= read_phy_reg(priv
, MIIM_PHYIR2
);
1388 phy_ID
|= (phy_reg
& 0xffff);
1390 /* loop through all the known PHY types, and find one that */
1391 /* matches the ID we read from the PHY. */
1392 for (i
= 0; phy_info
[i
]; i
++) {
1393 if (phy_info
[i
]->id
== (phy_ID
>> phy_info
[i
]->shift
)) {
1394 theInfo
= phy_info
[i
];
1399 if (theInfo
== NULL
) {
1400 printf("%s: PHY id %x is not supported!\n", dev
->name
, phy_ID
);
1403 debug("%s: PHY is %s (%x)\n", dev
->name
, theInfo
->name
, phy_ID
);
1409 /* Execute the given series of commands on the given device's
1410 * PHY, running functions as necessary
1412 void phy_run_commands(struct tsec_private
*priv
, struct phy_cmd
*cmd
)
1416 volatile tsec_t
*phyregs
= priv
->phyregs
;
1418 phyregs
->miimcfg
= MIIMCFG_RESET
;
1420 phyregs
->miimcfg
= MIIMCFG_INIT_VALUE
;
1422 while (phyregs
->miimind
& MIIMIND_BUSY
) ;
1424 for (i
= 0; cmd
->mii_reg
!= miim_end
; i
++) {
1425 if (cmd
->mii_data
== miim_read
) {
1426 result
= read_phy_reg(priv
, cmd
->mii_reg
);
1428 if (cmd
->funct
!= NULL
)
1429 (*(cmd
->funct
)) (result
, priv
);
1432 if (cmd
->funct
!= NULL
)
1433 result
= (*(cmd
->funct
)) (cmd
->mii_reg
, priv
);
1435 result
= cmd
->mii_data
;
1437 write_phy_reg(priv
, cmd
->mii_reg
, result
);
1444 /* Relocate the function pointers in the phy cmd lists */
1445 static void relocate_cmds(void)
1447 struct phy_cmd
**cmdlistptr
;
1448 struct phy_cmd
*cmd
;
1451 for (i
= 0; phy_info
[i
]; i
++) {
1452 /* First thing's first: relocate the pointers to the
1453 * PHY command structures (the structs were done) */
1454 phy_info
[i
] = (struct phy_info
*)((uint
) phy_info
[i
]
1456 phy_info
[i
]->name
+= gd
->reloc_off
;
1457 phy_info
[i
]->config
=
1458 (struct phy_cmd
*)((uint
) phy_info
[i
]->config
1460 phy_info
[i
]->startup
=
1461 (struct phy_cmd
*)((uint
) phy_info
[i
]->startup
1463 phy_info
[i
]->shutdown
=
1464 (struct phy_cmd
*)((uint
) phy_info
[i
]->shutdown
1467 cmdlistptr
= &phy_info
[i
]->config
;
1469 for (; cmdlistptr
<= &phy_info
[i
]->shutdown
; cmdlistptr
++) {
1471 for (cmd
= *cmdlistptr
;
1472 cmd
->mii_reg
!= miim_end
;
1474 /* Only relocate non-NULL pointers */
1476 cmd
->funct
+= gd
->reloc_off
;
1487 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
1488 && !defined(BITBANGMII)
1490 struct tsec_private
*get_priv_for_phy(unsigned char phyaddr
)
1494 for (i
= 0; i
< MAXCONTROLLERS
; i
++) {
1495 if (privlist
[i
]->phyaddr
== phyaddr
)
1503 * Read a MII PHY register.
1508 static int tsec_miiphy_read(char *devname
, unsigned char addr
,
1509 unsigned char reg
, unsigned short *value
)
1512 struct tsec_private
*priv
= get_priv_for_phy(addr
);
1515 printf("Can't read PHY at address %d\n", addr
);
1519 ret
= (unsigned short)read_phy_reg(priv
, reg
);
1526 * Write a MII PHY register.
1531 static int tsec_miiphy_write(char *devname
, unsigned char addr
,
1532 unsigned char reg
, unsigned short value
)
1534 struct tsec_private
*priv
= get_priv_for_phy(addr
);
1537 printf("Can't write PHY at address %d\n", addr
);
1541 write_phy_reg(priv
, reg
, value
);
1548 #ifdef CONFIG_MCAST_TFTP
1550 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
1552 /* Set the appropriate hash bit for the given addr */
1554 /* The algorithm works like so:
1555 * 1) Take the Destination Address (ie the multicast address), and
1556 * do a CRC on it (little endian), and reverse the bits of the
1558 * 2) Use the 8 most significant bits as a hash into a 256-entry
1559 * table. The table is controlled through 8 32-bit registers:
1560 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
1561 * gaddr7. This means that the 3 most significant bits in the
1562 * hash index which gaddr register to use, and the 5 other bits
1563 * indicate which bit (assuming an IBM numbering scheme, which
1564 * for PowerPC (tm) is usually the case) in the tregister holds
1567 tsec_mcast_addr (struct eth_device
*dev
, u8 mcast_mac
, u8 set
)
1569 struct tsec_private
*priv
= privlist
[1];
1570 volatile tsec_t
*regs
= priv
->regs
;
1571 volatile u32
*reg_array
, value
;
1572 u8 result
, whichbit
, whichreg
;
1574 result
= (u8
)((ether_crc(MAC_ADDR_LEN
,mcast_mac
) >> 24) & 0xff);
1575 whichbit
= result
& 0x1f; /* the 5 LSB = which bit to set */
1576 whichreg
= result
>> 5; /* the 3 MSB = which reg to set it in */
1577 value
= (1 << (31-whichbit
));
1579 reg_array
= &(regs
->hash
.gaddr0
);
1582 reg_array
[whichreg
] |= value
;
1584 reg_array
[whichreg
] &= ~value
;
1588 #endif /* Multicast TFTP ? */
1590 #endif /* CONFIG_TSEC_ENET */