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r8152: Fix an error on RTL8153-BD MAC Address Passthrough support
[thirdparty/kernel/linux.git] / drivers / net / usb / r8152.c
1 /*
2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 */
9
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
22 #include <linux/ip.h>
23 #include <linux/ipv6.h>
24 #include <net/ip6_checksum.h>
25 #include <uapi/linux/mdio.h>
26 #include <linux/mdio.h>
27 #include <linux/usb/cdc.h>
28 #include <linux/suspend.h>
29 #include <linux/acpi.h>
30
31 /* Information for net-next */
32 #define NETNEXT_VERSION "09"
33
34 /* Information for net */
35 #define NET_VERSION "9"
36
37 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
40 #define MODULENAME "r8152"
41
42 #define R8152_PHY_ID 32
43
44 #define PLA_IDR 0xc000
45 #define PLA_RCR 0xc010
46 #define PLA_RMS 0xc016
47 #define PLA_RXFIFO_CTRL0 0xc0a0
48 #define PLA_RXFIFO_CTRL1 0xc0a4
49 #define PLA_RXFIFO_CTRL2 0xc0a8
50 #define PLA_DMY_REG0 0xc0b0
51 #define PLA_FMC 0xc0b4
52 #define PLA_CFG_WOL 0xc0b6
53 #define PLA_TEREDO_CFG 0xc0bc
54 #define PLA_TEREDO_WAKE_BASE 0xc0c4
55 #define PLA_MAR 0xcd00
56 #define PLA_BACKUP 0xd000
57 #define PAL_BDC_CR 0xd1a0
58 #define PLA_TEREDO_TIMER 0xd2cc
59 #define PLA_REALWOW_TIMER 0xd2e8
60 #define PLA_EFUSE_DATA 0xdd00
61 #define PLA_EFUSE_CMD 0xdd02
62 #define PLA_LEDSEL 0xdd90
63 #define PLA_LED_FEATURE 0xdd92
64 #define PLA_PHYAR 0xde00
65 #define PLA_BOOT_CTRL 0xe004
66 #define PLA_GPHY_INTR_IMR 0xe022
67 #define PLA_EEE_CR 0xe040
68 #define PLA_EEEP_CR 0xe080
69 #define PLA_MAC_PWR_CTRL 0xe0c0
70 #define PLA_MAC_PWR_CTRL2 0xe0ca
71 #define PLA_MAC_PWR_CTRL3 0xe0cc
72 #define PLA_MAC_PWR_CTRL4 0xe0ce
73 #define PLA_WDT6_CTRL 0xe428
74 #define PLA_TCR0 0xe610
75 #define PLA_TCR1 0xe612
76 #define PLA_MTPS 0xe615
77 #define PLA_TXFIFO_CTRL 0xe618
78 #define PLA_RSTTALLY 0xe800
79 #define PLA_CR 0xe813
80 #define PLA_CRWECR 0xe81c
81 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
82 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
83 #define PLA_CONFIG5 0xe822
84 #define PLA_PHY_PWR 0xe84c
85 #define PLA_OOB_CTRL 0xe84f
86 #define PLA_CPCR 0xe854
87 #define PLA_MISC_0 0xe858
88 #define PLA_MISC_1 0xe85a
89 #define PLA_OCP_GPHY_BASE 0xe86c
90 #define PLA_TALLYCNT 0xe890
91 #define PLA_SFF_STS_7 0xe8de
92 #define PLA_PHYSTATUS 0xe908
93 #define PLA_BP_BA 0xfc26
94 #define PLA_BP_0 0xfc28
95 #define PLA_BP_1 0xfc2a
96 #define PLA_BP_2 0xfc2c
97 #define PLA_BP_3 0xfc2e
98 #define PLA_BP_4 0xfc30
99 #define PLA_BP_5 0xfc32
100 #define PLA_BP_6 0xfc34
101 #define PLA_BP_7 0xfc36
102 #define PLA_BP_EN 0xfc38
103
104 #define USB_USB2PHY 0xb41e
105 #define USB_SSPHYLINK2 0xb428
106 #define USB_U2P3_CTRL 0xb460
107 #define USB_CSR_DUMMY1 0xb464
108 #define USB_CSR_DUMMY2 0xb466
109 #define USB_DEV_STAT 0xb808
110 #define USB_CONNECT_TIMER 0xcbf8
111 #define USB_MSC_TIMER 0xcbfc
112 #define USB_BURST_SIZE 0xcfc0
113 #define USB_LPM_CONFIG 0xcfd8
114 #define USB_USB_CTRL 0xd406
115 #define USB_PHY_CTRL 0xd408
116 #define USB_TX_AGG 0xd40a
117 #define USB_RX_BUF_TH 0xd40c
118 #define USB_USB_TIMER 0xd428
119 #define USB_RX_EARLY_TIMEOUT 0xd42c
120 #define USB_RX_EARLY_SIZE 0xd42e
121 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
122 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
123 #define USB_TX_DMA 0xd434
124 #define USB_UPT_RXDMA_OWN 0xd437
125 #define USB_TOLERANCE 0xd490
126 #define USB_LPM_CTRL 0xd41a
127 #define USB_BMU_RESET 0xd4b0
128 #define USB_U1U2_TIMER 0xd4da
129 #define USB_UPS_CTRL 0xd800
130 #define USB_POWER_CUT 0xd80a
131 #define USB_MISC_0 0xd81a
132 #define USB_MISC_1 0xd81f
133 #define USB_AFE_CTRL2 0xd824
134 #define USB_UPS_CFG 0xd842
135 #define USB_UPS_FLAGS 0xd848
136 #define USB_WDT11_CTRL 0xe43c
137 #define USB_BP_BA 0xfc26
138 #define USB_BP_0 0xfc28
139 #define USB_BP_1 0xfc2a
140 #define USB_BP_2 0xfc2c
141 #define USB_BP_3 0xfc2e
142 #define USB_BP_4 0xfc30
143 #define USB_BP_5 0xfc32
144 #define USB_BP_6 0xfc34
145 #define USB_BP_7 0xfc36
146 #define USB_BP_EN 0xfc38
147 #define USB_BP_8 0xfc38
148 #define USB_BP_9 0xfc3a
149 #define USB_BP_10 0xfc3c
150 #define USB_BP_11 0xfc3e
151 #define USB_BP_12 0xfc40
152 #define USB_BP_13 0xfc42
153 #define USB_BP_14 0xfc44
154 #define USB_BP_15 0xfc46
155 #define USB_BP2_EN 0xfc48
156
157 /* OCP Registers */
158 #define OCP_ALDPS_CONFIG 0x2010
159 #define OCP_EEE_CONFIG1 0x2080
160 #define OCP_EEE_CONFIG2 0x2092
161 #define OCP_EEE_CONFIG3 0x2094
162 #define OCP_BASE_MII 0xa400
163 #define OCP_EEE_AR 0xa41a
164 #define OCP_EEE_DATA 0xa41c
165 #define OCP_PHY_STATUS 0xa420
166 #define OCP_NCTL_CFG 0xa42c
167 #define OCP_POWER_CFG 0xa430
168 #define OCP_EEE_CFG 0xa432
169 #define OCP_SRAM_ADDR 0xa436
170 #define OCP_SRAM_DATA 0xa438
171 #define OCP_DOWN_SPEED 0xa442
172 #define OCP_EEE_ABLE 0xa5c4
173 #define OCP_EEE_ADV 0xa5d0
174 #define OCP_EEE_LPABLE 0xa5d2
175 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
176 #define OCP_PHY_PATCH_STAT 0xb800
177 #define OCP_PHY_PATCH_CMD 0xb820
178 #define OCP_ADC_IOFFSET 0xbcfc
179 #define OCP_ADC_CFG 0xbc06
180 #define OCP_SYSCLK_CFG 0xc416
181
182 /* SRAM Register */
183 #define SRAM_GREEN_CFG 0x8011
184 #define SRAM_LPF_CFG 0x8012
185 #define SRAM_10M_AMP1 0x8080
186 #define SRAM_10M_AMP2 0x8082
187 #define SRAM_IMPEDANCE 0x8084
188
189 /* PLA_RCR */
190 #define RCR_AAP 0x00000001
191 #define RCR_APM 0x00000002
192 #define RCR_AM 0x00000004
193 #define RCR_AB 0x00000008
194 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
195
196 /* PLA_RXFIFO_CTRL0 */
197 #define RXFIFO_THR1_NORMAL 0x00080002
198 #define RXFIFO_THR1_OOB 0x01800003
199
200 /* PLA_RXFIFO_CTRL1 */
201 #define RXFIFO_THR2_FULL 0x00000060
202 #define RXFIFO_THR2_HIGH 0x00000038
203 #define RXFIFO_THR2_OOB 0x0000004a
204 #define RXFIFO_THR2_NORMAL 0x00a0
205
206 /* PLA_RXFIFO_CTRL2 */
207 #define RXFIFO_THR3_FULL 0x00000078
208 #define RXFIFO_THR3_HIGH 0x00000048
209 #define RXFIFO_THR3_OOB 0x0000005a
210 #define RXFIFO_THR3_NORMAL 0x0110
211
212 /* PLA_TXFIFO_CTRL */
213 #define TXFIFO_THR_NORMAL 0x00400008
214 #define TXFIFO_THR_NORMAL2 0x01000008
215
216 /* PLA_DMY_REG0 */
217 #define ECM_ALDPS 0x0002
218
219 /* PLA_FMC */
220 #define FMC_FCR_MCU_EN 0x0001
221
222 /* PLA_EEEP_CR */
223 #define EEEP_CR_EEEP_TX 0x0002
224
225 /* PLA_WDT6_CTRL */
226 #define WDT6_SET_MODE 0x0010
227
228 /* PLA_TCR0 */
229 #define TCR0_TX_EMPTY 0x0800
230 #define TCR0_AUTO_FIFO 0x0080
231
232 /* PLA_TCR1 */
233 #define VERSION_MASK 0x7cf0
234
235 /* PLA_MTPS */
236 #define MTPS_JUMBO (12 * 1024 / 64)
237 #define MTPS_DEFAULT (6 * 1024 / 64)
238
239 /* PLA_RSTTALLY */
240 #define TALLY_RESET 0x0001
241
242 /* PLA_CR */
243 #define CR_RST 0x10
244 #define CR_RE 0x08
245 #define CR_TE 0x04
246
247 /* PLA_CRWECR */
248 #define CRWECR_NORAML 0x00
249 #define CRWECR_CONFIG 0xc0
250
251 /* PLA_OOB_CTRL */
252 #define NOW_IS_OOB 0x80
253 #define TXFIFO_EMPTY 0x20
254 #define RXFIFO_EMPTY 0x10
255 #define LINK_LIST_READY 0x02
256 #define DIS_MCU_CLROOB 0x01
257 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
258
259 /* PLA_MISC_1 */
260 #define RXDY_GATED_EN 0x0008
261
262 /* PLA_SFF_STS_7 */
263 #define RE_INIT_LL 0x8000
264 #define MCU_BORW_EN 0x4000
265
266 /* PLA_CPCR */
267 #define CPCR_RX_VLAN 0x0040
268
269 /* PLA_CFG_WOL */
270 #define MAGIC_EN 0x0001
271
272 /* PLA_TEREDO_CFG */
273 #define TEREDO_SEL 0x8000
274 #define TEREDO_WAKE_MASK 0x7f00
275 #define TEREDO_RS_EVENT_MASK 0x00fe
276 #define OOB_TEREDO_EN 0x0001
277
278 /* PAL_BDC_CR */
279 #define ALDPS_PROXY_MODE 0x0001
280
281 /* PLA_EFUSE_CMD */
282 #define EFUSE_READ_CMD BIT(15)
283 #define EFUSE_DATA_BIT16 BIT(7)
284
285 /* PLA_CONFIG34 */
286 #define LINK_ON_WAKE_EN 0x0010
287 #define LINK_OFF_WAKE_EN 0x0008
288
289 /* PLA_CONFIG5 */
290 #define BWF_EN 0x0040
291 #define MWF_EN 0x0020
292 #define UWF_EN 0x0010
293 #define LAN_WAKE_EN 0x0002
294
295 /* PLA_LED_FEATURE */
296 #define LED_MODE_MASK 0x0700
297
298 /* PLA_PHY_PWR */
299 #define TX_10M_IDLE_EN 0x0080
300 #define PFM_PWM_SWITCH 0x0040
301
302 /* PLA_MAC_PWR_CTRL */
303 #define D3_CLK_GATED_EN 0x00004000
304 #define MCU_CLK_RATIO 0x07010f07
305 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
306 #define ALDPS_SPDWN_RATIO 0x0f87
307
308 /* PLA_MAC_PWR_CTRL2 */
309 #define EEE_SPDWN_RATIO 0x8007
310 #define MAC_CLK_SPDWN_EN BIT(15)
311
312 /* PLA_MAC_PWR_CTRL3 */
313 #define PKT_AVAIL_SPDWN_EN 0x0100
314 #define SUSPEND_SPDWN_EN 0x0004
315 #define U1U2_SPDWN_EN 0x0002
316 #define L1_SPDWN_EN 0x0001
317
318 /* PLA_MAC_PWR_CTRL4 */
319 #define PWRSAVE_SPDWN_EN 0x1000
320 #define RXDV_SPDWN_EN 0x0800
321 #define TX10MIDLE_EN 0x0100
322 #define TP100_SPDWN_EN 0x0020
323 #define TP500_SPDWN_EN 0x0010
324 #define TP1000_SPDWN_EN 0x0008
325 #define EEE_SPDWN_EN 0x0001
326
327 /* PLA_GPHY_INTR_IMR */
328 #define GPHY_STS_MSK 0x0001
329 #define SPEED_DOWN_MSK 0x0002
330 #define SPDWN_RXDV_MSK 0x0004
331 #define SPDWN_LINKCHG_MSK 0x0008
332
333 /* PLA_PHYAR */
334 #define PHYAR_FLAG 0x80000000
335
336 /* PLA_EEE_CR */
337 #define EEE_RX_EN 0x0001
338 #define EEE_TX_EN 0x0002
339
340 /* PLA_BOOT_CTRL */
341 #define AUTOLOAD_DONE 0x0002
342
343 /* USB_USB2PHY */
344 #define USB2PHY_SUSPEND 0x0001
345 #define USB2PHY_L1 0x0002
346
347 /* USB_SSPHYLINK2 */
348 #define pwd_dn_scale_mask 0x3ffe
349 #define pwd_dn_scale(x) ((x) << 1)
350
351 /* USB_CSR_DUMMY1 */
352 #define DYNAMIC_BURST 0x0001
353
354 /* USB_CSR_DUMMY2 */
355 #define EP4_FULL_FC 0x0001
356
357 /* USB_DEV_STAT */
358 #define STAT_SPEED_MASK 0x0006
359 #define STAT_SPEED_HIGH 0x0000
360 #define STAT_SPEED_FULL 0x0002
361
362 /* USB_LPM_CONFIG */
363 #define LPM_U1U2_EN BIT(0)
364
365 /* USB_TX_AGG */
366 #define TX_AGG_MAX_THRESHOLD 0x03
367
368 /* USB_RX_BUF_TH */
369 #define RX_THR_SUPPER 0x0c350180
370 #define RX_THR_HIGH 0x7a120180
371 #define RX_THR_SLOW 0xffff0180
372 #define RX_THR_B 0x00010001
373
374 /* USB_TX_DMA */
375 #define TEST_MODE_DISABLE 0x00000001
376 #define TX_SIZE_ADJUST1 0x00000100
377
378 /* USB_BMU_RESET */
379 #define BMU_RESET_EP_IN 0x01
380 #define BMU_RESET_EP_OUT 0x02
381
382 /* USB_UPT_RXDMA_OWN */
383 #define OWN_UPDATE BIT(0)
384 #define OWN_CLEAR BIT(1)
385
386 /* USB_UPS_CTRL */
387 #define POWER_CUT 0x0100
388
389 /* USB_PM_CTRL_STATUS */
390 #define RESUME_INDICATE 0x0001
391
392 /* USB_USB_CTRL */
393 #define RX_AGG_DISABLE 0x0010
394 #define RX_ZERO_EN 0x0080
395
396 /* USB_U2P3_CTRL */
397 #define U2P3_ENABLE 0x0001
398
399 /* USB_POWER_CUT */
400 #define PWR_EN 0x0001
401 #define PHASE2_EN 0x0008
402 #define UPS_EN BIT(4)
403 #define USP_PREWAKE BIT(5)
404
405 /* USB_MISC_0 */
406 #define PCUT_STATUS 0x0001
407
408 /* USB_RX_EARLY_TIMEOUT */
409 #define COALESCE_SUPER 85000U
410 #define COALESCE_HIGH 250000U
411 #define COALESCE_SLOW 524280U
412
413 /* USB_WDT11_CTRL */
414 #define TIMER11_EN 0x0001
415
416 /* USB_LPM_CTRL */
417 /* bit 4 ~ 5: fifo empty boundary */
418 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
419 /* bit 2 ~ 3: LMP timer */
420 #define LPM_TIMER_MASK 0x0c
421 #define LPM_TIMER_500MS 0x04 /* 500 ms */
422 #define LPM_TIMER_500US 0x0c /* 500 us */
423 #define ROK_EXIT_LPM 0x02
424
425 /* USB_AFE_CTRL2 */
426 #define SEN_VAL_MASK 0xf800
427 #define SEN_VAL_NORMAL 0xa000
428 #define SEL_RXIDLE 0x0100
429
430 /* USB_UPS_CFG */
431 #define SAW_CNT_1MS_MASK 0x0fff
432
433 /* USB_UPS_FLAGS */
434 #define UPS_FLAGS_R_TUNE BIT(0)
435 #define UPS_FLAGS_EN_10M_CKDIV BIT(1)
436 #define UPS_FLAGS_250M_CKDIV BIT(2)
437 #define UPS_FLAGS_EN_ALDPS BIT(3)
438 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
439 #define UPS_FLAGS_SPEED_MASK (0xf << 16)
440 #define ups_flags_speed(x) ((x) << 16)
441 #define UPS_FLAGS_EN_EEE BIT(20)
442 #define UPS_FLAGS_EN_500M_EEE BIT(21)
443 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
444 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
445 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
446 #define UPS_FLAGS_EN_GREEN BIT(26)
447 #define UPS_FLAGS_EN_FLOW_CTR BIT(27)
448
449 enum spd_duplex {
450 NWAY_10M_HALF = 1,
451 NWAY_10M_FULL,
452 NWAY_100M_HALF,
453 NWAY_100M_FULL,
454 NWAY_1000M_FULL,
455 FORCE_10M_HALF,
456 FORCE_10M_FULL,
457 FORCE_100M_HALF,
458 FORCE_100M_FULL,
459 };
460
461 /* OCP_ALDPS_CONFIG */
462 #define ENPWRSAVE 0x8000
463 #define ENPDNPS 0x0200
464 #define LINKENA 0x0100
465 #define DIS_SDSAVE 0x0010
466
467 /* OCP_PHY_STATUS */
468 #define PHY_STAT_MASK 0x0007
469 #define PHY_STAT_EXT_INIT 2
470 #define PHY_STAT_LAN_ON 3
471 #define PHY_STAT_PWRDN 5
472
473 /* OCP_NCTL_CFG */
474 #define PGA_RETURN_EN BIT(1)
475
476 /* OCP_POWER_CFG */
477 #define EEE_CLKDIV_EN 0x8000
478 #define EN_ALDPS 0x0004
479 #define EN_10M_PLLOFF 0x0001
480
481 /* OCP_EEE_CONFIG1 */
482 #define RG_TXLPI_MSK_HFDUP 0x8000
483 #define RG_MATCLR_EN 0x4000
484 #define EEE_10_CAP 0x2000
485 #define EEE_NWAY_EN 0x1000
486 #define TX_QUIET_EN 0x0200
487 #define RX_QUIET_EN 0x0100
488 #define sd_rise_time_mask 0x0070
489 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
490 #define RG_RXLPI_MSK_HFDUP 0x0008
491 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
492
493 /* OCP_EEE_CONFIG2 */
494 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
495 #define RG_DACQUIET_EN 0x0400
496 #define RG_LDVQUIET_EN 0x0200
497 #define RG_CKRSEL 0x0020
498 #define RG_EEEPRG_EN 0x0010
499
500 /* OCP_EEE_CONFIG3 */
501 #define fast_snr_mask 0xff80
502 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
503 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
504 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
505
506 /* OCP_EEE_AR */
507 /* bit[15:14] function */
508 #define FUN_ADDR 0x0000
509 #define FUN_DATA 0x4000
510 /* bit[4:0] device addr */
511
512 /* OCP_EEE_CFG */
513 #define CTAP_SHORT_EN 0x0040
514 #define EEE10_EN 0x0010
515
516 /* OCP_DOWN_SPEED */
517 #define EN_EEE_CMODE BIT(14)
518 #define EN_EEE_1000 BIT(13)
519 #define EN_EEE_100 BIT(12)
520 #define EN_10M_CLKDIV BIT(11)
521 #define EN_10M_BGOFF 0x0080
522
523 /* OCP_PHY_STATE */
524 #define TXDIS_STATE 0x01
525 #define ABD_STATE 0x02
526
527 /* OCP_PHY_PATCH_STAT */
528 #define PATCH_READY BIT(6)
529
530 /* OCP_PHY_PATCH_CMD */
531 #define PATCH_REQUEST BIT(4)
532
533 /* OCP_ADC_CFG */
534 #define CKADSEL_L 0x0100
535 #define ADC_EN 0x0080
536 #define EN_EMI_L 0x0040
537
538 /* OCP_SYSCLK_CFG */
539 #define clk_div_expo(x) (min(x, 5) << 8)
540
541 /* SRAM_GREEN_CFG */
542 #define GREEN_ETH_EN BIT(15)
543 #define R_TUNE_EN BIT(11)
544
545 /* SRAM_LPF_CFG */
546 #define LPF_AUTO_TUNE 0x8000
547
548 /* SRAM_10M_AMP1 */
549 #define GDAC_IB_UPALL 0x0008
550
551 /* SRAM_10M_AMP2 */
552 #define AMP_DN 0x0200
553
554 /* SRAM_IMPEDANCE */
555 #define RX_DRIVING_MASK 0x6000
556
557 /* MAC PASSTHRU */
558 #define AD_MASK 0xfee0
559 #define BND_MASK 0x0004
560 #define BD_MASK 0x0001
561 #define EFUSE 0xcfdb
562 #define PASS_THRU_MASK 0x1
563
564 enum rtl_register_content {
565 _1000bps = 0x10,
566 _100bps = 0x08,
567 _10bps = 0x04,
568 LINK_STATUS = 0x02,
569 FULL_DUP = 0x01,
570 };
571
572 #define RTL8152_MAX_TX 4
573 #define RTL8152_MAX_RX 10
574 #define INTBUFSIZE 2
575 #define TX_ALIGN 4
576 #define RX_ALIGN 8
577
578 #define INTR_LINK 0x0004
579
580 #define RTL8152_REQT_READ 0xc0
581 #define RTL8152_REQT_WRITE 0x40
582 #define RTL8152_REQ_GET_REGS 0x05
583 #define RTL8152_REQ_SET_REGS 0x05
584
585 #define BYTE_EN_DWORD 0xff
586 #define BYTE_EN_WORD 0x33
587 #define BYTE_EN_BYTE 0x11
588 #define BYTE_EN_SIX_BYTES 0x3f
589 #define BYTE_EN_START_MASK 0x0f
590 #define BYTE_EN_END_MASK 0xf0
591
592 #define RTL8153_MAX_PACKET 9216 /* 9K */
593 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
594 ETH_FCS_LEN)
595 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
596 #define RTL8153_RMS RTL8153_MAX_PACKET
597 #define RTL8152_TX_TIMEOUT (5 * HZ)
598 #define RTL8152_NAPI_WEIGHT 64
599 #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
600 sizeof(struct rx_desc) + RX_ALIGN)
601
602 /* rtl8152 flags */
603 enum rtl8152_flags {
604 RTL8152_UNPLUG = 0,
605 RTL8152_SET_RX_MODE,
606 WORK_ENABLE,
607 RTL8152_LINK_CHG,
608 SELECTIVE_SUSPEND,
609 PHY_RESET,
610 SCHEDULE_NAPI,
611 GREEN_ETHERNET,
612 DELL_TB_RX_AGG_BUG,
613 };
614
615 /* Define these values to match your device */
616 #define VENDOR_ID_REALTEK 0x0bda
617 #define VENDOR_ID_MICROSOFT 0x045e
618 #define VENDOR_ID_SAMSUNG 0x04e8
619 #define VENDOR_ID_LENOVO 0x17ef
620 #define VENDOR_ID_LINKSYS 0x13b1
621 #define VENDOR_ID_NVIDIA 0x0955
622 #define VENDOR_ID_TPLINK 0x2357
623
624 #define MCU_TYPE_PLA 0x0100
625 #define MCU_TYPE_USB 0x0000
626
627 struct tally_counter {
628 __le64 tx_packets;
629 __le64 rx_packets;
630 __le64 tx_errors;
631 __le32 rx_errors;
632 __le16 rx_missed;
633 __le16 align_errors;
634 __le32 tx_one_collision;
635 __le32 tx_multi_collision;
636 __le64 rx_unicast;
637 __le64 rx_broadcast;
638 __le32 rx_multicast;
639 __le16 tx_aborted;
640 __le16 tx_underrun;
641 };
642
643 struct rx_desc {
644 __le32 opts1;
645 #define RX_LEN_MASK 0x7fff
646
647 __le32 opts2;
648 #define RD_UDP_CS BIT(23)
649 #define RD_TCP_CS BIT(22)
650 #define RD_IPV6_CS BIT(20)
651 #define RD_IPV4_CS BIT(19)
652
653 __le32 opts3;
654 #define IPF BIT(23) /* IP checksum fail */
655 #define UDPF BIT(22) /* UDP checksum fail */
656 #define TCPF BIT(21) /* TCP checksum fail */
657 #define RX_VLAN_TAG BIT(16)
658
659 __le32 opts4;
660 __le32 opts5;
661 __le32 opts6;
662 };
663
664 struct tx_desc {
665 __le32 opts1;
666 #define TX_FS BIT(31) /* First segment of a packet */
667 #define TX_LS BIT(30) /* Final segment of a packet */
668 #define GTSENDV4 BIT(28)
669 #define GTSENDV6 BIT(27)
670 #define GTTCPHO_SHIFT 18
671 #define GTTCPHO_MAX 0x7fU
672 #define TX_LEN_MAX 0x3ffffU
673
674 __le32 opts2;
675 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
676 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
677 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
678 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
679 #define MSS_SHIFT 17
680 #define MSS_MAX 0x7ffU
681 #define TCPHO_SHIFT 17
682 #define TCPHO_MAX 0x7ffU
683 #define TX_VLAN_TAG BIT(16)
684 };
685
686 struct r8152;
687
688 struct rx_agg {
689 struct list_head list;
690 struct urb *urb;
691 struct r8152 *context;
692 void *buffer;
693 void *head;
694 };
695
696 struct tx_agg {
697 struct list_head list;
698 struct urb *urb;
699 struct r8152 *context;
700 void *buffer;
701 void *head;
702 u32 skb_num;
703 u32 skb_len;
704 };
705
706 struct r8152 {
707 unsigned long flags;
708 struct usb_device *udev;
709 struct napi_struct napi;
710 struct usb_interface *intf;
711 struct net_device *netdev;
712 struct urb *intr_urb;
713 struct tx_agg tx_info[RTL8152_MAX_TX];
714 struct rx_agg rx_info[RTL8152_MAX_RX];
715 struct list_head rx_done, tx_free;
716 struct sk_buff_head tx_queue, rx_queue;
717 spinlock_t rx_lock, tx_lock;
718 struct delayed_work schedule, hw_phy_work;
719 struct mii_if_info mii;
720 struct mutex control; /* use for hw setting */
721 #ifdef CONFIG_PM_SLEEP
722 struct notifier_block pm_notifier;
723 #endif
724
725 struct rtl_ops {
726 void (*init)(struct r8152 *);
727 int (*enable)(struct r8152 *);
728 void (*disable)(struct r8152 *);
729 void (*up)(struct r8152 *);
730 void (*down)(struct r8152 *);
731 void (*unload)(struct r8152 *);
732 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
733 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
734 bool (*in_nway)(struct r8152 *);
735 void (*hw_phy_cfg)(struct r8152 *);
736 void (*autosuspend_en)(struct r8152 *tp, bool enable);
737 } rtl_ops;
738
739 int intr_interval;
740 u32 saved_wolopts;
741 u32 msg_enable;
742 u32 tx_qlen;
743 u32 coalesce;
744 u16 ocp_base;
745 u16 speed;
746 u8 *intr_buff;
747 u8 version;
748 u8 duplex;
749 u8 autoneg;
750 };
751
752 enum rtl_version {
753 RTL_VER_UNKNOWN = 0,
754 RTL_VER_01,
755 RTL_VER_02,
756 RTL_VER_03,
757 RTL_VER_04,
758 RTL_VER_05,
759 RTL_VER_06,
760 RTL_VER_07,
761 RTL_VER_08,
762 RTL_VER_09,
763 RTL_VER_MAX
764 };
765
766 enum tx_csum_stat {
767 TX_CSUM_SUCCESS = 0,
768 TX_CSUM_TSO,
769 TX_CSUM_NONE
770 };
771
772 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
773 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
774 */
775 static const int multicast_filter_limit = 32;
776 static unsigned int agg_buf_sz = 16384;
777
778 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
779 VLAN_ETH_HLEN - ETH_FCS_LEN)
780
781 static
782 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
783 {
784 int ret;
785 void *tmp;
786
787 tmp = kmalloc(size, GFP_KERNEL);
788 if (!tmp)
789 return -ENOMEM;
790
791 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
792 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
793 value, index, tmp, size, 500);
794
795 memcpy(data, tmp, size);
796 kfree(tmp);
797
798 return ret;
799 }
800
801 static
802 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
803 {
804 int ret;
805 void *tmp;
806
807 tmp = kmemdup(data, size, GFP_KERNEL);
808 if (!tmp)
809 return -ENOMEM;
810
811 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
812 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
813 value, index, tmp, size, 500);
814
815 kfree(tmp);
816
817 return ret;
818 }
819
820 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
821 void *data, u16 type)
822 {
823 u16 limit = 64;
824 int ret = 0;
825
826 if (test_bit(RTL8152_UNPLUG, &tp->flags))
827 return -ENODEV;
828
829 /* both size and indix must be 4 bytes align */
830 if ((size & 3) || !size || (index & 3) || !data)
831 return -EPERM;
832
833 if ((u32)index + (u32)size > 0xffff)
834 return -EPERM;
835
836 while (size) {
837 if (size > limit) {
838 ret = get_registers(tp, index, type, limit, data);
839 if (ret < 0)
840 break;
841
842 index += limit;
843 data += limit;
844 size -= limit;
845 } else {
846 ret = get_registers(tp, index, type, size, data);
847 if (ret < 0)
848 break;
849
850 index += size;
851 data += size;
852 size = 0;
853 break;
854 }
855 }
856
857 if (ret == -ENODEV)
858 set_bit(RTL8152_UNPLUG, &tp->flags);
859
860 return ret;
861 }
862
863 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
864 u16 size, void *data, u16 type)
865 {
866 int ret;
867 u16 byteen_start, byteen_end, byen;
868 u16 limit = 512;
869
870 if (test_bit(RTL8152_UNPLUG, &tp->flags))
871 return -ENODEV;
872
873 /* both size and indix must be 4 bytes align */
874 if ((size & 3) || !size || (index & 3) || !data)
875 return -EPERM;
876
877 if ((u32)index + (u32)size > 0xffff)
878 return -EPERM;
879
880 byteen_start = byteen & BYTE_EN_START_MASK;
881 byteen_end = byteen & BYTE_EN_END_MASK;
882
883 byen = byteen_start | (byteen_start << 4);
884 ret = set_registers(tp, index, type | byen, 4, data);
885 if (ret < 0)
886 goto error1;
887
888 index += 4;
889 data += 4;
890 size -= 4;
891
892 if (size) {
893 size -= 4;
894
895 while (size) {
896 if (size > limit) {
897 ret = set_registers(tp, index,
898 type | BYTE_EN_DWORD,
899 limit, data);
900 if (ret < 0)
901 goto error1;
902
903 index += limit;
904 data += limit;
905 size -= limit;
906 } else {
907 ret = set_registers(tp, index,
908 type | BYTE_EN_DWORD,
909 size, data);
910 if (ret < 0)
911 goto error1;
912
913 index += size;
914 data += size;
915 size = 0;
916 break;
917 }
918 }
919
920 byen = byteen_end | (byteen_end >> 4);
921 ret = set_registers(tp, index, type | byen, 4, data);
922 if (ret < 0)
923 goto error1;
924 }
925
926 error1:
927 if (ret == -ENODEV)
928 set_bit(RTL8152_UNPLUG, &tp->flags);
929
930 return ret;
931 }
932
933 static inline
934 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
935 {
936 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
937 }
938
939 static inline
940 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
941 {
942 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
943 }
944
945 static inline
946 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
947 {
948 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
949 }
950
951 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
952 {
953 __le32 data;
954
955 generic_ocp_read(tp, index, sizeof(data), &data, type);
956
957 return __le32_to_cpu(data);
958 }
959
960 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
961 {
962 __le32 tmp = __cpu_to_le32(data);
963
964 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
965 }
966
967 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
968 {
969 u32 data;
970 __le32 tmp;
971 u16 byen = BYTE_EN_WORD;
972 u8 shift = index & 2;
973
974 index &= ~3;
975 byen <<= shift;
976
977 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
978
979 data = __le32_to_cpu(tmp);
980 data >>= (shift * 8);
981 data &= 0xffff;
982
983 return (u16)data;
984 }
985
986 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
987 {
988 u32 mask = 0xffff;
989 __le32 tmp;
990 u16 byen = BYTE_EN_WORD;
991 u8 shift = index & 2;
992
993 data &= mask;
994
995 if (index & 2) {
996 byen <<= shift;
997 mask <<= (shift * 8);
998 data <<= (shift * 8);
999 index &= ~3;
1000 }
1001
1002 tmp = __cpu_to_le32(data);
1003
1004 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1005 }
1006
1007 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1008 {
1009 u32 data;
1010 __le32 tmp;
1011 u8 shift = index & 3;
1012
1013 index &= ~3;
1014
1015 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1016
1017 data = __le32_to_cpu(tmp);
1018 data >>= (shift * 8);
1019 data &= 0xff;
1020
1021 return (u8)data;
1022 }
1023
1024 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1025 {
1026 u32 mask = 0xff;
1027 __le32 tmp;
1028 u16 byen = BYTE_EN_BYTE;
1029 u8 shift = index & 3;
1030
1031 data &= mask;
1032
1033 if (index & 3) {
1034 byen <<= shift;
1035 mask <<= (shift * 8);
1036 data <<= (shift * 8);
1037 index &= ~3;
1038 }
1039
1040 tmp = __cpu_to_le32(data);
1041
1042 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1043 }
1044
1045 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1046 {
1047 u16 ocp_base, ocp_index;
1048
1049 ocp_base = addr & 0xf000;
1050 if (ocp_base != tp->ocp_base) {
1051 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1052 tp->ocp_base = ocp_base;
1053 }
1054
1055 ocp_index = (addr & 0x0fff) | 0xb000;
1056 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1057 }
1058
1059 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1060 {
1061 u16 ocp_base, ocp_index;
1062
1063 ocp_base = addr & 0xf000;
1064 if (ocp_base != tp->ocp_base) {
1065 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1066 tp->ocp_base = ocp_base;
1067 }
1068
1069 ocp_index = (addr & 0x0fff) | 0xb000;
1070 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1071 }
1072
1073 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1074 {
1075 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1076 }
1077
1078 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1079 {
1080 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1081 }
1082
1083 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1084 {
1085 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1086 ocp_reg_write(tp, OCP_SRAM_DATA, data);
1087 }
1088
1089 static u16 sram_read(struct r8152 *tp, u16 addr)
1090 {
1091 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1092 return ocp_reg_read(tp, OCP_SRAM_DATA);
1093 }
1094
1095 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1096 {
1097 struct r8152 *tp = netdev_priv(netdev);
1098 int ret;
1099
1100 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1101 return -ENODEV;
1102
1103 if (phy_id != R8152_PHY_ID)
1104 return -EINVAL;
1105
1106 ret = r8152_mdio_read(tp, reg);
1107
1108 return ret;
1109 }
1110
1111 static
1112 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1113 {
1114 struct r8152 *tp = netdev_priv(netdev);
1115
1116 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1117 return;
1118
1119 if (phy_id != R8152_PHY_ID)
1120 return;
1121
1122 r8152_mdio_write(tp, reg, val);
1123 }
1124
1125 static int
1126 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1127
1128 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1129 {
1130 struct r8152 *tp = netdev_priv(netdev);
1131 struct sockaddr *addr = p;
1132 int ret = -EADDRNOTAVAIL;
1133
1134 if (!is_valid_ether_addr(addr->sa_data))
1135 goto out1;
1136
1137 ret = usb_autopm_get_interface(tp->intf);
1138 if (ret < 0)
1139 goto out1;
1140
1141 mutex_lock(&tp->control);
1142
1143 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1144
1145 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1146 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1147 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1148
1149 mutex_unlock(&tp->control);
1150
1151 usb_autopm_put_interface(tp->intf);
1152 out1:
1153 return ret;
1154 }
1155
1156 /* Devices containing proper chips can support a persistent
1157 * host system provided MAC address.
1158 * Examples of this are Dell TB15 and Dell WD15 docks
1159 */
1160 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1161 {
1162 acpi_status status;
1163 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1164 union acpi_object *obj;
1165 int ret = -EINVAL;
1166 u32 ocp_data;
1167 unsigned char buf[6];
1168
1169 /* test for -AD variant of RTL8153 */
1170 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1171 if ((ocp_data & AD_MASK) == 0x1000) {
1172 /* test for MAC address pass-through bit */
1173 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1174 if ((ocp_data & PASS_THRU_MASK) != 1) {
1175 netif_dbg(tp, probe, tp->netdev,
1176 "No efuse for RTL8153-AD MAC pass through\n");
1177 return -ENODEV;
1178 }
1179 } else {
1180 /* test for RTL8153-BND and RTL8153-BD */
1181 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1182 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1183 netif_dbg(tp, probe, tp->netdev,
1184 "Invalid variant for MAC pass through\n");
1185 return -ENODEV;
1186 }
1187 }
1188
1189 /* returns _AUXMAC_#AABBCCDDEEFF# */
1190 status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer);
1191 obj = (union acpi_object *)buffer.pointer;
1192 if (!ACPI_SUCCESS(status))
1193 return -ENODEV;
1194 if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) {
1195 netif_warn(tp, probe, tp->netdev,
1196 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1197 obj->type, obj->string.length);
1198 goto amacout;
1199 }
1200 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1201 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1202 netif_warn(tp, probe, tp->netdev,
1203 "Invalid header when reading pass-thru MAC addr\n");
1204 goto amacout;
1205 }
1206 ret = hex2bin(buf, obj->string.pointer + 9, 6);
1207 if (!(ret == 0 && is_valid_ether_addr(buf))) {
1208 netif_warn(tp, probe, tp->netdev,
1209 "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1210 ret, buf);
1211 ret = -EINVAL;
1212 goto amacout;
1213 }
1214 memcpy(sa->sa_data, buf, 6);
1215 ether_addr_copy(tp->netdev->dev_addr, sa->sa_data);
1216 netif_info(tp, probe, tp->netdev,
1217 "Using pass-thru MAC addr %pM\n", sa->sa_data);
1218
1219 amacout:
1220 kfree(obj);
1221 return ret;
1222 }
1223
1224 static int set_ethernet_addr(struct r8152 *tp)
1225 {
1226 struct net_device *dev = tp->netdev;
1227 struct sockaddr sa;
1228 int ret;
1229
1230 if (tp->version == RTL_VER_01) {
1231 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
1232 } else {
1233 /* if device doesn't support MAC pass through this will
1234 * be expected to be non-zero
1235 */
1236 ret = vendor_mac_passthru_addr_read(tp, &sa);
1237 if (ret < 0)
1238 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
1239 }
1240
1241 if (ret < 0) {
1242 netif_err(tp, probe, dev, "Get ether addr fail\n");
1243 } else if (!is_valid_ether_addr(sa.sa_data)) {
1244 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1245 sa.sa_data);
1246 eth_hw_addr_random(dev);
1247 ether_addr_copy(sa.sa_data, dev->dev_addr);
1248 ret = rtl8152_set_mac_address(dev, &sa);
1249 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1250 sa.sa_data);
1251 } else {
1252 if (tp->version == RTL_VER_01)
1253 ether_addr_copy(dev->dev_addr, sa.sa_data);
1254 else
1255 ret = rtl8152_set_mac_address(dev, &sa);
1256 }
1257
1258 return ret;
1259 }
1260
1261 static void read_bulk_callback(struct urb *urb)
1262 {
1263 struct net_device *netdev;
1264 int status = urb->status;
1265 struct rx_agg *agg;
1266 struct r8152 *tp;
1267 unsigned long flags;
1268
1269 agg = urb->context;
1270 if (!agg)
1271 return;
1272
1273 tp = agg->context;
1274 if (!tp)
1275 return;
1276
1277 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1278 return;
1279
1280 if (!test_bit(WORK_ENABLE, &tp->flags))
1281 return;
1282
1283 netdev = tp->netdev;
1284
1285 /* When link down, the driver would cancel all bulks. */
1286 /* This avoid the re-submitting bulk */
1287 if (!netif_carrier_ok(netdev))
1288 return;
1289
1290 usb_mark_last_busy(tp->udev);
1291
1292 switch (status) {
1293 case 0:
1294 if (urb->actual_length < ETH_ZLEN)
1295 break;
1296
1297 spin_lock_irqsave(&tp->rx_lock, flags);
1298 list_add_tail(&agg->list, &tp->rx_done);
1299 spin_unlock_irqrestore(&tp->rx_lock, flags);
1300 napi_schedule(&tp->napi);
1301 return;
1302 case -ESHUTDOWN:
1303 set_bit(RTL8152_UNPLUG, &tp->flags);
1304 netif_device_detach(tp->netdev);
1305 return;
1306 case -ENOENT:
1307 return; /* the urb is in unlink state */
1308 case -ETIME:
1309 if (net_ratelimit())
1310 netdev_warn(netdev, "maybe reset is needed?\n");
1311 break;
1312 default:
1313 if (net_ratelimit())
1314 netdev_warn(netdev, "Rx status %d\n", status);
1315 break;
1316 }
1317
1318 r8152_submit_rx(tp, agg, GFP_ATOMIC);
1319 }
1320
1321 static void write_bulk_callback(struct urb *urb)
1322 {
1323 struct net_device_stats *stats;
1324 struct net_device *netdev;
1325 struct tx_agg *agg;
1326 struct r8152 *tp;
1327 unsigned long flags;
1328 int status = urb->status;
1329
1330 agg = urb->context;
1331 if (!agg)
1332 return;
1333
1334 tp = agg->context;
1335 if (!tp)
1336 return;
1337
1338 netdev = tp->netdev;
1339 stats = &netdev->stats;
1340 if (status) {
1341 if (net_ratelimit())
1342 netdev_warn(netdev, "Tx status %d\n", status);
1343 stats->tx_errors += agg->skb_num;
1344 } else {
1345 stats->tx_packets += agg->skb_num;
1346 stats->tx_bytes += agg->skb_len;
1347 }
1348
1349 spin_lock_irqsave(&tp->tx_lock, flags);
1350 list_add_tail(&agg->list, &tp->tx_free);
1351 spin_unlock_irqrestore(&tp->tx_lock, flags);
1352
1353 usb_autopm_put_interface_async(tp->intf);
1354
1355 if (!netif_carrier_ok(netdev))
1356 return;
1357
1358 if (!test_bit(WORK_ENABLE, &tp->flags))
1359 return;
1360
1361 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1362 return;
1363
1364 if (!skb_queue_empty(&tp->tx_queue))
1365 napi_schedule(&tp->napi);
1366 }
1367
1368 static void intr_callback(struct urb *urb)
1369 {
1370 struct r8152 *tp;
1371 __le16 *d;
1372 int status = urb->status;
1373 int res;
1374
1375 tp = urb->context;
1376 if (!tp)
1377 return;
1378
1379 if (!test_bit(WORK_ENABLE, &tp->flags))
1380 return;
1381
1382 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1383 return;
1384
1385 switch (status) {
1386 case 0: /* success */
1387 break;
1388 case -ECONNRESET: /* unlink */
1389 case -ESHUTDOWN:
1390 netif_device_detach(tp->netdev);
1391 /* fall through */
1392 case -ENOENT:
1393 case -EPROTO:
1394 netif_info(tp, intr, tp->netdev,
1395 "Stop submitting intr, status %d\n", status);
1396 return;
1397 case -EOVERFLOW:
1398 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1399 goto resubmit;
1400 /* -EPIPE: should clear the halt */
1401 default:
1402 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1403 goto resubmit;
1404 }
1405
1406 d = urb->transfer_buffer;
1407 if (INTR_LINK & __le16_to_cpu(d[0])) {
1408 if (!netif_carrier_ok(tp->netdev)) {
1409 set_bit(RTL8152_LINK_CHG, &tp->flags);
1410 schedule_delayed_work(&tp->schedule, 0);
1411 }
1412 } else {
1413 if (netif_carrier_ok(tp->netdev)) {
1414 netif_stop_queue(tp->netdev);
1415 set_bit(RTL8152_LINK_CHG, &tp->flags);
1416 schedule_delayed_work(&tp->schedule, 0);
1417 }
1418 }
1419
1420 resubmit:
1421 res = usb_submit_urb(urb, GFP_ATOMIC);
1422 if (res == -ENODEV) {
1423 set_bit(RTL8152_UNPLUG, &tp->flags);
1424 netif_device_detach(tp->netdev);
1425 } else if (res) {
1426 netif_err(tp, intr, tp->netdev,
1427 "can't resubmit intr, status %d\n", res);
1428 }
1429 }
1430
1431 static inline void *rx_agg_align(void *data)
1432 {
1433 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1434 }
1435
1436 static inline void *tx_agg_align(void *data)
1437 {
1438 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1439 }
1440
1441 static void free_all_mem(struct r8152 *tp)
1442 {
1443 int i;
1444
1445 for (i = 0; i < RTL8152_MAX_RX; i++) {
1446 usb_free_urb(tp->rx_info[i].urb);
1447 tp->rx_info[i].urb = NULL;
1448
1449 kfree(tp->rx_info[i].buffer);
1450 tp->rx_info[i].buffer = NULL;
1451 tp->rx_info[i].head = NULL;
1452 }
1453
1454 for (i = 0; i < RTL8152_MAX_TX; i++) {
1455 usb_free_urb(tp->tx_info[i].urb);
1456 tp->tx_info[i].urb = NULL;
1457
1458 kfree(tp->tx_info[i].buffer);
1459 tp->tx_info[i].buffer = NULL;
1460 tp->tx_info[i].head = NULL;
1461 }
1462
1463 usb_free_urb(tp->intr_urb);
1464 tp->intr_urb = NULL;
1465
1466 kfree(tp->intr_buff);
1467 tp->intr_buff = NULL;
1468 }
1469
1470 static int alloc_all_mem(struct r8152 *tp)
1471 {
1472 struct net_device *netdev = tp->netdev;
1473 struct usb_interface *intf = tp->intf;
1474 struct usb_host_interface *alt = intf->cur_altsetting;
1475 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1476 struct urb *urb;
1477 int node, i;
1478 u8 *buf;
1479
1480 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1481
1482 spin_lock_init(&tp->rx_lock);
1483 spin_lock_init(&tp->tx_lock);
1484 INIT_LIST_HEAD(&tp->tx_free);
1485 INIT_LIST_HEAD(&tp->rx_done);
1486 skb_queue_head_init(&tp->tx_queue);
1487 skb_queue_head_init(&tp->rx_queue);
1488
1489 for (i = 0; i < RTL8152_MAX_RX; i++) {
1490 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1491 if (!buf)
1492 goto err1;
1493
1494 if (buf != rx_agg_align(buf)) {
1495 kfree(buf);
1496 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
1497 node);
1498 if (!buf)
1499 goto err1;
1500 }
1501
1502 urb = usb_alloc_urb(0, GFP_KERNEL);
1503 if (!urb) {
1504 kfree(buf);
1505 goto err1;
1506 }
1507
1508 INIT_LIST_HEAD(&tp->rx_info[i].list);
1509 tp->rx_info[i].context = tp;
1510 tp->rx_info[i].urb = urb;
1511 tp->rx_info[i].buffer = buf;
1512 tp->rx_info[i].head = rx_agg_align(buf);
1513 }
1514
1515 for (i = 0; i < RTL8152_MAX_TX; i++) {
1516 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1517 if (!buf)
1518 goto err1;
1519
1520 if (buf != tx_agg_align(buf)) {
1521 kfree(buf);
1522 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1523 node);
1524 if (!buf)
1525 goto err1;
1526 }
1527
1528 urb = usb_alloc_urb(0, GFP_KERNEL);
1529 if (!urb) {
1530 kfree(buf);
1531 goto err1;
1532 }
1533
1534 INIT_LIST_HEAD(&tp->tx_info[i].list);
1535 tp->tx_info[i].context = tp;
1536 tp->tx_info[i].urb = urb;
1537 tp->tx_info[i].buffer = buf;
1538 tp->tx_info[i].head = tx_agg_align(buf);
1539
1540 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1541 }
1542
1543 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1544 if (!tp->intr_urb)
1545 goto err1;
1546
1547 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1548 if (!tp->intr_buff)
1549 goto err1;
1550
1551 tp->intr_interval = (int)ep_intr->desc.bInterval;
1552 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1553 tp->intr_buff, INTBUFSIZE, intr_callback,
1554 tp, tp->intr_interval);
1555
1556 return 0;
1557
1558 err1:
1559 free_all_mem(tp);
1560 return -ENOMEM;
1561 }
1562
1563 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1564 {
1565 struct tx_agg *agg = NULL;
1566 unsigned long flags;
1567
1568 if (list_empty(&tp->tx_free))
1569 return NULL;
1570
1571 spin_lock_irqsave(&tp->tx_lock, flags);
1572 if (!list_empty(&tp->tx_free)) {
1573 struct list_head *cursor;
1574
1575 cursor = tp->tx_free.next;
1576 list_del_init(cursor);
1577 agg = list_entry(cursor, struct tx_agg, list);
1578 }
1579 spin_unlock_irqrestore(&tp->tx_lock, flags);
1580
1581 return agg;
1582 }
1583
1584 /* r8152_csum_workaround()
1585 * The hw limites the value the transport offset. When the offset is out of the
1586 * range, calculate the checksum by sw.
1587 */
1588 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1589 struct sk_buff_head *list)
1590 {
1591 if (skb_shinfo(skb)->gso_size) {
1592 netdev_features_t features = tp->netdev->features;
1593 struct sk_buff_head seg_list;
1594 struct sk_buff *segs, *nskb;
1595
1596 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1597 segs = skb_gso_segment(skb, features);
1598 if (IS_ERR(segs) || !segs)
1599 goto drop;
1600
1601 __skb_queue_head_init(&seg_list);
1602
1603 do {
1604 nskb = segs;
1605 segs = segs->next;
1606 nskb->next = NULL;
1607 __skb_queue_tail(&seg_list, nskb);
1608 } while (segs);
1609
1610 skb_queue_splice(&seg_list, list);
1611 dev_kfree_skb(skb);
1612 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1613 if (skb_checksum_help(skb) < 0)
1614 goto drop;
1615
1616 __skb_queue_head(list, skb);
1617 } else {
1618 struct net_device_stats *stats;
1619
1620 drop:
1621 stats = &tp->netdev->stats;
1622 stats->tx_dropped++;
1623 dev_kfree_skb(skb);
1624 }
1625 }
1626
1627 /* msdn_giant_send_check()
1628 * According to the document of microsoft, the TCP Pseudo Header excludes the
1629 * packet length for IPv6 TCP large packets.
1630 */
1631 static int msdn_giant_send_check(struct sk_buff *skb)
1632 {
1633 const struct ipv6hdr *ipv6h;
1634 struct tcphdr *th;
1635 int ret;
1636
1637 ret = skb_cow_head(skb, 0);
1638 if (ret)
1639 return ret;
1640
1641 ipv6h = ipv6_hdr(skb);
1642 th = tcp_hdr(skb);
1643
1644 th->check = 0;
1645 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1646
1647 return ret;
1648 }
1649
1650 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1651 {
1652 if (skb_vlan_tag_present(skb)) {
1653 u32 opts2;
1654
1655 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1656 desc->opts2 |= cpu_to_le32(opts2);
1657 }
1658 }
1659
1660 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1661 {
1662 u32 opts2 = le32_to_cpu(desc->opts2);
1663
1664 if (opts2 & RX_VLAN_TAG)
1665 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1666 swab16(opts2 & 0xffff));
1667 }
1668
1669 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1670 struct sk_buff *skb, u32 len, u32 transport_offset)
1671 {
1672 u32 mss = skb_shinfo(skb)->gso_size;
1673 u32 opts1, opts2 = 0;
1674 int ret = TX_CSUM_SUCCESS;
1675
1676 WARN_ON_ONCE(len > TX_LEN_MAX);
1677
1678 opts1 = len | TX_FS | TX_LS;
1679
1680 if (mss) {
1681 if (transport_offset > GTTCPHO_MAX) {
1682 netif_warn(tp, tx_err, tp->netdev,
1683 "Invalid transport offset 0x%x for TSO\n",
1684 transport_offset);
1685 ret = TX_CSUM_TSO;
1686 goto unavailable;
1687 }
1688
1689 switch (vlan_get_protocol(skb)) {
1690 case htons(ETH_P_IP):
1691 opts1 |= GTSENDV4;
1692 break;
1693
1694 case htons(ETH_P_IPV6):
1695 if (msdn_giant_send_check(skb)) {
1696 ret = TX_CSUM_TSO;
1697 goto unavailable;
1698 }
1699 opts1 |= GTSENDV6;
1700 break;
1701
1702 default:
1703 WARN_ON_ONCE(1);
1704 break;
1705 }
1706
1707 opts1 |= transport_offset << GTTCPHO_SHIFT;
1708 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1709 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1710 u8 ip_protocol;
1711
1712 if (transport_offset > TCPHO_MAX) {
1713 netif_warn(tp, tx_err, tp->netdev,
1714 "Invalid transport offset 0x%x\n",
1715 transport_offset);
1716 ret = TX_CSUM_NONE;
1717 goto unavailable;
1718 }
1719
1720 switch (vlan_get_protocol(skb)) {
1721 case htons(ETH_P_IP):
1722 opts2 |= IPV4_CS;
1723 ip_protocol = ip_hdr(skb)->protocol;
1724 break;
1725
1726 case htons(ETH_P_IPV6):
1727 opts2 |= IPV6_CS;
1728 ip_protocol = ipv6_hdr(skb)->nexthdr;
1729 break;
1730
1731 default:
1732 ip_protocol = IPPROTO_RAW;
1733 break;
1734 }
1735
1736 if (ip_protocol == IPPROTO_TCP)
1737 opts2 |= TCP_CS;
1738 else if (ip_protocol == IPPROTO_UDP)
1739 opts2 |= UDP_CS;
1740 else
1741 WARN_ON_ONCE(1);
1742
1743 opts2 |= transport_offset << TCPHO_SHIFT;
1744 }
1745
1746 desc->opts2 = cpu_to_le32(opts2);
1747 desc->opts1 = cpu_to_le32(opts1);
1748
1749 unavailable:
1750 return ret;
1751 }
1752
1753 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1754 {
1755 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1756 int remain, ret;
1757 u8 *tx_data;
1758
1759 __skb_queue_head_init(&skb_head);
1760 spin_lock(&tx_queue->lock);
1761 skb_queue_splice_init(tx_queue, &skb_head);
1762 spin_unlock(&tx_queue->lock);
1763
1764 tx_data = agg->head;
1765 agg->skb_num = 0;
1766 agg->skb_len = 0;
1767 remain = agg_buf_sz;
1768
1769 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1770 struct tx_desc *tx_desc;
1771 struct sk_buff *skb;
1772 unsigned int len;
1773 u32 offset;
1774
1775 skb = __skb_dequeue(&skb_head);
1776 if (!skb)
1777 break;
1778
1779 len = skb->len + sizeof(*tx_desc);
1780
1781 if (len > remain) {
1782 __skb_queue_head(&skb_head, skb);
1783 break;
1784 }
1785
1786 tx_data = tx_agg_align(tx_data);
1787 tx_desc = (struct tx_desc *)tx_data;
1788
1789 offset = (u32)skb_transport_offset(skb);
1790
1791 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1792 r8152_csum_workaround(tp, skb, &skb_head);
1793 continue;
1794 }
1795
1796 rtl_tx_vlan_tag(tx_desc, skb);
1797
1798 tx_data += sizeof(*tx_desc);
1799
1800 len = skb->len;
1801 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1802 struct net_device_stats *stats = &tp->netdev->stats;
1803
1804 stats->tx_dropped++;
1805 dev_kfree_skb_any(skb);
1806 tx_data -= sizeof(*tx_desc);
1807 continue;
1808 }
1809
1810 tx_data += len;
1811 agg->skb_len += len;
1812 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
1813
1814 dev_kfree_skb_any(skb);
1815
1816 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1817
1818 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
1819 break;
1820 }
1821
1822 if (!skb_queue_empty(&skb_head)) {
1823 spin_lock(&tx_queue->lock);
1824 skb_queue_splice(&skb_head, tx_queue);
1825 spin_unlock(&tx_queue->lock);
1826 }
1827
1828 netif_tx_lock(tp->netdev);
1829
1830 if (netif_queue_stopped(tp->netdev) &&
1831 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1832 netif_wake_queue(tp->netdev);
1833
1834 netif_tx_unlock(tp->netdev);
1835
1836 ret = usb_autopm_get_interface_async(tp->intf);
1837 if (ret < 0)
1838 goto out_tx_fill;
1839
1840 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1841 agg->head, (int)(tx_data - (u8 *)agg->head),
1842 (usb_complete_t)write_bulk_callback, agg);
1843
1844 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1845 if (ret < 0)
1846 usb_autopm_put_interface_async(tp->intf);
1847
1848 out_tx_fill:
1849 return ret;
1850 }
1851
1852 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1853 {
1854 u8 checksum = CHECKSUM_NONE;
1855 u32 opts2, opts3;
1856
1857 if (!(tp->netdev->features & NETIF_F_RXCSUM))
1858 goto return_result;
1859
1860 opts2 = le32_to_cpu(rx_desc->opts2);
1861 opts3 = le32_to_cpu(rx_desc->opts3);
1862
1863 if (opts2 & RD_IPV4_CS) {
1864 if (opts3 & IPF)
1865 checksum = CHECKSUM_NONE;
1866 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1867 checksum = CHECKSUM_UNNECESSARY;
1868 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1869 checksum = CHECKSUM_UNNECESSARY;
1870 } else if (opts2 & RD_IPV6_CS) {
1871 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1872 checksum = CHECKSUM_UNNECESSARY;
1873 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1874 checksum = CHECKSUM_UNNECESSARY;
1875 }
1876
1877 return_result:
1878 return checksum;
1879 }
1880
1881 static int rx_bottom(struct r8152 *tp, int budget)
1882 {
1883 unsigned long flags;
1884 struct list_head *cursor, *next, rx_queue;
1885 int ret = 0, work_done = 0;
1886 struct napi_struct *napi = &tp->napi;
1887
1888 if (!skb_queue_empty(&tp->rx_queue)) {
1889 while (work_done < budget) {
1890 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
1891 struct net_device *netdev = tp->netdev;
1892 struct net_device_stats *stats = &netdev->stats;
1893 unsigned int pkt_len;
1894
1895 if (!skb)
1896 break;
1897
1898 pkt_len = skb->len;
1899 napi_gro_receive(napi, skb);
1900 work_done++;
1901 stats->rx_packets++;
1902 stats->rx_bytes += pkt_len;
1903 }
1904 }
1905
1906 if (list_empty(&tp->rx_done))
1907 goto out1;
1908
1909 INIT_LIST_HEAD(&rx_queue);
1910 spin_lock_irqsave(&tp->rx_lock, flags);
1911 list_splice_init(&tp->rx_done, &rx_queue);
1912 spin_unlock_irqrestore(&tp->rx_lock, flags);
1913
1914 list_for_each_safe(cursor, next, &rx_queue) {
1915 struct rx_desc *rx_desc;
1916 struct rx_agg *agg;
1917 int len_used = 0;
1918 struct urb *urb;
1919 u8 *rx_data;
1920
1921 list_del_init(cursor);
1922
1923 agg = list_entry(cursor, struct rx_agg, list);
1924 urb = agg->urb;
1925 if (urb->actual_length < ETH_ZLEN)
1926 goto submit;
1927
1928 rx_desc = agg->head;
1929 rx_data = agg->head;
1930 len_used += sizeof(struct rx_desc);
1931
1932 while (urb->actual_length > len_used) {
1933 struct net_device *netdev = tp->netdev;
1934 struct net_device_stats *stats = &netdev->stats;
1935 unsigned int pkt_len;
1936 struct sk_buff *skb;
1937
1938 /* limite the skb numbers for rx_queue */
1939 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
1940 break;
1941
1942 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1943 if (pkt_len < ETH_ZLEN)
1944 break;
1945
1946 len_used += pkt_len;
1947 if (urb->actual_length < len_used)
1948 break;
1949
1950 pkt_len -= ETH_FCS_LEN;
1951 rx_data += sizeof(struct rx_desc);
1952
1953 skb = napi_alloc_skb(napi, pkt_len);
1954 if (!skb) {
1955 stats->rx_dropped++;
1956 goto find_next_rx;
1957 }
1958
1959 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1960 memcpy(skb->data, rx_data, pkt_len);
1961 skb_put(skb, pkt_len);
1962 skb->protocol = eth_type_trans(skb, netdev);
1963 rtl_rx_vlan_tag(rx_desc, skb);
1964 if (work_done < budget) {
1965 napi_gro_receive(napi, skb);
1966 work_done++;
1967 stats->rx_packets++;
1968 stats->rx_bytes += pkt_len;
1969 } else {
1970 __skb_queue_tail(&tp->rx_queue, skb);
1971 }
1972
1973 find_next_rx:
1974 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
1975 rx_desc = (struct rx_desc *)rx_data;
1976 len_used = (int)(rx_data - (u8 *)agg->head);
1977 len_used += sizeof(struct rx_desc);
1978 }
1979
1980 submit:
1981 if (!ret) {
1982 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1983 } else {
1984 urb->actual_length = 0;
1985 list_add_tail(&agg->list, next);
1986 }
1987 }
1988
1989 if (!list_empty(&rx_queue)) {
1990 spin_lock_irqsave(&tp->rx_lock, flags);
1991 list_splice_tail(&rx_queue, &tp->rx_done);
1992 spin_unlock_irqrestore(&tp->rx_lock, flags);
1993 }
1994
1995 out1:
1996 return work_done;
1997 }
1998
1999 static void tx_bottom(struct r8152 *tp)
2000 {
2001 int res;
2002
2003 do {
2004 struct tx_agg *agg;
2005
2006 if (skb_queue_empty(&tp->tx_queue))
2007 break;
2008
2009 agg = r8152_get_tx_agg(tp);
2010 if (!agg)
2011 break;
2012
2013 res = r8152_tx_agg_fill(tp, agg);
2014 if (res) {
2015 struct net_device *netdev = tp->netdev;
2016
2017 if (res == -ENODEV) {
2018 set_bit(RTL8152_UNPLUG, &tp->flags);
2019 netif_device_detach(netdev);
2020 } else {
2021 struct net_device_stats *stats = &netdev->stats;
2022 unsigned long flags;
2023
2024 netif_warn(tp, tx_err, netdev,
2025 "failed tx_urb %d\n", res);
2026 stats->tx_dropped += agg->skb_num;
2027
2028 spin_lock_irqsave(&tp->tx_lock, flags);
2029 list_add_tail(&agg->list, &tp->tx_free);
2030 spin_unlock_irqrestore(&tp->tx_lock, flags);
2031 }
2032 }
2033 } while (res == 0);
2034 }
2035
2036 static void bottom_half(struct r8152 *tp)
2037 {
2038 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2039 return;
2040
2041 if (!test_bit(WORK_ENABLE, &tp->flags))
2042 return;
2043
2044 /* When link down, the driver would cancel all bulks. */
2045 /* This avoid the re-submitting bulk */
2046 if (!netif_carrier_ok(tp->netdev))
2047 return;
2048
2049 clear_bit(SCHEDULE_NAPI, &tp->flags);
2050
2051 tx_bottom(tp);
2052 }
2053
2054 static int r8152_poll(struct napi_struct *napi, int budget)
2055 {
2056 struct r8152 *tp = container_of(napi, struct r8152, napi);
2057 int work_done;
2058
2059 work_done = rx_bottom(tp, budget);
2060 bottom_half(tp);
2061
2062 if (work_done < budget) {
2063 if (!napi_complete_done(napi, work_done))
2064 goto out;
2065 if (!list_empty(&tp->rx_done))
2066 napi_schedule(napi);
2067 else if (!skb_queue_empty(&tp->tx_queue) &&
2068 !list_empty(&tp->tx_free))
2069 napi_schedule(napi);
2070 }
2071
2072 out:
2073 return work_done;
2074 }
2075
2076 static
2077 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2078 {
2079 int ret;
2080
2081 /* The rx would be stopped, so skip submitting */
2082 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2083 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2084 return 0;
2085
2086 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
2087 agg->head, agg_buf_sz,
2088 (usb_complete_t)read_bulk_callback, agg);
2089
2090 ret = usb_submit_urb(agg->urb, mem_flags);
2091 if (ret == -ENODEV) {
2092 set_bit(RTL8152_UNPLUG, &tp->flags);
2093 netif_device_detach(tp->netdev);
2094 } else if (ret) {
2095 struct urb *urb = agg->urb;
2096 unsigned long flags;
2097
2098 urb->actual_length = 0;
2099 spin_lock_irqsave(&tp->rx_lock, flags);
2100 list_add_tail(&agg->list, &tp->rx_done);
2101 spin_unlock_irqrestore(&tp->rx_lock, flags);
2102
2103 netif_err(tp, rx_err, tp->netdev,
2104 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2105
2106 napi_schedule(&tp->napi);
2107 }
2108
2109 return ret;
2110 }
2111
2112 static void rtl_drop_queued_tx(struct r8152 *tp)
2113 {
2114 struct net_device_stats *stats = &tp->netdev->stats;
2115 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2116 struct sk_buff *skb;
2117
2118 if (skb_queue_empty(tx_queue))
2119 return;
2120
2121 __skb_queue_head_init(&skb_head);
2122 spin_lock_bh(&tx_queue->lock);
2123 skb_queue_splice_init(tx_queue, &skb_head);
2124 spin_unlock_bh(&tx_queue->lock);
2125
2126 while ((skb = __skb_dequeue(&skb_head))) {
2127 dev_kfree_skb(skb);
2128 stats->tx_dropped++;
2129 }
2130 }
2131
2132 static void rtl8152_tx_timeout(struct net_device *netdev)
2133 {
2134 struct r8152 *tp = netdev_priv(netdev);
2135
2136 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2137
2138 usb_queue_reset_device(tp->intf);
2139 }
2140
2141 static void rtl8152_set_rx_mode(struct net_device *netdev)
2142 {
2143 struct r8152 *tp = netdev_priv(netdev);
2144
2145 if (netif_carrier_ok(netdev)) {
2146 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2147 schedule_delayed_work(&tp->schedule, 0);
2148 }
2149 }
2150
2151 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2152 {
2153 struct r8152 *tp = netdev_priv(netdev);
2154 u32 mc_filter[2]; /* Multicast hash filter */
2155 __le32 tmp[2];
2156 u32 ocp_data;
2157
2158 netif_stop_queue(netdev);
2159 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2160 ocp_data &= ~RCR_ACPT_ALL;
2161 ocp_data |= RCR_AB | RCR_APM;
2162
2163 if (netdev->flags & IFF_PROMISC) {
2164 /* Unconditionally log net taps. */
2165 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2166 ocp_data |= RCR_AM | RCR_AAP;
2167 mc_filter[1] = 0xffffffff;
2168 mc_filter[0] = 0xffffffff;
2169 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2170 (netdev->flags & IFF_ALLMULTI)) {
2171 /* Too many to filter perfectly -- accept all multicasts. */
2172 ocp_data |= RCR_AM;
2173 mc_filter[1] = 0xffffffff;
2174 mc_filter[0] = 0xffffffff;
2175 } else {
2176 struct netdev_hw_addr *ha;
2177
2178 mc_filter[1] = 0;
2179 mc_filter[0] = 0;
2180 netdev_for_each_mc_addr(ha, netdev) {
2181 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2182
2183 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2184 ocp_data |= RCR_AM;
2185 }
2186 }
2187
2188 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2189 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2190
2191 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2192 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2193 netif_wake_queue(netdev);
2194 }
2195
2196 static netdev_features_t
2197 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2198 netdev_features_t features)
2199 {
2200 u32 mss = skb_shinfo(skb)->gso_size;
2201 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2202 int offset = skb_transport_offset(skb);
2203
2204 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2205 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2206 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2207 features &= ~NETIF_F_GSO_MASK;
2208
2209 return features;
2210 }
2211
2212 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2213 struct net_device *netdev)
2214 {
2215 struct r8152 *tp = netdev_priv(netdev);
2216
2217 skb_tx_timestamp(skb);
2218
2219 skb_queue_tail(&tp->tx_queue, skb);
2220
2221 if (!list_empty(&tp->tx_free)) {
2222 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2223 set_bit(SCHEDULE_NAPI, &tp->flags);
2224 schedule_delayed_work(&tp->schedule, 0);
2225 } else {
2226 usb_mark_last_busy(tp->udev);
2227 napi_schedule(&tp->napi);
2228 }
2229 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2230 netif_stop_queue(netdev);
2231 }
2232
2233 return NETDEV_TX_OK;
2234 }
2235
2236 static void r8152b_reset_packet_filter(struct r8152 *tp)
2237 {
2238 u32 ocp_data;
2239
2240 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2241 ocp_data &= ~FMC_FCR_MCU_EN;
2242 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2243 ocp_data |= FMC_FCR_MCU_EN;
2244 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2245 }
2246
2247 static void rtl8152_nic_reset(struct r8152 *tp)
2248 {
2249 int i;
2250
2251 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2252
2253 for (i = 0; i < 1000; i++) {
2254 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2255 break;
2256 usleep_range(100, 400);
2257 }
2258 }
2259
2260 static void set_tx_qlen(struct r8152 *tp)
2261 {
2262 struct net_device *netdev = tp->netdev;
2263
2264 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +
2265 sizeof(struct tx_desc));
2266 }
2267
2268 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2269 {
2270 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2271 }
2272
2273 static void rtl_set_eee_plus(struct r8152 *tp)
2274 {
2275 u32 ocp_data;
2276 u8 speed;
2277
2278 speed = rtl8152_get_speed(tp);
2279 if (speed & _10bps) {
2280 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2281 ocp_data |= EEEP_CR_EEEP_TX;
2282 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2283 } else {
2284 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2285 ocp_data &= ~EEEP_CR_EEEP_TX;
2286 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2287 }
2288 }
2289
2290 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2291 {
2292 u32 ocp_data;
2293
2294 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2295 if (enable)
2296 ocp_data |= RXDY_GATED_EN;
2297 else
2298 ocp_data &= ~RXDY_GATED_EN;
2299 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2300 }
2301
2302 static int rtl_start_rx(struct r8152 *tp)
2303 {
2304 int i, ret = 0;
2305
2306 INIT_LIST_HEAD(&tp->rx_done);
2307 for (i = 0; i < RTL8152_MAX_RX; i++) {
2308 INIT_LIST_HEAD(&tp->rx_info[i].list);
2309 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2310 if (ret)
2311 break;
2312 }
2313
2314 if (ret && ++i < RTL8152_MAX_RX) {
2315 struct list_head rx_queue;
2316 unsigned long flags;
2317
2318 INIT_LIST_HEAD(&rx_queue);
2319
2320 do {
2321 struct rx_agg *agg = &tp->rx_info[i++];
2322 struct urb *urb = agg->urb;
2323
2324 urb->actual_length = 0;
2325 list_add_tail(&agg->list, &rx_queue);
2326 } while (i < RTL8152_MAX_RX);
2327
2328 spin_lock_irqsave(&tp->rx_lock, flags);
2329 list_splice_tail(&rx_queue, &tp->rx_done);
2330 spin_unlock_irqrestore(&tp->rx_lock, flags);
2331 }
2332
2333 return ret;
2334 }
2335
2336 static int rtl_stop_rx(struct r8152 *tp)
2337 {
2338 int i;
2339
2340 for (i = 0; i < RTL8152_MAX_RX; i++)
2341 usb_kill_urb(tp->rx_info[i].urb);
2342
2343 while (!skb_queue_empty(&tp->rx_queue))
2344 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2345
2346 return 0;
2347 }
2348
2349 static int rtl_enable(struct r8152 *tp)
2350 {
2351 u32 ocp_data;
2352
2353 r8152b_reset_packet_filter(tp);
2354
2355 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2356 ocp_data |= CR_RE | CR_TE;
2357 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2358
2359 rxdy_gated_en(tp, false);
2360
2361 return 0;
2362 }
2363
2364 static int rtl8152_enable(struct r8152 *tp)
2365 {
2366 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2367 return -ENODEV;
2368
2369 set_tx_qlen(tp);
2370 rtl_set_eee_plus(tp);
2371
2372 return rtl_enable(tp);
2373 }
2374
2375 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2376 {
2377 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2378 OWN_UPDATE | OWN_CLEAR);
2379 }
2380
2381 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2382 {
2383 u32 ocp_data = tp->coalesce / 8;
2384
2385 switch (tp->version) {
2386 case RTL_VER_03:
2387 case RTL_VER_04:
2388 case RTL_VER_05:
2389 case RTL_VER_06:
2390 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2391 ocp_data);
2392 break;
2393
2394 case RTL_VER_08:
2395 case RTL_VER_09:
2396 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
2397 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
2398 */
2399 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2400 128 / 8);
2401 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
2402 ocp_data);
2403 r8153b_rx_agg_chg_indicate(tp);
2404 break;
2405
2406 default:
2407 break;
2408 }
2409 }
2410
2411 static void r8153_set_rx_early_size(struct r8152 *tp)
2412 {
2413 u32 ocp_data = agg_buf_sz - rx_reserved_size(tp->netdev->mtu);
2414
2415 switch (tp->version) {
2416 case RTL_VER_03:
2417 case RTL_VER_04:
2418 case RTL_VER_05:
2419 case RTL_VER_06:
2420 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2421 ocp_data / 4);
2422 break;
2423 case RTL_VER_08:
2424 case RTL_VER_09:
2425 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2426 ocp_data / 8);
2427 r8153b_rx_agg_chg_indicate(tp);
2428 break;
2429 default:
2430 WARN_ON_ONCE(1);
2431 break;
2432 }
2433 }
2434
2435 static int rtl8153_enable(struct r8152 *tp)
2436 {
2437 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2438 return -ENODEV;
2439
2440 set_tx_qlen(tp);
2441 rtl_set_eee_plus(tp);
2442 r8153_set_rx_early_timeout(tp);
2443 r8153_set_rx_early_size(tp);
2444
2445 return rtl_enable(tp);
2446 }
2447
2448 static void rtl_disable(struct r8152 *tp)
2449 {
2450 u32 ocp_data;
2451 int i;
2452
2453 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2454 rtl_drop_queued_tx(tp);
2455 return;
2456 }
2457
2458 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2459 ocp_data &= ~RCR_ACPT_ALL;
2460 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2461
2462 rtl_drop_queued_tx(tp);
2463
2464 for (i = 0; i < RTL8152_MAX_TX; i++)
2465 usb_kill_urb(tp->tx_info[i].urb);
2466
2467 rxdy_gated_en(tp, true);
2468
2469 for (i = 0; i < 1000; i++) {
2470 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2471 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2472 break;
2473 usleep_range(1000, 2000);
2474 }
2475
2476 for (i = 0; i < 1000; i++) {
2477 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2478 break;
2479 usleep_range(1000, 2000);
2480 }
2481
2482 rtl_stop_rx(tp);
2483
2484 rtl8152_nic_reset(tp);
2485 }
2486
2487 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2488 {
2489 u32 ocp_data;
2490
2491 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2492 if (enable)
2493 ocp_data |= POWER_CUT;
2494 else
2495 ocp_data &= ~POWER_CUT;
2496 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2497
2498 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2499 ocp_data &= ~RESUME_INDICATE;
2500 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2501 }
2502
2503 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2504 {
2505 u32 ocp_data;
2506
2507 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2508 if (enable)
2509 ocp_data |= CPCR_RX_VLAN;
2510 else
2511 ocp_data &= ~CPCR_RX_VLAN;
2512 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2513 }
2514
2515 static int rtl8152_set_features(struct net_device *dev,
2516 netdev_features_t features)
2517 {
2518 netdev_features_t changed = features ^ dev->features;
2519 struct r8152 *tp = netdev_priv(dev);
2520 int ret;
2521
2522 ret = usb_autopm_get_interface(tp->intf);
2523 if (ret < 0)
2524 goto out;
2525
2526 mutex_lock(&tp->control);
2527
2528 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2529 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2530 rtl_rx_vlan_en(tp, true);
2531 else
2532 rtl_rx_vlan_en(tp, false);
2533 }
2534
2535 mutex_unlock(&tp->control);
2536
2537 usb_autopm_put_interface(tp->intf);
2538
2539 out:
2540 return ret;
2541 }
2542
2543 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2544
2545 static u32 __rtl_get_wol(struct r8152 *tp)
2546 {
2547 u32 ocp_data;
2548 u32 wolopts = 0;
2549
2550 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2551 if (ocp_data & LINK_ON_WAKE_EN)
2552 wolopts |= WAKE_PHY;
2553
2554 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2555 if (ocp_data & UWF_EN)
2556 wolopts |= WAKE_UCAST;
2557 if (ocp_data & BWF_EN)
2558 wolopts |= WAKE_BCAST;
2559 if (ocp_data & MWF_EN)
2560 wolopts |= WAKE_MCAST;
2561
2562 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2563 if (ocp_data & MAGIC_EN)
2564 wolopts |= WAKE_MAGIC;
2565
2566 return wolopts;
2567 }
2568
2569 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2570 {
2571 u32 ocp_data;
2572
2573 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2574
2575 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2576 ocp_data &= ~LINK_ON_WAKE_EN;
2577 if (wolopts & WAKE_PHY)
2578 ocp_data |= LINK_ON_WAKE_EN;
2579 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2580
2581 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2582 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
2583 if (wolopts & WAKE_UCAST)
2584 ocp_data |= UWF_EN;
2585 if (wolopts & WAKE_BCAST)
2586 ocp_data |= BWF_EN;
2587 if (wolopts & WAKE_MCAST)
2588 ocp_data |= MWF_EN;
2589 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2590
2591 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2592
2593 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2594 ocp_data &= ~MAGIC_EN;
2595 if (wolopts & WAKE_MAGIC)
2596 ocp_data |= MAGIC_EN;
2597 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2598
2599 if (wolopts & WAKE_ANY)
2600 device_set_wakeup_enable(&tp->udev->dev, true);
2601 else
2602 device_set_wakeup_enable(&tp->udev->dev, false);
2603 }
2604
2605 static void r8153_mac_clk_spd(struct r8152 *tp, bool enable)
2606 {
2607 /* MAC clock speed down */
2608 if (enable) {
2609 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
2610 ALDPS_SPDWN_RATIO);
2611 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2,
2612 EEE_SPDWN_RATIO);
2613 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
2614 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
2615 U1U2_SPDWN_EN | L1_SPDWN_EN);
2616 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
2617 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
2618 TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN |
2619 TP1000_SPDWN_EN);
2620 } else {
2621 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
2622 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
2623 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
2624 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
2625 }
2626 }
2627
2628 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2629 {
2630 u8 u1u2[8];
2631
2632 if (enable)
2633 memset(u1u2, 0xff, sizeof(u1u2));
2634 else
2635 memset(u1u2, 0x00, sizeof(u1u2));
2636
2637 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2638 }
2639
2640 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
2641 {
2642 u32 ocp_data;
2643
2644 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
2645 if (enable)
2646 ocp_data |= LPM_U1U2_EN;
2647 else
2648 ocp_data &= ~LPM_U1U2_EN;
2649
2650 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
2651 }
2652
2653 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2654 {
2655 u32 ocp_data;
2656
2657 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2658 if (enable)
2659 ocp_data |= U2P3_ENABLE;
2660 else
2661 ocp_data &= ~U2P3_ENABLE;
2662 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2663 }
2664
2665 static void r8153b_ups_flags_w1w0(struct r8152 *tp, u32 set, u32 clear)
2666 {
2667 u32 ocp_data;
2668
2669 ocp_data = ocp_read_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS);
2670 ocp_data &= ~clear;
2671 ocp_data |= set;
2672 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ocp_data);
2673 }
2674
2675 static void r8153b_green_en(struct r8152 *tp, bool enable)
2676 {
2677 u16 data;
2678
2679 if (enable) {
2680 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */
2681 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
2682 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
2683 } else {
2684 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
2685 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
2686 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
2687 }
2688
2689 data = sram_read(tp, SRAM_GREEN_CFG);
2690 data |= GREEN_ETH_EN;
2691 sram_write(tp, SRAM_GREEN_CFG, data);
2692
2693 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_GREEN, 0);
2694 }
2695
2696 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
2697 {
2698 u16 data;
2699 int i;
2700
2701 for (i = 0; i < 500; i++) {
2702 data = ocp_reg_read(tp, OCP_PHY_STATUS);
2703 data &= PHY_STAT_MASK;
2704 if (desired) {
2705 if (data == desired)
2706 break;
2707 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
2708 data == PHY_STAT_EXT_INIT) {
2709 break;
2710 }
2711
2712 msleep(20);
2713 }
2714
2715 return data;
2716 }
2717
2718 static void r8153b_ups_en(struct r8152 *tp, bool enable)
2719 {
2720 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
2721
2722 if (enable) {
2723 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
2724 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2725
2726 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
2727 ocp_data |= BIT(0);
2728 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
2729 } else {
2730 u16 data;
2731
2732 ocp_data &= ~(UPS_EN | USP_PREWAKE);
2733 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2734
2735 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
2736 ocp_data &= ~BIT(0);
2737 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
2738
2739 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2740 ocp_data &= ~PCUT_STATUS;
2741 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2742
2743 data = r8153_phy_status(tp, 0);
2744
2745 switch (data) {
2746 case PHY_STAT_PWRDN:
2747 case PHY_STAT_EXT_INIT:
2748 r8153b_green_en(tp,
2749 test_bit(GREEN_ETHERNET, &tp->flags));
2750
2751 data = r8152_mdio_read(tp, MII_BMCR);
2752 data &= ~BMCR_PDOWN;
2753 data |= BMCR_RESET;
2754 r8152_mdio_write(tp, MII_BMCR, data);
2755
2756 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
2757 /* fall through */
2758
2759 default:
2760 if (data != PHY_STAT_LAN_ON)
2761 netif_warn(tp, link, tp->netdev,
2762 "PHY not ready");
2763 break;
2764 }
2765 }
2766 }
2767
2768 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2769 {
2770 u32 ocp_data;
2771
2772 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2773 if (enable)
2774 ocp_data |= PWR_EN | PHASE2_EN;
2775 else
2776 ocp_data &= ~(PWR_EN | PHASE2_EN);
2777 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2778
2779 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2780 ocp_data &= ~PCUT_STATUS;
2781 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2782 }
2783
2784 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
2785 {
2786 u32 ocp_data;
2787
2788 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2789 if (enable)
2790 ocp_data |= PWR_EN | PHASE2_EN;
2791 else
2792 ocp_data &= ~PWR_EN;
2793 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2794
2795 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2796 ocp_data &= ~PCUT_STATUS;
2797 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2798 }
2799
2800 static void r8153b_queue_wake(struct r8152 *tp, bool enable)
2801 {
2802 u32 ocp_data;
2803
2804 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38a);
2805 if (enable)
2806 ocp_data |= BIT(0);
2807 else
2808 ocp_data &= ~BIT(0);
2809 ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38a, ocp_data);
2810
2811 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38c);
2812 ocp_data &= ~BIT(0);
2813 ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38c, ocp_data);
2814 }
2815
2816 static bool rtl_can_wakeup(struct r8152 *tp)
2817 {
2818 struct usb_device *udev = tp->udev;
2819
2820 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
2821 }
2822
2823 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2824 {
2825 if (enable) {
2826 u32 ocp_data;
2827
2828 __rtl_set_wol(tp, WAKE_ANY);
2829
2830 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2831
2832 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2833 ocp_data |= LINK_OFF_WAKE_EN;
2834 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2835
2836 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2837 } else {
2838 u32 ocp_data;
2839
2840 __rtl_set_wol(tp, tp->saved_wolopts);
2841
2842 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2843
2844 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2845 ocp_data &= ~LINK_OFF_WAKE_EN;
2846 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2847
2848 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2849 }
2850 }
2851
2852 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
2853 {
2854 if (enable) {
2855 r8153_u1u2en(tp, false);
2856 r8153_u2p3en(tp, false);
2857 r8153_mac_clk_spd(tp, true);
2858 rtl_runtime_suspend_enable(tp, true);
2859 } else {
2860 rtl_runtime_suspend_enable(tp, false);
2861 r8153_mac_clk_spd(tp, false);
2862
2863 switch (tp->version) {
2864 case RTL_VER_03:
2865 case RTL_VER_04:
2866 break;
2867 case RTL_VER_05:
2868 case RTL_VER_06:
2869 default:
2870 r8153_u2p3en(tp, true);
2871 break;
2872 }
2873
2874 r8153_u1u2en(tp, true);
2875 }
2876 }
2877
2878 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
2879 {
2880 if (enable) {
2881 r8153b_queue_wake(tp, true);
2882 r8153b_u1u2en(tp, false);
2883 r8153_u2p3en(tp, false);
2884 rtl_runtime_suspend_enable(tp, true);
2885 r8153b_ups_en(tp, true);
2886 } else {
2887 r8153b_ups_en(tp, false);
2888 r8153b_queue_wake(tp, false);
2889 rtl_runtime_suspend_enable(tp, false);
2890 r8153_u2p3en(tp, true);
2891 r8153b_u1u2en(tp, true);
2892 }
2893 }
2894
2895 static void r8153_teredo_off(struct r8152 *tp)
2896 {
2897 u32 ocp_data;
2898
2899 switch (tp->version) {
2900 case RTL_VER_01:
2901 case RTL_VER_02:
2902 case RTL_VER_03:
2903 case RTL_VER_04:
2904 case RTL_VER_05:
2905 case RTL_VER_06:
2906 case RTL_VER_07:
2907 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2908 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
2909 OOB_TEREDO_EN);
2910 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2911 break;
2912
2913 case RTL_VER_08:
2914 case RTL_VER_09:
2915 /* The bit 0 ~ 7 are relative with teredo settings. They are
2916 * W1C (write 1 to clear), so set all 1 to disable it.
2917 */
2918 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
2919 break;
2920
2921 default:
2922 break;
2923 }
2924
2925 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2926 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2927 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2928 }
2929
2930 static void rtl_reset_bmu(struct r8152 *tp)
2931 {
2932 u32 ocp_data;
2933
2934 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
2935 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
2936 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2937 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
2938 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2939 }
2940
2941 static void r8152_aldps_en(struct r8152 *tp, bool enable)
2942 {
2943 if (enable) {
2944 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2945 LINKENA | DIS_SDSAVE);
2946 } else {
2947 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
2948 DIS_SDSAVE);
2949 msleep(20);
2950 }
2951 }
2952
2953 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
2954 {
2955 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
2956 ocp_reg_write(tp, OCP_EEE_DATA, reg);
2957 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
2958 }
2959
2960 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
2961 {
2962 u16 data;
2963
2964 r8152_mmd_indirect(tp, dev, reg);
2965 data = ocp_reg_read(tp, OCP_EEE_DATA);
2966 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2967
2968 return data;
2969 }
2970
2971 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
2972 {
2973 r8152_mmd_indirect(tp, dev, reg);
2974 ocp_reg_write(tp, OCP_EEE_DATA, data);
2975 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2976 }
2977
2978 static void r8152_eee_en(struct r8152 *tp, bool enable)
2979 {
2980 u16 config1, config2, config3;
2981 u32 ocp_data;
2982
2983 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2984 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
2985 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
2986 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
2987
2988 if (enable) {
2989 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2990 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
2991 config1 |= sd_rise_time(1);
2992 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
2993 config3 |= fast_snr(42);
2994 } else {
2995 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
2996 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
2997 RX_QUIET_EN);
2998 config1 |= sd_rise_time(7);
2999 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
3000 config3 |= fast_snr(511);
3001 }
3002
3003 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3004 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3005 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3006 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
3007 }
3008
3009 static void r8152b_enable_eee(struct r8152 *tp)
3010 {
3011 r8152_eee_en(tp, true);
3012 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3013 }
3014
3015 static void r8152b_enable_fc(struct r8152 *tp)
3016 {
3017 u16 anar;
3018
3019 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3020 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3021 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3022 }
3023
3024 static void rtl8152_disable(struct r8152 *tp)
3025 {
3026 r8152_aldps_en(tp, false);
3027 rtl_disable(tp);
3028 r8152_aldps_en(tp, true);
3029 }
3030
3031 static void r8152b_hw_phy_cfg(struct r8152 *tp)
3032 {
3033 r8152b_enable_eee(tp);
3034 r8152_aldps_en(tp, true);
3035 r8152b_enable_fc(tp);
3036
3037 set_bit(PHY_RESET, &tp->flags);
3038 }
3039
3040 static void r8152b_exit_oob(struct r8152 *tp)
3041 {
3042 u32 ocp_data;
3043 int i;
3044
3045 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3046 ocp_data &= ~RCR_ACPT_ALL;
3047 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3048
3049 rxdy_gated_en(tp, true);
3050 r8153_teredo_off(tp);
3051 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3052 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
3053
3054 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3055 ocp_data &= ~NOW_IS_OOB;
3056 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3057
3058 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3059 ocp_data &= ~MCU_BORW_EN;
3060 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3061
3062 for (i = 0; i < 1000; i++) {
3063 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3064 if (ocp_data & LINK_LIST_READY)
3065 break;
3066 usleep_range(1000, 2000);
3067 }
3068
3069 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3070 ocp_data |= RE_INIT_LL;
3071 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3072
3073 for (i = 0; i < 1000; i++) {
3074 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3075 if (ocp_data & LINK_LIST_READY)
3076 break;
3077 usleep_range(1000, 2000);
3078 }
3079
3080 rtl8152_nic_reset(tp);
3081
3082 /* rx share fifo credit full threshold */
3083 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3084
3085 if (tp->udev->speed == USB_SPEED_FULL ||
3086 tp->udev->speed == USB_SPEED_LOW) {
3087 /* rx share fifo credit near full threshold */
3088 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3089 RXFIFO_THR2_FULL);
3090 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3091 RXFIFO_THR3_FULL);
3092 } else {
3093 /* rx share fifo credit near full threshold */
3094 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3095 RXFIFO_THR2_HIGH);
3096 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3097 RXFIFO_THR3_HIGH);
3098 }
3099
3100 /* TX share fifo free credit full threshold */
3101 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
3102
3103 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
3104 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
3105 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
3106 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
3107
3108 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
3109
3110 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
3111
3112 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
3113 ocp_data |= TCR0_AUTO_FIFO;
3114 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
3115 }
3116
3117 static void r8152b_enter_oob(struct r8152 *tp)
3118 {
3119 u32 ocp_data;
3120 int i;
3121
3122 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3123 ocp_data &= ~NOW_IS_OOB;
3124 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3125
3126 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
3127 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
3128 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
3129
3130 rtl_disable(tp);
3131
3132 for (i = 0; i < 1000; i++) {
3133 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3134 if (ocp_data & LINK_LIST_READY)
3135 break;
3136 usleep_range(1000, 2000);
3137 }
3138
3139 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3140 ocp_data |= RE_INIT_LL;
3141 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3142
3143 for (i = 0; i < 1000; i++) {
3144 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3145 if (ocp_data & LINK_LIST_READY)
3146 break;
3147 usleep_range(1000, 2000);
3148 }
3149
3150 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
3151
3152 rtl_rx_vlan_en(tp, true);
3153
3154 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
3155 ocp_data |= ALDPS_PROXY_MODE;
3156 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
3157
3158 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3159 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3160 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3161
3162 rxdy_gated_en(tp, false);
3163
3164 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3165 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3166 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3167 }
3168
3169 static int r8153_patch_request(struct r8152 *tp, bool request)
3170 {
3171 u16 data;
3172 int i;
3173
3174 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
3175 if (request)
3176 data |= PATCH_REQUEST;
3177 else
3178 data &= ~PATCH_REQUEST;
3179 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
3180
3181 for (i = 0; request && i < 5000; i++) {
3182 usleep_range(1000, 2000);
3183 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)
3184 break;
3185 }
3186
3187 if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
3188 netif_err(tp, drv, tp->netdev, "patch request fail\n");
3189 r8153_patch_request(tp, false);
3190 return -ETIME;
3191 } else {
3192 return 0;
3193 }
3194 }
3195
3196 static void r8153_aldps_en(struct r8152 *tp, bool enable)
3197 {
3198 u16 data;
3199
3200 data = ocp_reg_read(tp, OCP_POWER_CFG);
3201 if (enable) {
3202 data |= EN_ALDPS;
3203 ocp_reg_write(tp, OCP_POWER_CFG, data);
3204 } else {
3205 int i;
3206
3207 data &= ~EN_ALDPS;
3208 ocp_reg_write(tp, OCP_POWER_CFG, data);
3209 for (i = 0; i < 20; i++) {
3210 usleep_range(1000, 2000);
3211 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
3212 break;
3213 }
3214 }
3215 }
3216
3217 static void r8153b_aldps_en(struct r8152 *tp, bool enable)
3218 {
3219 r8153_aldps_en(tp, enable);
3220
3221 if (enable)
3222 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_ALDPS, 0);
3223 else
3224 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_ALDPS);
3225 }
3226
3227 static void r8153_eee_en(struct r8152 *tp, bool enable)
3228 {
3229 u32 ocp_data;
3230 u16 config;
3231
3232 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3233 config = ocp_reg_read(tp, OCP_EEE_CFG);
3234
3235 if (enable) {
3236 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3237 config |= EEE10_EN;
3238 } else {
3239 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3240 config &= ~EEE10_EN;
3241 }
3242
3243 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3244 ocp_reg_write(tp, OCP_EEE_CFG, config);
3245 }
3246
3247 static void r8153b_eee_en(struct r8152 *tp, bool enable)
3248 {
3249 r8153_eee_en(tp, enable);
3250
3251 if (enable)
3252 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_EEE, 0);
3253 else
3254 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_EEE);
3255 }
3256
3257 static void r8153b_enable_fc(struct r8152 *tp)
3258 {
3259 r8152b_enable_fc(tp);
3260 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_FLOW_CTR, 0);
3261 }
3262
3263 static void r8153_hw_phy_cfg(struct r8152 *tp)
3264 {
3265 u32 ocp_data;
3266 u16 data;
3267
3268 /* disable ALDPS before updating the PHY parameters */
3269 r8153_aldps_en(tp, false);
3270
3271 /* disable EEE before updating the PHY parameters */
3272 r8153_eee_en(tp, false);
3273 ocp_reg_write(tp, OCP_EEE_ADV, 0);
3274
3275 if (tp->version == RTL_VER_03) {
3276 data = ocp_reg_read(tp, OCP_EEE_CFG);
3277 data &= ~CTAP_SHORT_EN;
3278 ocp_reg_write(tp, OCP_EEE_CFG, data);
3279 }
3280
3281 data = ocp_reg_read(tp, OCP_POWER_CFG);
3282 data |= EEE_CLKDIV_EN;
3283 ocp_reg_write(tp, OCP_POWER_CFG, data);
3284
3285 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
3286 data |= EN_10M_BGOFF;
3287 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
3288 data = ocp_reg_read(tp, OCP_POWER_CFG);
3289 data |= EN_10M_PLLOFF;
3290 ocp_reg_write(tp, OCP_POWER_CFG, data);
3291 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
3292
3293 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3294 ocp_data |= PFM_PWM_SWITCH;
3295 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3296
3297 /* Enable LPF corner auto tune */
3298 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
3299
3300 /* Adjust 10M Amplitude */
3301 sram_write(tp, SRAM_10M_AMP1, 0x00af);
3302 sram_write(tp, SRAM_10M_AMP2, 0x0208);
3303
3304 r8153_eee_en(tp, true);
3305 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3306
3307 r8153_aldps_en(tp, true);
3308 r8152b_enable_fc(tp);
3309
3310 switch (tp->version) {
3311 case RTL_VER_03:
3312 case RTL_VER_04:
3313 break;
3314 case RTL_VER_05:
3315 case RTL_VER_06:
3316 default:
3317 r8153_u2p3en(tp, true);
3318 break;
3319 }
3320
3321 set_bit(PHY_RESET, &tp->flags);
3322 }
3323
3324 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
3325 {
3326 u32 ocp_data;
3327
3328 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
3329 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
3330 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
3331 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
3332
3333 return ocp_data;
3334 }
3335
3336 static void r8153b_hw_phy_cfg(struct r8152 *tp)
3337 {
3338 u32 ocp_data, ups_flags = 0;
3339 u16 data;
3340
3341 /* disable ALDPS before updating the PHY parameters */
3342 r8153b_aldps_en(tp, false);
3343
3344 /* disable EEE before updating the PHY parameters */
3345 r8153b_eee_en(tp, false);
3346 ocp_reg_write(tp, OCP_EEE_ADV, 0);
3347
3348 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
3349
3350 data = sram_read(tp, SRAM_GREEN_CFG);
3351 data |= R_TUNE_EN;
3352 sram_write(tp, SRAM_GREEN_CFG, data);
3353 data = ocp_reg_read(tp, OCP_NCTL_CFG);
3354 data |= PGA_RETURN_EN;
3355 ocp_reg_write(tp, OCP_NCTL_CFG, data);
3356
3357 /* ADC Bias Calibration:
3358 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
3359 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
3360 * ADC ioffset.
3361 */
3362 ocp_data = r8152_efuse_read(tp, 0x7d);
3363 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
3364 if (data != 0xffff)
3365 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
3366
3367 /* ups mode tx-link-pulse timing adjustment:
3368 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
3369 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
3370 */
3371 ocp_data = ocp_reg_read(tp, 0xc426);
3372 ocp_data &= 0x3fff;
3373 if (ocp_data) {
3374 u32 swr_cnt_1ms_ini;
3375
3376 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
3377 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
3378 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
3379 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
3380 }
3381
3382 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3383 ocp_data |= PFM_PWM_SWITCH;
3384 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3385
3386 /* Advnace EEE */
3387 if (!r8153_patch_request(tp, true)) {
3388 data = ocp_reg_read(tp, OCP_POWER_CFG);
3389 data |= EEE_CLKDIV_EN;
3390 ocp_reg_write(tp, OCP_POWER_CFG, data);
3391
3392 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
3393 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
3394 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
3395
3396 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
3397 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
3398
3399 ups_flags |= UPS_FLAGS_EN_10M_CKDIV | UPS_FLAGS_250M_CKDIV |
3400 UPS_FLAGS_EN_EEE_CKDIV | UPS_FLAGS_EEE_CMOD_LV_EN |
3401 UPS_FLAGS_EEE_PLLOFF_GIGA;
3402
3403 r8153_patch_request(tp, false);
3404 }
3405
3406 r8153b_ups_flags_w1w0(tp, ups_flags, 0);
3407
3408 r8153b_eee_en(tp, true);
3409 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3410
3411 r8153b_aldps_en(tp, true);
3412 r8153b_enable_fc(tp);
3413 r8153_u2p3en(tp, true);
3414
3415 set_bit(PHY_RESET, &tp->flags);
3416 }
3417
3418 static void r8153_first_init(struct r8152 *tp)
3419 {
3420 u32 ocp_data;
3421 int i;
3422
3423 r8153_mac_clk_spd(tp, false);
3424 rxdy_gated_en(tp, true);
3425 r8153_teredo_off(tp);
3426
3427 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3428 ocp_data &= ~RCR_ACPT_ALL;
3429 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3430
3431 rtl8152_nic_reset(tp);
3432 rtl_reset_bmu(tp);
3433
3434 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3435 ocp_data &= ~NOW_IS_OOB;
3436 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3437
3438 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3439 ocp_data &= ~MCU_BORW_EN;
3440 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3441
3442 for (i = 0; i < 1000; i++) {
3443 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3444 if (ocp_data & LINK_LIST_READY)
3445 break;
3446 usleep_range(1000, 2000);
3447 }
3448
3449 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3450 ocp_data |= RE_INIT_LL;
3451 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3452
3453 for (i = 0; i < 1000; i++) {
3454 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3455 if (ocp_data & LINK_LIST_READY)
3456 break;
3457 usleep_range(1000, 2000);
3458 }
3459
3460 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
3461
3462 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3463 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
3464 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
3465
3466 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
3467 ocp_data |= TCR0_AUTO_FIFO;
3468 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
3469
3470 rtl8152_nic_reset(tp);
3471
3472 /* rx share fifo credit full threshold */
3473 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3474 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
3475 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
3476 /* TX share fifo free credit full threshold */
3477 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
3478 }
3479
3480 static void r8153_enter_oob(struct r8152 *tp)
3481 {
3482 u32 ocp_data;
3483 int i;
3484
3485 r8153_mac_clk_spd(tp, true);
3486
3487 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3488 ocp_data &= ~NOW_IS_OOB;
3489 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3490
3491 rtl_disable(tp);
3492 rtl_reset_bmu(tp);
3493
3494 for (i = 0; i < 1000; i++) {
3495 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3496 if (ocp_data & LINK_LIST_READY)
3497 break;
3498 usleep_range(1000, 2000);
3499 }
3500
3501 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3502 ocp_data |= RE_INIT_LL;
3503 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3504
3505 for (i = 0; i < 1000; i++) {
3506 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3507 if (ocp_data & LINK_LIST_READY)
3508 break;
3509 usleep_range(1000, 2000);
3510 }
3511
3512 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3513 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
3514
3515 switch (tp->version) {
3516 case RTL_VER_03:
3517 case RTL_VER_04:
3518 case RTL_VER_05:
3519 case RTL_VER_06:
3520 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3521 ocp_data &= ~TEREDO_WAKE_MASK;
3522 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3523 break;
3524
3525 case RTL_VER_08:
3526 case RTL_VER_09:
3527 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
3528 * type. Set it to zero. bits[7:0] are the W1C bits about
3529 * the events. Set them to all 1 to clear them.
3530 */
3531 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
3532 break;
3533
3534 default:
3535 break;
3536 }
3537
3538 rtl_rx_vlan_en(tp, true);
3539
3540 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
3541 ocp_data |= ALDPS_PROXY_MODE;
3542 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
3543
3544 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3545 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3546 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3547
3548 rxdy_gated_en(tp, false);
3549
3550 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3551 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3552 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3553 }
3554
3555 static void rtl8153_disable(struct r8152 *tp)
3556 {
3557 r8153_aldps_en(tp, false);
3558 rtl_disable(tp);
3559 rtl_reset_bmu(tp);
3560 r8153_aldps_en(tp, true);
3561 }
3562
3563 static void rtl8153b_disable(struct r8152 *tp)
3564 {
3565 r8153b_aldps_en(tp, false);
3566 rtl_disable(tp);
3567 rtl_reset_bmu(tp);
3568 r8153b_aldps_en(tp, true);
3569 }
3570
3571 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
3572 {
3573 u16 bmcr, anar, gbcr;
3574 enum spd_duplex speed_duplex;
3575 int ret = 0;
3576
3577 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3578 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
3579 ADVERTISE_100HALF | ADVERTISE_100FULL);
3580 if (tp->mii.supports_gmii) {
3581 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
3582 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3583 } else {
3584 gbcr = 0;
3585 }
3586
3587 if (autoneg == AUTONEG_DISABLE) {
3588 if (speed == SPEED_10) {
3589 bmcr = 0;
3590 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3591 speed_duplex = FORCE_10M_HALF;
3592 } else if (speed == SPEED_100) {
3593 bmcr = BMCR_SPEED100;
3594 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3595 speed_duplex = FORCE_100M_HALF;
3596 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3597 bmcr = BMCR_SPEED1000;
3598 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3599 speed_duplex = NWAY_1000M_FULL;
3600 } else {
3601 ret = -EINVAL;
3602 goto out;
3603 }
3604
3605 if (duplex == DUPLEX_FULL) {
3606 bmcr |= BMCR_FULLDPLX;
3607 if (speed != SPEED_1000)
3608 speed_duplex++;
3609 }
3610 } else {
3611 if (speed == SPEED_10) {
3612 if (duplex == DUPLEX_FULL) {
3613 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3614 speed_duplex = NWAY_10M_FULL;
3615 } else {
3616 anar |= ADVERTISE_10HALF;
3617 speed_duplex = NWAY_10M_HALF;
3618 }
3619 } else if (speed == SPEED_100) {
3620 if (duplex == DUPLEX_FULL) {
3621 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3622 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3623 speed_duplex = NWAY_100M_FULL;
3624 } else {
3625 anar |= ADVERTISE_10HALF;
3626 anar |= ADVERTISE_100HALF;
3627 speed_duplex = NWAY_100M_HALF;
3628 }
3629 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3630 if (duplex == DUPLEX_FULL) {
3631 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3632 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3633 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3634 } else {
3635 anar |= ADVERTISE_10HALF;
3636 anar |= ADVERTISE_100HALF;
3637 gbcr |= ADVERTISE_1000HALF;
3638 }
3639 speed_duplex = NWAY_1000M_FULL;
3640 } else {
3641 ret = -EINVAL;
3642 goto out;
3643 }
3644
3645 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
3646 }
3647
3648 if (test_and_clear_bit(PHY_RESET, &tp->flags))
3649 bmcr |= BMCR_RESET;
3650
3651 if (tp->mii.supports_gmii)
3652 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
3653
3654 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3655 r8152_mdio_write(tp, MII_BMCR, bmcr);
3656
3657 switch (tp->version) {
3658 case RTL_VER_08:
3659 case RTL_VER_09:
3660 r8153b_ups_flags_w1w0(tp, ups_flags_speed(speed_duplex),
3661 UPS_FLAGS_SPEED_MASK);
3662 break;
3663
3664 default:
3665 break;
3666 }
3667
3668 if (bmcr & BMCR_RESET) {
3669 int i;
3670
3671 for (i = 0; i < 50; i++) {
3672 msleep(20);
3673 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
3674 break;
3675 }
3676 }
3677
3678 out:
3679 return ret;
3680 }
3681
3682 static void rtl8152_up(struct r8152 *tp)
3683 {
3684 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3685 return;
3686
3687 r8152_aldps_en(tp, false);
3688 r8152b_exit_oob(tp);
3689 r8152_aldps_en(tp, true);
3690 }
3691
3692 static void rtl8152_down(struct r8152 *tp)
3693 {
3694 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3695 rtl_drop_queued_tx(tp);
3696 return;
3697 }
3698
3699 r8152_power_cut_en(tp, false);
3700 r8152_aldps_en(tp, false);
3701 r8152b_enter_oob(tp);
3702 r8152_aldps_en(tp, true);
3703 }
3704
3705 static void rtl8153_up(struct r8152 *tp)
3706 {
3707 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3708 return;
3709
3710 r8153_u1u2en(tp, false);
3711 r8153_u2p3en(tp, false);
3712 r8153_aldps_en(tp, false);
3713 r8153_first_init(tp);
3714 r8153_aldps_en(tp, true);
3715
3716 switch (tp->version) {
3717 case RTL_VER_03:
3718 case RTL_VER_04:
3719 break;
3720 case RTL_VER_05:
3721 case RTL_VER_06:
3722 default:
3723 r8153_u2p3en(tp, true);
3724 break;
3725 }
3726
3727 r8153_u1u2en(tp, true);
3728 }
3729
3730 static void rtl8153_down(struct r8152 *tp)
3731 {
3732 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3733 rtl_drop_queued_tx(tp);
3734 return;
3735 }
3736
3737 r8153_u1u2en(tp, false);
3738 r8153_u2p3en(tp, false);
3739 r8153_power_cut_en(tp, false);
3740 r8153_aldps_en(tp, false);
3741 r8153_enter_oob(tp);
3742 r8153_aldps_en(tp, true);
3743 }
3744
3745 static void rtl8153b_up(struct r8152 *tp)
3746 {
3747 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3748 return;
3749
3750 r8153b_u1u2en(tp, false);
3751 r8153_u2p3en(tp, false);
3752 r8153b_aldps_en(tp, false);
3753
3754 r8153_first_init(tp);
3755 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
3756
3757 r8153b_aldps_en(tp, true);
3758 r8153_u2p3en(tp, true);
3759 r8153b_u1u2en(tp, true);
3760 }
3761
3762 static void rtl8153b_down(struct r8152 *tp)
3763 {
3764 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3765 rtl_drop_queued_tx(tp);
3766 return;
3767 }
3768
3769 r8153b_u1u2en(tp, false);
3770 r8153_u2p3en(tp, false);
3771 r8153b_power_cut_en(tp, false);
3772 r8153b_aldps_en(tp, false);
3773 r8153_enter_oob(tp);
3774 r8153b_aldps_en(tp, true);
3775 }
3776
3777 static bool rtl8152_in_nway(struct r8152 *tp)
3778 {
3779 u16 nway_state;
3780
3781 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
3782 tp->ocp_base = 0x2000;
3783 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
3784 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
3785
3786 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
3787 if (nway_state & 0xc000)
3788 return false;
3789 else
3790 return true;
3791 }
3792
3793 static bool rtl8153_in_nway(struct r8152 *tp)
3794 {
3795 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
3796
3797 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
3798 return false;
3799 else
3800 return true;
3801 }
3802
3803 static void set_carrier(struct r8152 *tp)
3804 {
3805 struct net_device *netdev = tp->netdev;
3806 struct napi_struct *napi = &tp->napi;
3807 u8 speed;
3808
3809 speed = rtl8152_get_speed(tp);
3810
3811 if (speed & LINK_STATUS) {
3812 if (!netif_carrier_ok(netdev)) {
3813 tp->rtl_ops.enable(tp);
3814 netif_stop_queue(netdev);
3815 napi_disable(napi);
3816 netif_carrier_on(netdev);
3817 rtl_start_rx(tp);
3818 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
3819 _rtl8152_set_rx_mode(netdev);
3820 napi_enable(&tp->napi);
3821 netif_wake_queue(netdev);
3822 netif_info(tp, link, netdev, "carrier on\n");
3823 } else if (netif_queue_stopped(netdev) &&
3824 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
3825 netif_wake_queue(netdev);
3826 }
3827 } else {
3828 if (netif_carrier_ok(netdev)) {
3829 netif_carrier_off(netdev);
3830 napi_disable(napi);
3831 tp->rtl_ops.disable(tp);
3832 napi_enable(napi);
3833 netif_info(tp, link, netdev, "carrier off\n");
3834 }
3835 }
3836 }
3837
3838 static void rtl_work_func_t(struct work_struct *work)
3839 {
3840 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
3841
3842 /* If the device is unplugged or !netif_running(), the workqueue
3843 * doesn't need to wake the device, and could return directly.
3844 */
3845 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
3846 return;
3847
3848 if (usb_autopm_get_interface(tp->intf) < 0)
3849 return;
3850
3851 if (!test_bit(WORK_ENABLE, &tp->flags))
3852 goto out1;
3853
3854 if (!mutex_trylock(&tp->control)) {
3855 schedule_delayed_work(&tp->schedule, 0);
3856 goto out1;
3857 }
3858
3859 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
3860 set_carrier(tp);
3861
3862 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
3863 _rtl8152_set_rx_mode(tp->netdev);
3864
3865 /* don't schedule napi before linking */
3866 if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) &&
3867 netif_carrier_ok(tp->netdev))
3868 napi_schedule(&tp->napi);
3869
3870 mutex_unlock(&tp->control);
3871
3872 out1:
3873 usb_autopm_put_interface(tp->intf);
3874 }
3875
3876 static void rtl_hw_phy_work_func_t(struct work_struct *work)
3877 {
3878 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
3879
3880 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3881 return;
3882
3883 if (usb_autopm_get_interface(tp->intf) < 0)
3884 return;
3885
3886 mutex_lock(&tp->control);
3887
3888 tp->rtl_ops.hw_phy_cfg(tp);
3889
3890 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex);
3891
3892 mutex_unlock(&tp->control);
3893
3894 usb_autopm_put_interface(tp->intf);
3895 }
3896
3897 #ifdef CONFIG_PM_SLEEP
3898 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
3899 void *data)
3900 {
3901 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
3902
3903 switch (action) {
3904 case PM_HIBERNATION_PREPARE:
3905 case PM_SUSPEND_PREPARE:
3906 usb_autopm_get_interface(tp->intf);
3907 break;
3908
3909 case PM_POST_HIBERNATION:
3910 case PM_POST_SUSPEND:
3911 usb_autopm_put_interface(tp->intf);
3912 break;
3913
3914 case PM_POST_RESTORE:
3915 case PM_RESTORE_PREPARE:
3916 default:
3917 break;
3918 }
3919
3920 return NOTIFY_DONE;
3921 }
3922 #endif
3923
3924 static int rtl8152_open(struct net_device *netdev)
3925 {
3926 struct r8152 *tp = netdev_priv(netdev);
3927 int res = 0;
3928
3929 res = alloc_all_mem(tp);
3930 if (res)
3931 goto out;
3932
3933 res = usb_autopm_get_interface(tp->intf);
3934 if (res < 0)
3935 goto out_free;
3936
3937 mutex_lock(&tp->control);
3938
3939 tp->rtl_ops.up(tp);
3940
3941 netif_carrier_off(netdev);
3942 netif_start_queue(netdev);
3943 set_bit(WORK_ENABLE, &tp->flags);
3944
3945 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3946 if (res) {
3947 if (res == -ENODEV)
3948 netif_device_detach(tp->netdev);
3949 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
3950 res);
3951 goto out_unlock;
3952 }
3953 napi_enable(&tp->napi);
3954
3955 mutex_unlock(&tp->control);
3956
3957 usb_autopm_put_interface(tp->intf);
3958 #ifdef CONFIG_PM_SLEEP
3959 tp->pm_notifier.notifier_call = rtl_notifier;
3960 register_pm_notifier(&tp->pm_notifier);
3961 #endif
3962 return 0;
3963
3964 out_unlock:
3965 mutex_unlock(&tp->control);
3966 usb_autopm_put_interface(tp->intf);
3967 out_free:
3968 free_all_mem(tp);
3969 out:
3970 return res;
3971 }
3972
3973 static int rtl8152_close(struct net_device *netdev)
3974 {
3975 struct r8152 *tp = netdev_priv(netdev);
3976 int res = 0;
3977
3978 #ifdef CONFIG_PM_SLEEP
3979 unregister_pm_notifier(&tp->pm_notifier);
3980 #endif
3981 if (!test_bit(RTL8152_UNPLUG, &tp->flags))
3982 napi_disable(&tp->napi);
3983 clear_bit(WORK_ENABLE, &tp->flags);
3984 usb_kill_urb(tp->intr_urb);
3985 cancel_delayed_work_sync(&tp->schedule);
3986 netif_stop_queue(netdev);
3987
3988 res = usb_autopm_get_interface(tp->intf);
3989 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
3990 rtl_drop_queued_tx(tp);
3991 rtl_stop_rx(tp);
3992 } else {
3993 mutex_lock(&tp->control);
3994
3995 tp->rtl_ops.down(tp);
3996
3997 mutex_unlock(&tp->control);
3998
3999 usb_autopm_put_interface(tp->intf);
4000 }
4001
4002 free_all_mem(tp);
4003
4004 return res;
4005 }
4006
4007 static void rtl_tally_reset(struct r8152 *tp)
4008 {
4009 u32 ocp_data;
4010
4011 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
4012 ocp_data |= TALLY_RESET;
4013 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
4014 }
4015
4016 static void r8152b_init(struct r8152 *tp)
4017 {
4018 u32 ocp_data;
4019 u16 data;
4020
4021 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4022 return;
4023
4024 data = r8152_mdio_read(tp, MII_BMCR);
4025 if (data & BMCR_PDOWN) {
4026 data &= ~BMCR_PDOWN;
4027 r8152_mdio_write(tp, MII_BMCR, data);
4028 }
4029
4030 r8152_aldps_en(tp, false);
4031
4032 if (tp->version == RTL_VER_01) {
4033 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
4034 ocp_data &= ~LED_MODE_MASK;
4035 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
4036 }
4037
4038 r8152_power_cut_en(tp, false);
4039
4040 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4041 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
4042 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4043 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
4044 ocp_data &= ~MCU_CLK_RATIO_MASK;
4045 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
4046 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
4047 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
4048 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
4049 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
4050
4051 rtl_tally_reset(tp);
4052
4053 /* enable rx aggregation */
4054 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4055 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4056 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4057 }
4058
4059 static void r8153_init(struct r8152 *tp)
4060 {
4061 u32 ocp_data;
4062 u16 data;
4063 int i;
4064
4065 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4066 return;
4067
4068 r8153_u1u2en(tp, false);
4069
4070 for (i = 0; i < 500; i++) {
4071 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
4072 AUTOLOAD_DONE)
4073 break;
4074 msleep(20);
4075 }
4076
4077 data = r8153_phy_status(tp, 0);
4078
4079 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
4080 tp->version == RTL_VER_05)
4081 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
4082
4083 data = r8152_mdio_read(tp, MII_BMCR);
4084 if (data & BMCR_PDOWN) {
4085 data &= ~BMCR_PDOWN;
4086 r8152_mdio_write(tp, MII_BMCR, data);
4087 }
4088
4089 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
4090
4091 r8153_u2p3en(tp, false);
4092
4093 if (tp->version == RTL_VER_04) {
4094 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
4095 ocp_data &= ~pwd_dn_scale_mask;
4096 ocp_data |= pwd_dn_scale(96);
4097 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
4098
4099 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4100 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4101 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4102 } else if (tp->version == RTL_VER_05) {
4103 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
4104 ocp_data &= ~ECM_ALDPS;
4105 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
4106
4107 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
4108 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
4109 ocp_data &= ~DYNAMIC_BURST;
4110 else
4111 ocp_data |= DYNAMIC_BURST;
4112 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
4113 } else if (tp->version == RTL_VER_06) {
4114 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
4115 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
4116 ocp_data &= ~DYNAMIC_BURST;
4117 else
4118 ocp_data |= DYNAMIC_BURST;
4119 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
4120 }
4121
4122 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
4123 ocp_data |= EP4_FULL_FC;
4124 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
4125
4126 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
4127 ocp_data &= ~TIMER11_EN;
4128 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
4129
4130 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
4131 ocp_data &= ~LED_MODE_MASK;
4132 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
4133
4134 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
4135 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
4136 ocp_data |= LPM_TIMER_500MS;
4137 else
4138 ocp_data |= LPM_TIMER_500US;
4139 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
4140
4141 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
4142 ocp_data &= ~SEN_VAL_MASK;
4143 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
4144 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
4145
4146 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
4147
4148 r8153_power_cut_en(tp, false);
4149 r8153_u1u2en(tp, true);
4150 r8153_mac_clk_spd(tp, false);
4151 usb_enable_lpm(tp->udev);
4152
4153 /* rx aggregation */
4154 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4155 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4156 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
4157 ocp_data |= RX_AGG_DISABLE;
4158
4159 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4160
4161 rtl_tally_reset(tp);
4162
4163 switch (tp->udev->speed) {
4164 case USB_SPEED_SUPER:
4165 case USB_SPEED_SUPER_PLUS:
4166 tp->coalesce = COALESCE_SUPER;
4167 break;
4168 case USB_SPEED_HIGH:
4169 tp->coalesce = COALESCE_HIGH;
4170 break;
4171 default:
4172 tp->coalesce = COALESCE_SLOW;
4173 break;
4174 }
4175 }
4176
4177 static void r8153b_init(struct r8152 *tp)
4178 {
4179 u32 ocp_data;
4180 u16 data;
4181 int i;
4182
4183 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4184 return;
4185
4186 r8153b_u1u2en(tp, false);
4187
4188 for (i = 0; i < 500; i++) {
4189 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
4190 AUTOLOAD_DONE)
4191 break;
4192 msleep(20);
4193 }
4194
4195 data = r8153_phy_status(tp, 0);
4196
4197 data = r8152_mdio_read(tp, MII_BMCR);
4198 if (data & BMCR_PDOWN) {
4199 data &= ~BMCR_PDOWN;
4200 r8152_mdio_write(tp, MII_BMCR, data);
4201 }
4202
4203 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
4204
4205 r8153_u2p3en(tp, false);
4206
4207 /* MSC timer = 0xfff * 8ms = 32760 ms */
4208 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
4209
4210 /* U1/U2/L1 idle timer. 500 us */
4211 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
4212
4213 r8153b_power_cut_en(tp, false);
4214 r8153b_ups_en(tp, false);
4215 r8153b_queue_wake(tp, false);
4216 rtl_runtime_suspend_enable(tp, false);
4217 r8153b_u1u2en(tp, true);
4218 usb_enable_lpm(tp->udev);
4219
4220 /* MAC clock speed down */
4221 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
4222 ocp_data |= MAC_CLK_SPDWN_EN;
4223 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
4224
4225 set_bit(GREEN_ETHERNET, &tp->flags);
4226
4227 /* rx aggregation */
4228 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4229 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4230 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4231
4232 rtl_tally_reset(tp);
4233
4234 tp->coalesce = 15000; /* 15 us */
4235 }
4236
4237 static int rtl8152_pre_reset(struct usb_interface *intf)
4238 {
4239 struct r8152 *tp = usb_get_intfdata(intf);
4240 struct net_device *netdev;
4241
4242 if (!tp)
4243 return 0;
4244
4245 netdev = tp->netdev;
4246 if (!netif_running(netdev))
4247 return 0;
4248
4249 netif_stop_queue(netdev);
4250 napi_disable(&tp->napi);
4251 clear_bit(WORK_ENABLE, &tp->flags);
4252 usb_kill_urb(tp->intr_urb);
4253 cancel_delayed_work_sync(&tp->schedule);
4254 if (netif_carrier_ok(netdev)) {
4255 mutex_lock(&tp->control);
4256 tp->rtl_ops.disable(tp);
4257 mutex_unlock(&tp->control);
4258 }
4259
4260 return 0;
4261 }
4262
4263 static int rtl8152_post_reset(struct usb_interface *intf)
4264 {
4265 struct r8152 *tp = usb_get_intfdata(intf);
4266 struct net_device *netdev;
4267
4268 if (!tp)
4269 return 0;
4270
4271 netdev = tp->netdev;
4272 if (!netif_running(netdev))
4273 return 0;
4274
4275 set_bit(WORK_ENABLE, &tp->flags);
4276 if (netif_carrier_ok(netdev)) {
4277 mutex_lock(&tp->control);
4278 tp->rtl_ops.enable(tp);
4279 rtl_start_rx(tp);
4280 _rtl8152_set_rx_mode(netdev);
4281 mutex_unlock(&tp->control);
4282 }
4283
4284 napi_enable(&tp->napi);
4285 netif_wake_queue(netdev);
4286 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
4287
4288 if (!list_empty(&tp->rx_done))
4289 napi_schedule(&tp->napi);
4290
4291 return 0;
4292 }
4293
4294 static bool delay_autosuspend(struct r8152 *tp)
4295 {
4296 bool sw_linking = !!netif_carrier_ok(tp->netdev);
4297 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
4298
4299 /* This means a linking change occurs and the driver doesn't detect it,
4300 * yet. If the driver has disabled tx/rx and hw is linking on, the
4301 * device wouldn't wake up by receiving any packet.
4302 */
4303 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
4304 return true;
4305
4306 /* If the linking down is occurred by nway, the device may miss the
4307 * linking change event. And it wouldn't wake when linking on.
4308 */
4309 if (!sw_linking && tp->rtl_ops.in_nway(tp))
4310 return true;
4311 else if (!skb_queue_empty(&tp->tx_queue))
4312 return true;
4313 else
4314 return false;
4315 }
4316
4317 static int rtl8152_runtime_resume(struct r8152 *tp)
4318 {
4319 struct net_device *netdev = tp->netdev;
4320
4321 if (netif_running(netdev) && netdev->flags & IFF_UP) {
4322 struct napi_struct *napi = &tp->napi;
4323
4324 tp->rtl_ops.autosuspend_en(tp, false);
4325 napi_disable(napi);
4326 set_bit(WORK_ENABLE, &tp->flags);
4327
4328 if (netif_carrier_ok(netdev)) {
4329 if (rtl8152_get_speed(tp) & LINK_STATUS) {
4330 rtl_start_rx(tp);
4331 } else {
4332 netif_carrier_off(netdev);
4333 tp->rtl_ops.disable(tp);
4334 netif_info(tp, link, netdev, "linking down\n");
4335 }
4336 }
4337
4338 napi_enable(napi);
4339 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4340 smp_mb__after_atomic();
4341
4342 if (!list_empty(&tp->rx_done))
4343 napi_schedule(&tp->napi);
4344
4345 usb_submit_urb(tp->intr_urb, GFP_NOIO);
4346 } else {
4347 if (netdev->flags & IFF_UP)
4348 tp->rtl_ops.autosuspend_en(tp, false);
4349
4350 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4351 }
4352
4353 return 0;
4354 }
4355
4356 static int rtl8152_system_resume(struct r8152 *tp)
4357 {
4358 struct net_device *netdev = tp->netdev;
4359
4360 netif_device_attach(netdev);
4361
4362 if (netif_running(netdev) && netdev->flags & IFF_UP) {
4363 tp->rtl_ops.up(tp);
4364 netif_carrier_off(netdev);
4365 set_bit(WORK_ENABLE, &tp->flags);
4366 usb_submit_urb(tp->intr_urb, GFP_NOIO);
4367 }
4368
4369 return 0;
4370 }
4371
4372 static int rtl8152_runtime_suspend(struct r8152 *tp)
4373 {
4374 struct net_device *netdev = tp->netdev;
4375 int ret = 0;
4376
4377 set_bit(SELECTIVE_SUSPEND, &tp->flags);
4378 smp_mb__after_atomic();
4379
4380 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
4381 u32 rcr = 0;
4382
4383 if (netif_carrier_ok(netdev)) {
4384 u32 ocp_data;
4385
4386 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4387 ocp_data = rcr & ~RCR_ACPT_ALL;
4388 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4389 rxdy_gated_en(tp, true);
4390 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
4391 PLA_OOB_CTRL);
4392 if (!(ocp_data & RXFIFO_EMPTY)) {
4393 rxdy_gated_en(tp, false);
4394 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
4395 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4396 smp_mb__after_atomic();
4397 ret = -EBUSY;
4398 goto out1;
4399 }
4400 }
4401
4402 clear_bit(WORK_ENABLE, &tp->flags);
4403 usb_kill_urb(tp->intr_urb);
4404
4405 tp->rtl_ops.autosuspend_en(tp, true);
4406
4407 if (netif_carrier_ok(netdev)) {
4408 struct napi_struct *napi = &tp->napi;
4409
4410 napi_disable(napi);
4411 rtl_stop_rx(tp);
4412 rxdy_gated_en(tp, false);
4413 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
4414 napi_enable(napi);
4415 }
4416
4417 if (delay_autosuspend(tp)) {
4418 rtl8152_runtime_resume(tp);
4419 ret = -EBUSY;
4420 }
4421 }
4422
4423 out1:
4424 return ret;
4425 }
4426
4427 static int rtl8152_system_suspend(struct r8152 *tp)
4428 {
4429 struct net_device *netdev = tp->netdev;
4430
4431 netif_device_detach(netdev);
4432
4433 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
4434 struct napi_struct *napi = &tp->napi;
4435
4436 clear_bit(WORK_ENABLE, &tp->flags);
4437 usb_kill_urb(tp->intr_urb);
4438 napi_disable(napi);
4439 cancel_delayed_work_sync(&tp->schedule);
4440 tp->rtl_ops.down(tp);
4441 napi_enable(napi);
4442 }
4443
4444 return 0;
4445 }
4446
4447 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
4448 {
4449 struct r8152 *tp = usb_get_intfdata(intf);
4450 int ret;
4451
4452 mutex_lock(&tp->control);
4453
4454 if (PMSG_IS_AUTO(message))
4455 ret = rtl8152_runtime_suspend(tp);
4456 else
4457 ret = rtl8152_system_suspend(tp);
4458
4459 mutex_unlock(&tp->control);
4460
4461 return ret;
4462 }
4463
4464 static int rtl8152_resume(struct usb_interface *intf)
4465 {
4466 struct r8152 *tp = usb_get_intfdata(intf);
4467 int ret;
4468
4469 mutex_lock(&tp->control);
4470
4471 if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
4472 ret = rtl8152_runtime_resume(tp);
4473 else
4474 ret = rtl8152_system_resume(tp);
4475
4476 mutex_unlock(&tp->control);
4477
4478 return ret;
4479 }
4480
4481 static int rtl8152_reset_resume(struct usb_interface *intf)
4482 {
4483 struct r8152 *tp = usb_get_intfdata(intf);
4484
4485 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4486 mutex_lock(&tp->control);
4487 tp->rtl_ops.init(tp);
4488 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
4489 mutex_unlock(&tp->control);
4490 return rtl8152_resume(intf);
4491 }
4492
4493 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4494 {
4495 struct r8152 *tp = netdev_priv(dev);
4496
4497 if (usb_autopm_get_interface(tp->intf) < 0)
4498 return;
4499
4500 if (!rtl_can_wakeup(tp)) {
4501 wol->supported = 0;
4502 wol->wolopts = 0;
4503 } else {
4504 mutex_lock(&tp->control);
4505 wol->supported = WAKE_ANY;
4506 wol->wolopts = __rtl_get_wol(tp);
4507 mutex_unlock(&tp->control);
4508 }
4509
4510 usb_autopm_put_interface(tp->intf);
4511 }
4512
4513 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4514 {
4515 struct r8152 *tp = netdev_priv(dev);
4516 int ret;
4517
4518 if (!rtl_can_wakeup(tp))
4519 return -EOPNOTSUPP;
4520
4521 if (wol->wolopts & ~WAKE_ANY)
4522 return -EINVAL;
4523
4524 ret = usb_autopm_get_interface(tp->intf);
4525 if (ret < 0)
4526 goto out_set_wol;
4527
4528 mutex_lock(&tp->control);
4529
4530 __rtl_set_wol(tp, wol->wolopts);
4531 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
4532
4533 mutex_unlock(&tp->control);
4534
4535 usb_autopm_put_interface(tp->intf);
4536
4537 out_set_wol:
4538 return ret;
4539 }
4540
4541 static u32 rtl8152_get_msglevel(struct net_device *dev)
4542 {
4543 struct r8152 *tp = netdev_priv(dev);
4544
4545 return tp->msg_enable;
4546 }
4547
4548 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
4549 {
4550 struct r8152 *tp = netdev_priv(dev);
4551
4552 tp->msg_enable = value;
4553 }
4554
4555 static void rtl8152_get_drvinfo(struct net_device *netdev,
4556 struct ethtool_drvinfo *info)
4557 {
4558 struct r8152 *tp = netdev_priv(netdev);
4559
4560 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
4561 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
4562 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
4563 }
4564
4565 static
4566 int rtl8152_get_link_ksettings(struct net_device *netdev,
4567 struct ethtool_link_ksettings *cmd)
4568 {
4569 struct r8152 *tp = netdev_priv(netdev);
4570 int ret;
4571
4572 if (!tp->mii.mdio_read)
4573 return -EOPNOTSUPP;
4574
4575 ret = usb_autopm_get_interface(tp->intf);
4576 if (ret < 0)
4577 goto out;
4578
4579 mutex_lock(&tp->control);
4580
4581 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
4582
4583 mutex_unlock(&tp->control);
4584
4585 usb_autopm_put_interface(tp->intf);
4586
4587 out:
4588 return ret;
4589 }
4590
4591 static int rtl8152_set_link_ksettings(struct net_device *dev,
4592 const struct ethtool_link_ksettings *cmd)
4593 {
4594 struct r8152 *tp = netdev_priv(dev);
4595 int ret;
4596
4597 ret = usb_autopm_get_interface(tp->intf);
4598 if (ret < 0)
4599 goto out;
4600
4601 mutex_lock(&tp->control);
4602
4603 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
4604 cmd->base.duplex);
4605 if (!ret) {
4606 tp->autoneg = cmd->base.autoneg;
4607 tp->speed = cmd->base.speed;
4608 tp->duplex = cmd->base.duplex;
4609 }
4610
4611 mutex_unlock(&tp->control);
4612
4613 usb_autopm_put_interface(tp->intf);
4614
4615 out:
4616 return ret;
4617 }
4618
4619 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
4620 "tx_packets",
4621 "rx_packets",
4622 "tx_errors",
4623 "rx_errors",
4624 "rx_missed",
4625 "align_errors",
4626 "tx_single_collisions",
4627 "tx_multi_collisions",
4628 "rx_unicast",
4629 "rx_broadcast",
4630 "rx_multicast",
4631 "tx_aborted",
4632 "tx_underrun",
4633 };
4634
4635 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
4636 {
4637 switch (sset) {
4638 case ETH_SS_STATS:
4639 return ARRAY_SIZE(rtl8152_gstrings);
4640 default:
4641 return -EOPNOTSUPP;
4642 }
4643 }
4644
4645 static void rtl8152_get_ethtool_stats(struct net_device *dev,
4646 struct ethtool_stats *stats, u64 *data)
4647 {
4648 struct r8152 *tp = netdev_priv(dev);
4649 struct tally_counter tally;
4650
4651 if (usb_autopm_get_interface(tp->intf) < 0)
4652 return;
4653
4654 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
4655
4656 usb_autopm_put_interface(tp->intf);
4657
4658 data[0] = le64_to_cpu(tally.tx_packets);
4659 data[1] = le64_to_cpu(tally.rx_packets);
4660 data[2] = le64_to_cpu(tally.tx_errors);
4661 data[3] = le32_to_cpu(tally.rx_errors);
4662 data[4] = le16_to_cpu(tally.rx_missed);
4663 data[5] = le16_to_cpu(tally.align_errors);
4664 data[6] = le32_to_cpu(tally.tx_one_collision);
4665 data[7] = le32_to_cpu(tally.tx_multi_collision);
4666 data[8] = le64_to_cpu(tally.rx_unicast);
4667 data[9] = le64_to_cpu(tally.rx_broadcast);
4668 data[10] = le32_to_cpu(tally.rx_multicast);
4669 data[11] = le16_to_cpu(tally.tx_aborted);
4670 data[12] = le16_to_cpu(tally.tx_underrun);
4671 }
4672
4673 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4674 {
4675 switch (stringset) {
4676 case ETH_SS_STATS:
4677 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
4678 break;
4679 }
4680 }
4681
4682 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
4683 {
4684 u32 ocp_data, lp, adv, supported = 0;
4685 u16 val;
4686
4687 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
4688 supported = mmd_eee_cap_to_ethtool_sup_t(val);
4689
4690 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
4691 adv = mmd_eee_adv_to_ethtool_adv_t(val);
4692
4693 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
4694 lp = mmd_eee_adv_to_ethtool_adv_t(val);
4695
4696 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4697 ocp_data &= EEE_RX_EN | EEE_TX_EN;
4698
4699 eee->eee_enabled = !!ocp_data;
4700 eee->eee_active = !!(supported & adv & lp);
4701 eee->supported = supported;
4702 eee->advertised = adv;
4703 eee->lp_advertised = lp;
4704
4705 return 0;
4706 }
4707
4708 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4709 {
4710 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4711
4712 r8152_eee_en(tp, eee->eee_enabled);
4713
4714 if (!eee->eee_enabled)
4715 val = 0;
4716
4717 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4718
4719 return 0;
4720 }
4721
4722 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
4723 {
4724 u32 ocp_data, lp, adv, supported = 0;
4725 u16 val;
4726
4727 val = ocp_reg_read(tp, OCP_EEE_ABLE);
4728 supported = mmd_eee_cap_to_ethtool_sup_t(val);
4729
4730 val = ocp_reg_read(tp, OCP_EEE_ADV);
4731 adv = mmd_eee_adv_to_ethtool_adv_t(val);
4732
4733 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
4734 lp = mmd_eee_adv_to_ethtool_adv_t(val);
4735
4736 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4737 ocp_data &= EEE_RX_EN | EEE_TX_EN;
4738
4739 eee->eee_enabled = !!ocp_data;
4740 eee->eee_active = !!(supported & adv & lp);
4741 eee->supported = supported;
4742 eee->advertised = adv;
4743 eee->lp_advertised = lp;
4744
4745 return 0;
4746 }
4747
4748 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4749 {
4750 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4751
4752 r8153_eee_en(tp, eee->eee_enabled);
4753
4754 if (!eee->eee_enabled)
4755 val = 0;
4756
4757 ocp_reg_write(tp, OCP_EEE_ADV, val);
4758
4759 return 0;
4760 }
4761
4762 static int r8153b_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4763 {
4764 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4765
4766 r8153b_eee_en(tp, eee->eee_enabled);
4767
4768 if (!eee->eee_enabled)
4769 val = 0;
4770
4771 ocp_reg_write(tp, OCP_EEE_ADV, val);
4772
4773 return 0;
4774 }
4775
4776 static int
4777 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
4778 {
4779 struct r8152 *tp = netdev_priv(net);
4780 int ret;
4781
4782 ret = usb_autopm_get_interface(tp->intf);
4783 if (ret < 0)
4784 goto out;
4785
4786 mutex_lock(&tp->control);
4787
4788 ret = tp->rtl_ops.eee_get(tp, edata);
4789
4790 mutex_unlock(&tp->control);
4791
4792 usb_autopm_put_interface(tp->intf);
4793
4794 out:
4795 return ret;
4796 }
4797
4798 static int
4799 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
4800 {
4801 struct r8152 *tp = netdev_priv(net);
4802 int ret;
4803
4804 ret = usb_autopm_get_interface(tp->intf);
4805 if (ret < 0)
4806 goto out;
4807
4808 mutex_lock(&tp->control);
4809
4810 ret = tp->rtl_ops.eee_set(tp, edata);
4811 if (!ret)
4812 ret = mii_nway_restart(&tp->mii);
4813
4814 mutex_unlock(&tp->control);
4815
4816 usb_autopm_put_interface(tp->intf);
4817
4818 out:
4819 return ret;
4820 }
4821
4822 static int rtl8152_nway_reset(struct net_device *dev)
4823 {
4824 struct r8152 *tp = netdev_priv(dev);
4825 int ret;
4826
4827 ret = usb_autopm_get_interface(tp->intf);
4828 if (ret < 0)
4829 goto out;
4830
4831 mutex_lock(&tp->control);
4832
4833 ret = mii_nway_restart(&tp->mii);
4834
4835 mutex_unlock(&tp->control);
4836
4837 usb_autopm_put_interface(tp->intf);
4838
4839 out:
4840 return ret;
4841 }
4842
4843 static int rtl8152_get_coalesce(struct net_device *netdev,
4844 struct ethtool_coalesce *coalesce)
4845 {
4846 struct r8152 *tp = netdev_priv(netdev);
4847
4848 switch (tp->version) {
4849 case RTL_VER_01:
4850 case RTL_VER_02:
4851 case RTL_VER_07:
4852 return -EOPNOTSUPP;
4853 default:
4854 break;
4855 }
4856
4857 coalesce->rx_coalesce_usecs = tp->coalesce;
4858
4859 return 0;
4860 }
4861
4862 static int rtl8152_set_coalesce(struct net_device *netdev,
4863 struct ethtool_coalesce *coalesce)
4864 {
4865 struct r8152 *tp = netdev_priv(netdev);
4866 int ret;
4867
4868 switch (tp->version) {
4869 case RTL_VER_01:
4870 case RTL_VER_02:
4871 case RTL_VER_07:
4872 return -EOPNOTSUPP;
4873 default:
4874 break;
4875 }
4876
4877 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
4878 return -EINVAL;
4879
4880 ret = usb_autopm_get_interface(tp->intf);
4881 if (ret < 0)
4882 return ret;
4883
4884 mutex_lock(&tp->control);
4885
4886 if (tp->coalesce != coalesce->rx_coalesce_usecs) {
4887 tp->coalesce = coalesce->rx_coalesce_usecs;
4888
4889 if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
4890 r8153_set_rx_early_timeout(tp);
4891 }
4892
4893 mutex_unlock(&tp->control);
4894
4895 usb_autopm_put_interface(tp->intf);
4896
4897 return ret;
4898 }
4899
4900 static const struct ethtool_ops ops = {
4901 .get_drvinfo = rtl8152_get_drvinfo,
4902 .get_link = ethtool_op_get_link,
4903 .nway_reset = rtl8152_nway_reset,
4904 .get_msglevel = rtl8152_get_msglevel,
4905 .set_msglevel = rtl8152_set_msglevel,
4906 .get_wol = rtl8152_get_wol,
4907 .set_wol = rtl8152_set_wol,
4908 .get_strings = rtl8152_get_strings,
4909 .get_sset_count = rtl8152_get_sset_count,
4910 .get_ethtool_stats = rtl8152_get_ethtool_stats,
4911 .get_coalesce = rtl8152_get_coalesce,
4912 .set_coalesce = rtl8152_set_coalesce,
4913 .get_eee = rtl_ethtool_get_eee,
4914 .set_eee = rtl_ethtool_set_eee,
4915 .get_link_ksettings = rtl8152_get_link_ksettings,
4916 .set_link_ksettings = rtl8152_set_link_ksettings,
4917 };
4918
4919 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
4920 {
4921 struct r8152 *tp = netdev_priv(netdev);
4922 struct mii_ioctl_data *data = if_mii(rq);
4923 int res;
4924
4925 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4926 return -ENODEV;
4927
4928 res = usb_autopm_get_interface(tp->intf);
4929 if (res < 0)
4930 goto out;
4931
4932 switch (cmd) {
4933 case SIOCGMIIPHY:
4934 data->phy_id = R8152_PHY_ID; /* Internal PHY */
4935 break;
4936
4937 case SIOCGMIIREG:
4938 mutex_lock(&tp->control);
4939 data->val_out = r8152_mdio_read(tp, data->reg_num);
4940 mutex_unlock(&tp->control);
4941 break;
4942
4943 case SIOCSMIIREG:
4944 if (!capable(CAP_NET_ADMIN)) {
4945 res = -EPERM;
4946 break;
4947 }
4948 mutex_lock(&tp->control);
4949 r8152_mdio_write(tp, data->reg_num, data->val_in);
4950 mutex_unlock(&tp->control);
4951 break;
4952
4953 default:
4954 res = -EOPNOTSUPP;
4955 }
4956
4957 usb_autopm_put_interface(tp->intf);
4958
4959 out:
4960 return res;
4961 }
4962
4963 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
4964 {
4965 struct r8152 *tp = netdev_priv(dev);
4966 int ret;
4967
4968 switch (tp->version) {
4969 case RTL_VER_01:
4970 case RTL_VER_02:
4971 case RTL_VER_07:
4972 dev->mtu = new_mtu;
4973 return 0;
4974 default:
4975 break;
4976 }
4977
4978 ret = usb_autopm_get_interface(tp->intf);
4979 if (ret < 0)
4980 return ret;
4981
4982 mutex_lock(&tp->control);
4983
4984 dev->mtu = new_mtu;
4985
4986 if (netif_running(dev)) {
4987 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4988
4989 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
4990
4991 if (netif_carrier_ok(dev))
4992 r8153_set_rx_early_size(tp);
4993 }
4994
4995 mutex_unlock(&tp->control);
4996
4997 usb_autopm_put_interface(tp->intf);
4998
4999 return ret;
5000 }
5001
5002 static const struct net_device_ops rtl8152_netdev_ops = {
5003 .ndo_open = rtl8152_open,
5004 .ndo_stop = rtl8152_close,
5005 .ndo_do_ioctl = rtl8152_ioctl,
5006 .ndo_start_xmit = rtl8152_start_xmit,
5007 .ndo_tx_timeout = rtl8152_tx_timeout,
5008 .ndo_set_features = rtl8152_set_features,
5009 .ndo_set_rx_mode = rtl8152_set_rx_mode,
5010 .ndo_set_mac_address = rtl8152_set_mac_address,
5011 .ndo_change_mtu = rtl8152_change_mtu,
5012 .ndo_validate_addr = eth_validate_addr,
5013 .ndo_features_check = rtl8152_features_check,
5014 };
5015
5016 static void rtl8152_unload(struct r8152 *tp)
5017 {
5018 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5019 return;
5020
5021 if (tp->version != RTL_VER_01)
5022 r8152_power_cut_en(tp, true);
5023 }
5024
5025 static void rtl8153_unload(struct r8152 *tp)
5026 {
5027 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5028 return;
5029
5030 r8153_power_cut_en(tp, false);
5031 }
5032
5033 static void rtl8153b_unload(struct r8152 *tp)
5034 {
5035 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5036 return;
5037
5038 r8153b_power_cut_en(tp, false);
5039 }
5040
5041 static int rtl_ops_init(struct r8152 *tp)
5042 {
5043 struct rtl_ops *ops = &tp->rtl_ops;
5044 int ret = 0;
5045
5046 switch (tp->version) {
5047 case RTL_VER_01:
5048 case RTL_VER_02:
5049 case RTL_VER_07:
5050 ops->init = r8152b_init;
5051 ops->enable = rtl8152_enable;
5052 ops->disable = rtl8152_disable;
5053 ops->up = rtl8152_up;
5054 ops->down = rtl8152_down;
5055 ops->unload = rtl8152_unload;
5056 ops->eee_get = r8152_get_eee;
5057 ops->eee_set = r8152_set_eee;
5058 ops->in_nway = rtl8152_in_nway;
5059 ops->hw_phy_cfg = r8152b_hw_phy_cfg;
5060 ops->autosuspend_en = rtl_runtime_suspend_enable;
5061 break;
5062
5063 case RTL_VER_03:
5064 case RTL_VER_04:
5065 case RTL_VER_05:
5066 case RTL_VER_06:
5067 ops->init = r8153_init;
5068 ops->enable = rtl8153_enable;
5069 ops->disable = rtl8153_disable;
5070 ops->up = rtl8153_up;
5071 ops->down = rtl8153_down;
5072 ops->unload = rtl8153_unload;
5073 ops->eee_get = r8153_get_eee;
5074 ops->eee_set = r8153_set_eee;
5075 ops->in_nway = rtl8153_in_nway;
5076 ops->hw_phy_cfg = r8153_hw_phy_cfg;
5077 ops->autosuspend_en = rtl8153_runtime_enable;
5078 break;
5079
5080 case RTL_VER_08:
5081 case RTL_VER_09:
5082 ops->init = r8153b_init;
5083 ops->enable = rtl8153_enable;
5084 ops->disable = rtl8153b_disable;
5085 ops->up = rtl8153b_up;
5086 ops->down = rtl8153b_down;
5087 ops->unload = rtl8153b_unload;
5088 ops->eee_get = r8153_get_eee;
5089 ops->eee_set = r8153b_set_eee;
5090 ops->in_nway = rtl8153_in_nway;
5091 ops->hw_phy_cfg = r8153b_hw_phy_cfg;
5092 ops->autosuspend_en = rtl8153b_runtime_enable;
5093 break;
5094
5095 default:
5096 ret = -ENODEV;
5097 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
5098 break;
5099 }
5100
5101 return ret;
5102 }
5103
5104 static u8 rtl_get_version(struct usb_interface *intf)
5105 {
5106 struct usb_device *udev = interface_to_usbdev(intf);
5107 u32 ocp_data = 0;
5108 __le32 *tmp;
5109 u8 version;
5110 int ret;
5111
5112 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
5113 if (!tmp)
5114 return 0;
5115
5116 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
5117 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
5118 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
5119 if (ret > 0)
5120 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
5121
5122 kfree(tmp);
5123
5124 switch (ocp_data) {
5125 case 0x4c00:
5126 version = RTL_VER_01;
5127 break;
5128 case 0x4c10:
5129 version = RTL_VER_02;
5130 break;
5131 case 0x5c00:
5132 version = RTL_VER_03;
5133 break;
5134 case 0x5c10:
5135 version = RTL_VER_04;
5136 break;
5137 case 0x5c20:
5138 version = RTL_VER_05;
5139 break;
5140 case 0x5c30:
5141 version = RTL_VER_06;
5142 break;
5143 case 0x4800:
5144 version = RTL_VER_07;
5145 break;
5146 case 0x6000:
5147 version = RTL_VER_08;
5148 break;
5149 case 0x6010:
5150 version = RTL_VER_09;
5151 break;
5152 default:
5153 version = RTL_VER_UNKNOWN;
5154 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
5155 break;
5156 }
5157
5158 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
5159
5160 return version;
5161 }
5162
5163 static int rtl8152_probe(struct usb_interface *intf,
5164 const struct usb_device_id *id)
5165 {
5166 struct usb_device *udev = interface_to_usbdev(intf);
5167 u8 version = rtl_get_version(intf);
5168 struct r8152 *tp;
5169 struct net_device *netdev;
5170 int ret;
5171
5172 if (version == RTL_VER_UNKNOWN)
5173 return -ENODEV;
5174
5175 if (udev->actconfig->desc.bConfigurationValue != 1) {
5176 usb_driver_set_configuration(udev, 1);
5177 return -ENODEV;
5178 }
5179
5180 usb_reset_device(udev);
5181 netdev = alloc_etherdev(sizeof(struct r8152));
5182 if (!netdev) {
5183 dev_err(&intf->dev, "Out of memory\n");
5184 return -ENOMEM;
5185 }
5186
5187 SET_NETDEV_DEV(netdev, &intf->dev);
5188 tp = netdev_priv(netdev);
5189 tp->msg_enable = 0x7FFF;
5190
5191 tp->udev = udev;
5192 tp->netdev = netdev;
5193 tp->intf = intf;
5194 tp->version = version;
5195
5196 switch (version) {
5197 case RTL_VER_01:
5198 case RTL_VER_02:
5199 case RTL_VER_07:
5200 tp->mii.supports_gmii = 0;
5201 break;
5202 default:
5203 tp->mii.supports_gmii = 1;
5204 break;
5205 }
5206
5207 ret = rtl_ops_init(tp);
5208 if (ret)
5209 goto out;
5210
5211 mutex_init(&tp->control);
5212 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
5213 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
5214
5215 netdev->netdev_ops = &rtl8152_netdev_ops;
5216 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5217
5218 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
5219 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
5220 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
5221 NETIF_F_HW_VLAN_CTAG_TX;
5222 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
5223 NETIF_F_TSO | NETIF_F_FRAGLIST |
5224 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
5225 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
5226 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
5227 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
5228 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
5229
5230 if (tp->version == RTL_VER_01) {
5231 netdev->features &= ~NETIF_F_RXCSUM;
5232 netdev->hw_features &= ~NETIF_F_RXCSUM;
5233 }
5234
5235 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
5236 (!strcmp(udev->serial, "000001000000") || !strcmp(udev->serial, "000002000000"))) {
5237 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
5238 set_bit(DELL_TB_RX_AGG_BUG, &tp->flags);
5239 }
5240
5241 netdev->ethtool_ops = &ops;
5242 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
5243
5244 /* MTU range: 68 - 1500 or 9194 */
5245 netdev->min_mtu = ETH_MIN_MTU;
5246 switch (tp->version) {
5247 case RTL_VER_01:
5248 case RTL_VER_02:
5249 netdev->max_mtu = ETH_DATA_LEN;
5250 break;
5251 default:
5252 netdev->max_mtu = RTL8153_MAX_MTU;
5253 break;
5254 }
5255
5256 tp->mii.dev = netdev;
5257 tp->mii.mdio_read = read_mii_word;
5258 tp->mii.mdio_write = write_mii_word;
5259 tp->mii.phy_id_mask = 0x3f;
5260 tp->mii.reg_num_mask = 0x1f;
5261 tp->mii.phy_id = R8152_PHY_ID;
5262
5263 tp->autoneg = AUTONEG_ENABLE;
5264 tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100;
5265 tp->duplex = DUPLEX_FULL;
5266
5267 intf->needs_remote_wakeup = 1;
5268
5269 tp->rtl_ops.init(tp);
5270 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
5271 set_ethernet_addr(tp);
5272
5273 usb_set_intfdata(intf, tp);
5274 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
5275
5276 ret = register_netdev(netdev);
5277 if (ret != 0) {
5278 netif_err(tp, probe, netdev, "couldn't register the device\n");
5279 goto out1;
5280 }
5281
5282 if (!rtl_can_wakeup(tp))
5283 __rtl_set_wol(tp, 0);
5284
5285 tp->saved_wolopts = __rtl_get_wol(tp);
5286 if (tp->saved_wolopts)
5287 device_set_wakeup_enable(&udev->dev, true);
5288 else
5289 device_set_wakeup_enable(&udev->dev, false);
5290
5291 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
5292
5293 return 0;
5294
5295 out1:
5296 netif_napi_del(&tp->napi);
5297 usb_set_intfdata(intf, NULL);
5298 out:
5299 free_netdev(netdev);
5300 return ret;
5301 }
5302
5303 static void rtl8152_disconnect(struct usb_interface *intf)
5304 {
5305 struct r8152 *tp = usb_get_intfdata(intf);
5306
5307 usb_set_intfdata(intf, NULL);
5308 if (tp) {
5309 struct usb_device *udev = tp->udev;
5310
5311 if (udev->state == USB_STATE_NOTATTACHED)
5312 set_bit(RTL8152_UNPLUG, &tp->flags);
5313
5314 netif_napi_del(&tp->napi);
5315 unregister_netdev(tp->netdev);
5316 cancel_delayed_work_sync(&tp->hw_phy_work);
5317 tp->rtl_ops.unload(tp);
5318 free_netdev(tp->netdev);
5319 }
5320 }
5321
5322 #define REALTEK_USB_DEVICE(vend, prod) \
5323 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
5324 USB_DEVICE_ID_MATCH_INT_CLASS, \
5325 .idVendor = (vend), \
5326 .idProduct = (prod), \
5327 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
5328 }, \
5329 { \
5330 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
5331 USB_DEVICE_ID_MATCH_DEVICE, \
5332 .idVendor = (vend), \
5333 .idProduct = (prod), \
5334 .bInterfaceClass = USB_CLASS_COMM, \
5335 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
5336 .bInterfaceProtocol = USB_CDC_PROTO_NONE
5337
5338 /* table of devices that work with this driver */
5339 static const struct usb_device_id rtl8152_table[] = {
5340 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
5341 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
5342 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
5343 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
5344 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
5345 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
5346 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
5347 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)},
5348 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)},
5349 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
5350 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)},
5351 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)},
5352 {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
5353 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
5354 {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601)},
5355 {}
5356 };
5357
5358 MODULE_DEVICE_TABLE(usb, rtl8152_table);
5359
5360 static struct usb_driver rtl8152_driver = {
5361 .name = MODULENAME,
5362 .id_table = rtl8152_table,
5363 .probe = rtl8152_probe,
5364 .disconnect = rtl8152_disconnect,
5365 .suspend = rtl8152_suspend,
5366 .resume = rtl8152_resume,
5367 .reset_resume = rtl8152_reset_resume,
5368 .pre_reset = rtl8152_pre_reset,
5369 .post_reset = rtl8152_post_reset,
5370 .supports_autosuspend = 1,
5371 .disable_hub_initiated_lpm = 1,
5372 };
5373
5374 module_usb_driver(rtl8152_driver);
5375
5376 MODULE_AUTHOR(DRIVER_AUTHOR);
5377 MODULE_DESCRIPTION(DRIVER_DESC);
5378 MODULE_LICENSE("GPL");
5379 MODULE_VERSION(DRIVER_VERSION);