2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
3 * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl>
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #include "mt76x02_trace.h"
21 static enum mt76x02_cipher_type
22 mt76x02_mac_get_key_info(struct ieee80211_key_conf
*key
, u8
*key_data
)
24 memset(key_data
, 0, 32);
26 return MT_CIPHER_NONE
;
29 return MT_CIPHER_NONE
;
31 memcpy(key_data
, key
->key
, key
->keylen
);
33 switch (key
->cipher
) {
34 case WLAN_CIPHER_SUITE_WEP40
:
35 return MT_CIPHER_WEP40
;
36 case WLAN_CIPHER_SUITE_WEP104
:
37 return MT_CIPHER_WEP104
;
38 case WLAN_CIPHER_SUITE_TKIP
:
39 return MT_CIPHER_TKIP
;
40 case WLAN_CIPHER_SUITE_CCMP
:
41 return MT_CIPHER_AES_CCMP
;
43 return MT_CIPHER_NONE
;
47 int mt76x02_mac_shared_key_setup(struct mt76x02_dev
*dev
, u8 vif_idx
,
48 u8 key_idx
, struct ieee80211_key_conf
*key
)
50 enum mt76x02_cipher_type cipher
;
54 cipher
= mt76x02_mac_get_key_info(key
, key_data
);
55 if (cipher
== MT_CIPHER_NONE
&& key
)
58 val
= mt76_rr(dev
, MT_SKEY_MODE(vif_idx
));
59 val
&= ~(MT_SKEY_MODE_MASK
<< MT_SKEY_MODE_SHIFT(vif_idx
, key_idx
));
60 val
|= cipher
<< MT_SKEY_MODE_SHIFT(vif_idx
, key_idx
);
61 mt76_wr(dev
, MT_SKEY_MODE(vif_idx
), val
);
63 mt76_wr_copy(dev
, MT_SKEY(vif_idx
, key_idx
), key_data
,
68 EXPORT_SYMBOL_GPL(mt76x02_mac_shared_key_setup
);
70 int mt76x02_mac_wcid_set_key(struct mt76x02_dev
*dev
, u8 idx
,
71 struct ieee80211_key_conf
*key
)
73 enum mt76x02_cipher_type cipher
;
77 cipher
= mt76x02_mac_get_key_info(key
, key_data
);
78 if (cipher
== MT_CIPHER_NONE
&& key
)
81 mt76_wr_copy(dev
, MT_WCID_KEY(idx
), key_data
, sizeof(key_data
));
82 mt76_rmw_field(dev
, MT_WCID_ATTR(idx
), MT_WCID_ATTR_PKEY_MODE
, cipher
);
84 memset(iv_data
, 0, sizeof(iv_data
));
86 mt76_rmw_field(dev
, MT_WCID_ATTR(idx
), MT_WCID_ATTR_PAIRWISE
,
87 !!(key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
));
88 iv_data
[3] = key
->keyidx
<< 6;
89 if (cipher
>= MT_CIPHER_TKIP
)
93 mt76_wr_copy(dev
, MT_WCID_IV(idx
), iv_data
, sizeof(iv_data
));
98 void mt76x02_mac_wcid_setup(struct mt76x02_dev
*dev
, u8 idx
,
101 struct mt76_wcid_addr addr
= {};
104 attr
= FIELD_PREP(MT_WCID_ATTR_BSS_IDX
, vif_idx
& 7) |
105 FIELD_PREP(MT_WCID_ATTR_BSS_IDX_EXT
, !!(vif_idx
& 8));
107 mt76_wr(dev
, MT_WCID_ATTR(idx
), attr
);
113 memcpy(addr
.macaddr
, mac
, ETH_ALEN
);
115 mt76_wr_copy(dev
, MT_WCID_ADDR(idx
), &addr
, sizeof(addr
));
117 EXPORT_SYMBOL_GPL(mt76x02_mac_wcid_setup
);
119 void mt76x02_mac_wcid_set_drop(struct mt76x02_dev
*dev
, u8 idx
, bool drop
)
121 u32 val
= mt76_rr(dev
, MT_WCID_DROP(idx
));
122 u32 bit
= MT_WCID_DROP_MASK(idx
);
124 /* prevent unnecessary writes */
125 if ((val
& bit
) != (bit
* drop
))
126 mt76_wr(dev
, MT_WCID_DROP(idx
), (val
& ~bit
) | (bit
* drop
));
130 mt76x02_mac_tx_rate_val(struct mt76x02_dev
*dev
,
131 const struct ieee80211_tx_rate
*rate
, u8
*nss_val
)
133 u8 phy
, rate_idx
, nss
, bw
= 0;
136 if (rate
->flags
& IEEE80211_TX_RC_VHT_MCS
) {
137 rate_idx
= rate
->idx
;
138 nss
= 1 + (rate
->idx
>> 4);
139 phy
= MT_PHY_TYPE_VHT
;
140 if (rate
->flags
& IEEE80211_TX_RC_80_MHZ_WIDTH
)
142 else if (rate
->flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
)
144 } else if (rate
->flags
& IEEE80211_TX_RC_MCS
) {
145 rate_idx
= rate
->idx
;
146 nss
= 1 + (rate
->idx
>> 3);
147 phy
= MT_PHY_TYPE_HT
;
148 if (rate
->flags
& IEEE80211_TX_RC_GREEN_FIELD
)
149 phy
= MT_PHY_TYPE_HT_GF
;
150 if (rate
->flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
)
153 const struct ieee80211_rate
*r
;
154 int band
= dev
->mt76
.chandef
.chan
->band
;
157 r
= &dev
->mt76
.hw
->wiphy
->bands
[band
]->bitrates
[rate
->idx
];
158 if (rate
->flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
)
159 val
= r
->hw_value_short
;
164 rate_idx
= val
& 0xff;
168 rateval
= FIELD_PREP(MT_RXWI_RATE_INDEX
, rate_idx
);
169 rateval
|= FIELD_PREP(MT_RXWI_RATE_PHY
, phy
);
170 rateval
|= FIELD_PREP(MT_RXWI_RATE_BW
, bw
);
171 if (rate
->flags
& IEEE80211_TX_RC_SHORT_GI
)
172 rateval
|= MT_RXWI_RATE_SGI
;
175 return cpu_to_le16(rateval
);
178 void mt76x02_mac_wcid_set_rate(struct mt76x02_dev
*dev
, struct mt76_wcid
*wcid
,
179 const struct ieee80211_tx_rate
*rate
)
181 spin_lock_bh(&dev
->mt76
.lock
);
182 wcid
->tx_rate
= mt76x02_mac_tx_rate_val(dev
, rate
, &wcid
->tx_rate_nss
);
183 wcid
->tx_rate_set
= true;
184 spin_unlock_bh(&dev
->mt76
.lock
);
187 void mt76x02_mac_set_short_preamble(struct mt76x02_dev
*dev
, bool enable
)
190 mt76_set(dev
, MT_AUTO_RSP_CFG
, MT_AUTO_RSP_PREAMB_SHORT
);
192 mt76_clear(dev
, MT_AUTO_RSP_CFG
, MT_AUTO_RSP_PREAMB_SHORT
);
195 bool mt76x02_mac_load_tx_status(struct mt76x02_dev
*dev
,
196 struct mt76x02_tx_status
*stat
)
200 stat2
= mt76_rr(dev
, MT_TX_STAT_FIFO_EXT
);
201 stat1
= mt76_rr(dev
, MT_TX_STAT_FIFO
);
203 stat
->valid
= !!(stat1
& MT_TX_STAT_FIFO_VALID
);
207 stat
->success
= !!(stat1
& MT_TX_STAT_FIFO_SUCCESS
);
208 stat
->aggr
= !!(stat1
& MT_TX_STAT_FIFO_AGGR
);
209 stat
->ack_req
= !!(stat1
& MT_TX_STAT_FIFO_ACKREQ
);
210 stat
->wcid
= FIELD_GET(MT_TX_STAT_FIFO_WCID
, stat1
);
211 stat
->rate
= FIELD_GET(MT_TX_STAT_FIFO_RATE
, stat1
);
213 stat
->retry
= FIELD_GET(MT_TX_STAT_FIFO_EXT_RETRY
, stat2
);
214 stat
->pktid
= FIELD_GET(MT_TX_STAT_FIFO_EXT_PKTID
, stat2
);
216 trace_mac_txstat_fetch(dev
, stat
);
222 mt76x02_mac_process_tx_rate(struct ieee80211_tx_rate
*txrate
, u16 rate
,
223 enum nl80211_band band
)
225 u8 idx
= FIELD_GET(MT_RXWI_RATE_INDEX
, rate
);
231 switch (FIELD_GET(MT_RXWI_RATE_PHY
, rate
)) {
232 case MT_PHY_TYPE_OFDM
:
233 if (band
== NL80211_BAND_2GHZ
)
238 case MT_PHY_TYPE_CCK
:
244 case MT_PHY_TYPE_HT_GF
:
245 txrate
->flags
|= IEEE80211_TX_RC_GREEN_FIELD
;
248 txrate
->flags
|= IEEE80211_TX_RC_MCS
;
251 case MT_PHY_TYPE_VHT
:
252 txrate
->flags
|= IEEE80211_TX_RC_VHT_MCS
;
259 switch (FIELD_GET(MT_RXWI_RATE_BW
, rate
)) {
263 txrate
->flags
|= IEEE80211_TX_RC_40_MHZ_WIDTH
;
266 txrate
->flags
|= IEEE80211_TX_RC_80_MHZ_WIDTH
;
272 if (rate
& MT_RXWI_RATE_SGI
)
273 txrate
->flags
|= IEEE80211_TX_RC_SHORT_GI
;
278 void mt76x02_mac_write_txwi(struct mt76x02_dev
*dev
, struct mt76x02_txwi
*txwi
,
279 struct sk_buff
*skb
, struct mt76_wcid
*wcid
,
280 struct ieee80211_sta
*sta
, int len
)
282 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
283 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
284 struct ieee80211_tx_rate
*rate
= &info
->control
.rates
[0];
285 struct ieee80211_key_conf
*key
= info
->control
.hw_key
;
286 u16 rate_ht_mask
= FIELD_PREP(MT_RXWI_RATE_PHY
, BIT(1) | BIT(2));
289 s8 txpwr_adj
, max_txpwr_adj
;
290 u8 ccmp_pn
[8], nstreams
= dev
->mt76
.chainmask
& 0xf;
292 memset(txwi
, 0, sizeof(*txwi
));
294 if (!info
->control
.hw_key
&& wcid
&& wcid
->hw_key_idx
!= 0xff &&
295 ieee80211_has_protected(hdr
->frame_control
)) {
297 ieee80211_get_tx_rates(info
->control
.vif
, sta
, skb
,
298 info
->control
.rates
, 1);
302 txwi
->wcid
= wcid
->idx
;
306 if (wcid
&& wcid
->sw_iv
&& key
) {
307 u64 pn
= atomic64_inc_return(&key
->tx_pn
);
309 ccmp_pn
[1] = pn
>> 8;
311 ccmp_pn
[3] = 0x20 | (key
->keyidx
<< 6);
312 ccmp_pn
[4] = pn
>> 16;
313 ccmp_pn
[5] = pn
>> 24;
314 ccmp_pn
[6] = pn
>> 32;
315 ccmp_pn
[7] = pn
>> 40;
316 txwi
->iv
= *((__le32
*)&ccmp_pn
[0]);
317 txwi
->eiv
= *((__le32
*)&ccmp_pn
[4]);
320 spin_lock_bh(&dev
->mt76
.lock
);
321 if (wcid
&& (rate
->idx
< 0 || !rate
->count
)) {
322 txwi
->rate
= wcid
->tx_rate
;
323 max_txpwr_adj
= wcid
->max_txpwr_adj
;
324 nss
= wcid
->tx_rate_nss
;
326 txwi
->rate
= mt76x02_mac_tx_rate_val(dev
, rate
, &nss
);
327 max_txpwr_adj
= mt76x02_tx_get_max_txpwr_adj(dev
, rate
);
329 spin_unlock_bh(&dev
->mt76
.lock
);
331 txpwr_adj
= mt76x02_tx_get_txpwr_adj(dev
, dev
->mt76
.txpower_conf
,
333 txwi
->ctl2
= FIELD_PREP(MT_TX_PWR_ADJ
, txpwr_adj
);
335 if (nstreams
> 1 && mt76_rev(&dev
->mt76
) >= MT76XX_REV_E4
)
336 txwi
->txstream
= 0x13;
337 else if (nstreams
> 1 && mt76_rev(&dev
->mt76
) >= MT76XX_REV_E3
&&
338 !(txwi
->rate
& cpu_to_le16(rate_ht_mask
)))
339 txwi
->txstream
= 0x93;
341 if (is_mt76x2(dev
) && (info
->flags
& IEEE80211_TX_CTL_LDPC
))
342 txwi
->rate
|= cpu_to_le16(MT_RXWI_RATE_LDPC
);
343 if ((info
->flags
& IEEE80211_TX_CTL_STBC
) && nss
== 1)
344 txwi
->rate
|= cpu_to_le16(MT_RXWI_RATE_STBC
);
345 if (nss
> 1 && sta
&& sta
->smps_mode
== IEEE80211_SMPS_DYNAMIC
)
346 txwi_flags
|= MT_TXWI_FLAGS_MMPS
;
347 if (!(info
->flags
& IEEE80211_TX_CTL_NO_ACK
))
348 txwi
->ack_ctl
|= MT_TXWI_ACK_CTL_REQ
;
349 if (info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
)
350 txwi
->ack_ctl
|= MT_TXWI_ACK_CTL_NSEQ
;
351 if ((info
->flags
& IEEE80211_TX_CTL_AMPDU
) && sta
) {
352 u8 ba_size
= IEEE80211_MIN_AMPDU_BUF
;
354 ba_size
<<= sta
->ht_cap
.ampdu_factor
;
355 ba_size
= min_t(int, 63, ba_size
- 1);
356 if (info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
)
358 txwi
->ack_ctl
|= FIELD_PREP(MT_TXWI_ACK_CTL_BA_WINDOW
, ba_size
);
360 txwi_flags
|= MT_TXWI_FLAGS_AMPDU
|
361 FIELD_PREP(MT_TXWI_FLAGS_MPDU_DENSITY
,
362 sta
->ht_cap
.ampdu_density
);
365 if (ieee80211_is_probe_resp(hdr
->frame_control
) ||
366 ieee80211_is_beacon(hdr
->frame_control
))
367 txwi_flags
|= MT_TXWI_FLAGS_TS
;
369 txwi
->flags
|= cpu_to_le16(txwi_flags
);
370 txwi
->len_ctl
= cpu_to_le16(len
);
372 EXPORT_SYMBOL_GPL(mt76x02_mac_write_txwi
);
375 mt76x02_mac_fill_tx_status(struct mt76x02_dev
*dev
,
376 struct ieee80211_tx_info
*info
,
377 struct mt76x02_tx_status
*st
, int n_frames
)
379 struct ieee80211_tx_rate
*rate
= info
->status
.rates
;
380 int cur_idx
, last_rate
;
386 last_rate
= min_t(int, st
->retry
, IEEE80211_TX_MAX_RATES
- 1);
387 mt76x02_mac_process_tx_rate(&rate
[last_rate
], st
->rate
,
388 dev
->mt76
.chandef
.chan
->band
);
389 if (last_rate
< IEEE80211_TX_MAX_RATES
- 1)
390 rate
[last_rate
+ 1].idx
= -1;
392 cur_idx
= rate
[last_rate
].idx
+ last_rate
;
393 for (i
= 0; i
<= last_rate
; i
++) {
394 rate
[i
].flags
= rate
[last_rate
].flags
;
395 rate
[i
].idx
= max_t(int, 0, cur_idx
- i
);
398 rate
[last_rate
].count
= st
->retry
+ 1 - last_rate
;
400 info
->status
.ampdu_len
= n_frames
;
401 info
->status
.ampdu_ack_len
= st
->success
? n_frames
: 0;
404 info
->flags
|= IEEE80211_TX_CTL_AMPDU
|
405 IEEE80211_TX_STAT_AMPDU
;
408 info
->flags
|= IEEE80211_TX_CTL_NO_ACK
;
409 else if (st
->success
)
410 info
->flags
|= IEEE80211_TX_STAT_ACK
;
413 void mt76x02_send_tx_status(struct mt76x02_dev
*dev
,
414 struct mt76x02_tx_status
*stat
, u8
*update
)
416 struct ieee80211_tx_info info
= {};
417 struct ieee80211_tx_status status
= {
420 struct mt76_wcid
*wcid
= NULL
;
421 struct mt76x02_sta
*msta
= NULL
;
422 struct mt76_dev
*mdev
= &dev
->mt76
;
423 struct sk_buff_head list
;
425 if (stat
->pktid
== MT_PACKET_ID_NO_ACK
)
429 mt76_tx_status_lock(mdev
, &list
);
431 if (stat
->wcid
< ARRAY_SIZE(dev
->mt76
.wcid
))
432 wcid
= rcu_dereference(dev
->mt76
.wcid
[stat
->wcid
]);
434 if (wcid
&& wcid
->sta
) {
437 priv
= msta
= container_of(wcid
, struct mt76x02_sta
, wcid
);
438 status
.sta
= container_of(priv
, struct ieee80211_sta
,
443 if (stat
->pktid
>= MT_PACKET_ID_FIRST
)
444 status
.skb
= mt76_tx_status_skb_get(mdev
, wcid
,
447 status
.info
= IEEE80211_SKB_CB(status
.skb
);
450 if (msta
&& stat
->aggr
&& !status
.skb
) {
451 u32 stat_val
, stat_cache
;
453 stat_val
= stat
->rate
;
454 stat_val
|= ((u32
) stat
->retry
) << 16;
455 stat_cache
= msta
->status
.rate
;
456 stat_cache
|= ((u32
) msta
->status
.retry
) << 16;
458 if (*update
== 0 && stat_val
== stat_cache
&&
459 stat
->wcid
== msta
->status
.wcid
&& msta
->n_frames
< 32) {
464 mt76x02_mac_fill_tx_status(dev
, status
.info
, &msta
->status
,
467 msta
->status
= *stat
;
471 mt76x02_mac_fill_tx_status(dev
, status
.info
, stat
, 1);
476 mt76_tx_status_skb_done(mdev
, status
.skb
, &list
);
478 ieee80211_tx_status_ext(mt76_hw(dev
), &status
);
481 mt76_tx_status_unlock(mdev
, &list
);
486 mt76x02_mac_process_rate(struct mt76x02_dev
*dev
,
487 struct mt76_rx_status
*status
,
490 u8 idx
= FIELD_GET(MT_RXWI_RATE_INDEX
, rate
);
492 switch (FIELD_GET(MT_RXWI_RATE_PHY
, rate
)) {
493 case MT_PHY_TYPE_OFDM
:
497 if (status
->band
== NL80211_BAND_2GHZ
)
500 status
->rate_idx
= idx
;
502 case MT_PHY_TYPE_CCK
:
505 status
->enc_flags
|= RX_ENC_FLAG_SHORTPRE
;
511 status
->rate_idx
= idx
;
513 case MT_PHY_TYPE_HT_GF
:
514 status
->enc_flags
|= RX_ENC_FLAG_HT_GF
;
517 status
->encoding
= RX_ENC_HT
;
518 status
->rate_idx
= idx
;
520 case MT_PHY_TYPE_VHT
: {
521 u8 n_rxstream
= dev
->mt76
.chainmask
& 0xf;
523 status
->encoding
= RX_ENC_VHT
;
524 status
->rate_idx
= FIELD_GET(MT_RATE_INDEX_VHT_IDX
, idx
);
525 status
->nss
= min_t(u8
, n_rxstream
,
526 FIELD_GET(MT_RATE_INDEX_VHT_NSS
, idx
) + 1);
533 if (rate
& MT_RXWI_RATE_LDPC
)
534 status
->enc_flags
|= RX_ENC_FLAG_LDPC
;
536 if (rate
& MT_RXWI_RATE_SGI
)
537 status
->enc_flags
|= RX_ENC_FLAG_SHORT_GI
;
539 if (rate
& MT_RXWI_RATE_STBC
)
540 status
->enc_flags
|= 1 << RX_ENC_FLAG_STBC_SHIFT
;
542 switch (FIELD_GET(MT_RXWI_RATE_BW
, rate
)) {
546 status
->bw
= RATE_INFO_BW_40
;
549 status
->bw
= RATE_INFO_BW_80
;
558 void mt76x02_mac_setaddr(struct mt76x02_dev
*dev
, const u8
*addr
)
560 static const u8 null_addr
[ETH_ALEN
] = {};
563 ether_addr_copy(dev
->mt76
.macaddr
, addr
);
565 if (!is_valid_ether_addr(dev
->mt76
.macaddr
)) {
566 eth_random_addr(dev
->mt76
.macaddr
);
567 dev_info(dev
->mt76
.dev
,
568 "Invalid MAC address, using random address %pM\n",
572 mt76_wr(dev
, MT_MAC_ADDR_DW0
, get_unaligned_le32(dev
->mt76
.macaddr
));
573 mt76_wr(dev
, MT_MAC_ADDR_DW1
,
574 get_unaligned_le16(dev
->mt76
.macaddr
+ 4) |
575 FIELD_PREP(MT_MAC_ADDR_DW1_U2ME_MASK
, 0xff));
577 mt76_wr(dev
, MT_MAC_BSSID_DW0
,
578 get_unaligned_le32(dev
->mt76
.macaddr
));
579 mt76_wr(dev
, MT_MAC_BSSID_DW1
,
580 get_unaligned_le16(dev
->mt76
.macaddr
+ 4) |
581 FIELD_PREP(MT_MAC_BSSID_DW1_MBSS_MODE
, 3) | /* 8 APs + 8 STAs */
582 MT_MAC_BSSID_DW1_MBSS_LOCAL_BIT
);
584 for (i
= 0; i
< 16; i
++)
585 mt76x02_mac_set_bssid(dev
, i
, null_addr
);
587 EXPORT_SYMBOL_GPL(mt76x02_mac_setaddr
);
590 mt76x02_mac_get_rssi(struct mt76x02_dev
*dev
, s8 rssi
, int chain
)
592 struct mt76x02_rx_freq_cal
*cal
= &dev
->cal
.rx
;
594 rssi
+= cal
->rssi_offset
[chain
];
595 rssi
-= cal
->lna_gain
;
600 int mt76x02_mac_process_rx(struct mt76x02_dev
*dev
, struct sk_buff
*skb
,
603 struct mt76_rx_status
*status
= (struct mt76_rx_status
*) skb
->cb
;
604 struct mt76x02_rxwi
*rxwi
= rxi
;
605 struct mt76x02_sta
*sta
;
606 u32 rxinfo
= le32_to_cpu(rxwi
->rxinfo
);
607 u32 ctl
= le32_to_cpu(rxwi
->ctl
);
608 u16 rate
= le16_to_cpu(rxwi
->rate
);
609 u16 tid_sn
= le16_to_cpu(rxwi
->tid_sn
);
610 bool unicast
= rxwi
->rxinfo
& cpu_to_le32(MT_RXINFO_UNICAST
);
611 int pad_len
= 0, nstreams
= dev
->mt76
.chainmask
& 0xf;
617 if (!test_bit(MT76_STATE_RUNNING
, &dev
->mt76
.state
))
620 if (rxinfo
& MT_RXINFO_L2PAD
)
623 if (rxinfo
& MT_RXINFO_DECRYPT
) {
624 status
->flag
|= RX_FLAG_DECRYPTED
;
625 status
->flag
|= RX_FLAG_MMIC_STRIPPED
;
626 status
->flag
|= RX_FLAG_MIC_STRIPPED
;
627 status
->flag
|= RX_FLAG_IV_STRIPPED
;
630 wcid
= FIELD_GET(MT_RXWI_CTL_WCID
, ctl
);
631 sta
= mt76x02_rx_get_sta(&dev
->mt76
, wcid
);
632 status
->wcid
= mt76x02_rx_get_sta_wcid(sta
, unicast
);
634 len
= FIELD_GET(MT_RXWI_CTL_MPDU_LEN
, ctl
);
635 pn_len
= FIELD_GET(MT_RXINFO_PN_LEN
, rxinfo
);
637 int offset
= ieee80211_get_hdrlen_from_skb(skb
) + pad_len
;
638 u8
*data
= skb
->data
+ offset
;
640 status
->iv
[0] = data
[7];
641 status
->iv
[1] = data
[6];
642 status
->iv
[2] = data
[5];
643 status
->iv
[3] = data
[4];
644 status
->iv
[4] = data
[1];
645 status
->iv
[5] = data
[0];
648 * Driver CCMP validation can't deal with fragments.
649 * Let mac80211 take care of it.
651 if (rxinfo
& MT_RXINFO_FRAG
) {
652 status
->flag
&= ~RX_FLAG_IV_STRIPPED
;
654 pad_len
+= pn_len
<< 2;
659 mt76x02_remove_hdr_pad(skb
, pad_len
);
661 if ((rxinfo
& MT_RXINFO_BA
) && !(rxinfo
& MT_RXINFO_NULL
))
664 if (WARN_ON_ONCE(len
> skb
->len
))
669 status
->chains
= BIT(0);
670 signal
= mt76x02_mac_get_rssi(dev
, rxwi
->rssi
[0], 0);
671 status
->chain_signal
[0] = signal
;
673 status
->chains
|= BIT(1);
674 status
->chain_signal
[1] = mt76x02_mac_get_rssi(dev
,
677 signal
= max_t(s8
, signal
, status
->chain_signal
[1]);
679 status
->signal
= signal
;
680 status
->freq
= dev
->mt76
.chandef
.chan
->center_freq
;
681 status
->band
= dev
->mt76
.chandef
.chan
->band
;
683 status
->tid
= FIELD_GET(MT_RXWI_TID
, tid_sn
);
684 status
->seqno
= FIELD_GET(MT_RXWI_SN
, tid_sn
);
686 return mt76x02_mac_process_rate(dev
, status
, rate
);
689 void mt76x02_mac_poll_tx_status(struct mt76x02_dev
*dev
, bool irq
)
691 struct mt76x02_tx_status stat
= {};
696 if (!test_bit(MT76_STATE_RUNNING
, &dev
->mt76
.state
))
699 trace_mac_txstat_poll(dev
);
701 while (!irq
|| !kfifo_is_full(&dev
->txstatus_fifo
)) {
702 spin_lock_irqsave(&dev
->mt76
.mmio
.irq_lock
, flags
);
703 ret
= mt76x02_mac_load_tx_status(dev
, &stat
);
704 spin_unlock_irqrestore(&dev
->mt76
.mmio
.irq_lock
, flags
);
710 mt76x02_send_tx_status(dev
, &stat
, &update
);
714 kfifo_put(&dev
->txstatus_fifo
, stat
);
718 void mt76x02_tx_complete_skb(struct mt76_dev
*mdev
, struct mt76_queue
*q
,
719 struct mt76_queue_entry
*e
, bool flush
)
721 struct mt76x02_dev
*dev
= container_of(mdev
, struct mt76x02_dev
, mt76
);
722 struct mt76x02_txwi
*txwi
;
725 dev_kfree_skb_any(e
->skb
);
729 mt76x02_mac_poll_tx_status(dev
, false);
731 txwi
= (struct mt76x02_txwi
*) &e
->txwi
->txwi
;
732 trace_mac_txdone_add(dev
, txwi
->wcid
, txwi
->pktid
);
734 mt76_tx_complete_skb(mdev
, e
->skb
);
736 EXPORT_SYMBOL_GPL(mt76x02_tx_complete_skb
);
738 void mt76x02_mac_set_rts_thresh(struct mt76x02_dev
*dev
, u32 val
)
743 data
= FIELD_PREP(MT_PROT_CFG_CTRL
, 1) |
744 MT_PROT_CFG_RTS_THRESH
;
746 mt76_rmw_field(dev
, MT_TX_RTS_CFG
, MT_TX_RTS_CFG_THRESH
, val
);
748 mt76_rmw(dev
, MT_CCK_PROT_CFG
,
749 MT_PROT_CFG_CTRL
| MT_PROT_CFG_RTS_THRESH
, data
);
750 mt76_rmw(dev
, MT_OFDM_PROT_CFG
,
751 MT_PROT_CFG_CTRL
| MT_PROT_CFG_RTS_THRESH
, data
);
754 void mt76x02_mac_set_tx_protection(struct mt76x02_dev
*dev
, bool legacy_prot
,
757 int mode
= ht_mode
& IEEE80211_HT_OP_MODE_PROTECTION
;
758 bool non_gf
= !!(ht_mode
& IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT
);
764 for (i
= 0; i
< ARRAY_SIZE(prot
); i
++) {
765 prot
[i
] = mt76_rr(dev
, MT_CCK_PROT_CFG
+ i
* 4);
766 prot
[i
] &= ~MT_PROT_CFG_CTRL
;
768 prot
[i
] &= ~MT_PROT_CFG_RATE
;
771 for (i
= 0; i
< ARRAY_SIZE(vht_prot
); i
++) {
772 vht_prot
[i
] = mt76_rr(dev
, MT_TX_PROT_CFG6
+ i
* 4);
773 vht_prot
[i
] &= ~(MT_PROT_CFG_CTRL
| MT_PROT_CFG_RATE
);
776 rts_thr
= mt76_get_field(dev
, MT_TX_RTS_CFG
, MT_TX_RTS_CFG_THRESH
);
778 if (rts_thr
!= 0xffff)
779 prot
[0] |= MT_PROT_CTRL_RTS_CTS
;
782 prot
[1] |= MT_PROT_CTRL_CTS2SELF
;
784 prot
[2] |= MT_PROT_RATE_CCK_11
;
785 prot
[3] |= MT_PROT_RATE_CCK_11
;
786 prot
[4] |= MT_PROT_RATE_CCK_11
;
787 prot
[5] |= MT_PROT_RATE_CCK_11
;
789 vht_prot
[0] |= MT_PROT_RATE_CCK_11
;
790 vht_prot
[1] |= MT_PROT_RATE_CCK_11
;
791 vht_prot
[2] |= MT_PROT_RATE_CCK_11
;
793 if (rts_thr
!= 0xffff)
794 prot
[1] |= MT_PROT_CTRL_RTS_CTS
;
796 prot
[2] |= MT_PROT_RATE_OFDM_24
;
797 prot
[3] |= MT_PROT_RATE_DUP_OFDM_24
;
798 prot
[4] |= MT_PROT_RATE_OFDM_24
;
799 prot
[5] |= MT_PROT_RATE_DUP_OFDM_24
;
801 vht_prot
[0] |= MT_PROT_RATE_OFDM_24
;
802 vht_prot
[1] |= MT_PROT_RATE_DUP_OFDM_24
;
803 vht_prot
[2] |= MT_PROT_RATE_SGI_OFDM_24
;
807 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER
:
808 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED
:
809 prot
[2] |= MT_PROT_CTRL_RTS_CTS
;
810 prot
[3] |= MT_PROT_CTRL_RTS_CTS
;
811 prot
[4] |= MT_PROT_CTRL_RTS_CTS
;
812 prot
[5] |= MT_PROT_CTRL_RTS_CTS
;
813 vht_prot
[0] |= MT_PROT_CTRL_RTS_CTS
;
814 vht_prot
[1] |= MT_PROT_CTRL_RTS_CTS
;
815 vht_prot
[2] |= MT_PROT_CTRL_RTS_CTS
;
817 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ
:
818 prot
[3] |= MT_PROT_CTRL_RTS_CTS
;
819 prot
[5] |= MT_PROT_CTRL_RTS_CTS
;
820 vht_prot
[1] |= MT_PROT_CTRL_RTS_CTS
;
821 vht_prot
[2] |= MT_PROT_CTRL_RTS_CTS
;
826 prot
[4] |= MT_PROT_CTRL_RTS_CTS
;
827 prot
[5] |= MT_PROT_CTRL_RTS_CTS
;
830 for (i
= 0; i
< ARRAY_SIZE(prot
); i
++)
831 mt76_wr(dev
, MT_CCK_PROT_CFG
+ i
* 4, prot
[i
]);
833 for (i
= 0; i
< ARRAY_SIZE(vht_prot
); i
++)
834 mt76_wr(dev
, MT_TX_PROT_CFG6
+ i
* 4, vht_prot
[i
]);
837 void mt76x02_update_channel(struct mt76_dev
*mdev
)
839 struct mt76x02_dev
*dev
= container_of(mdev
, struct mt76x02_dev
, mt76
);
840 struct mt76_channel_state
*state
;
843 state
= mt76_channel_state(&dev
->mt76
, dev
->mt76
.chandef
.chan
);
845 busy
= mt76_rr(dev
, MT_CH_BUSY
);
846 active
= busy
+ mt76_rr(dev
, MT_CH_IDLE
);
848 spin_lock_bh(&dev
->mt76
.cc_lock
);
849 state
->cc_busy
+= busy
;
850 state
->cc_active
+= active
;
851 spin_unlock_bh(&dev
->mt76
.cc_lock
);
853 EXPORT_SYMBOL_GPL(mt76x02_update_channel
);
855 static void mt76x02_check_mac_err(struct mt76x02_dev
*dev
)
857 u32 val
= mt76_rr(dev
, 0x10f4);
859 if (!(val
& BIT(29)) || !(val
& (BIT(7) | BIT(5))))
862 dev_err(dev
->mt76
.dev
, "mac specific condition occurred\n");
864 mt76_set(dev
, MT_MAC_SYS_CTRL
, MT_MAC_SYS_CTRL_RESET_CSR
);
866 mt76_wr(dev
, MT_MAC_SYS_CTRL
,
867 MT_MAC_SYS_CTRL_ENABLE_TX
| MT_MAC_SYS_CTRL_ENABLE_RX
);
871 mt76x02_edcca_tx_enable(struct mt76x02_dev
*dev
, bool enable
)
876 mt76_set(dev
, MT_MAC_SYS_CTRL
, MT_MAC_SYS_CTRL_ENABLE_TX
);
877 mt76_set(dev
, MT_AUTO_RSP_CFG
, MT_AUTO_RSP_EN
);
879 data
= mt76_rr(dev
, MT_TX_PIN_CFG
);
880 data
|= MT_TX_PIN_CFG_TXANT
|
881 MT_TX_PIN_CFG_RXANT
|
884 mt76_wr(dev
, MT_TX_PIN_CFG
, data
);
886 mt76_clear(dev
, MT_MAC_SYS_CTRL
, MT_MAC_SYS_CTRL_ENABLE_TX
);
887 mt76_clear(dev
, MT_AUTO_RSP_CFG
, MT_AUTO_RSP_EN
);
889 mt76_clear(dev
, MT_TX_PIN_CFG
, MT_TX_PIN_CFG_TXANT
);
890 mt76_clear(dev
, MT_TX_PIN_CFG
, MT_TX_PIN_CFG_RXANT
);
892 dev
->ed_tx_blocked
= !enable
;
895 void mt76x02_edcca_init(struct mt76x02_dev
*dev
, bool enable
)
900 if (dev
->ed_monitor
&& enable
) {
901 struct ieee80211_channel
*chan
= dev
->mt76
.chandef
.chan
;
902 u8 ed_th
= chan
->band
== NL80211_BAND_5GHZ
? 0x0e : 0x20;
904 mt76_clear(dev
, MT_TX_LINK_CFG
, MT_TX_CFACK_EN
);
905 mt76_set(dev
, MT_TXOP_CTRL_CFG
, MT_TXOP_ED_CCA_EN
);
906 mt76_rmw(dev
, MT_BBP(AGC
, 2), GENMASK(15, 0),
908 mt76_set(dev
, MT_TXOP_HLDR_ET
, MT_TXOP_HLDR_TX40M_BLK_EN
);
910 mt76_set(dev
, MT_TX_LINK_CFG
, MT_TX_CFACK_EN
);
911 mt76_clear(dev
, MT_TXOP_CTRL_CFG
, MT_TXOP_ED_CCA_EN
);
912 if (is_mt76x2(dev
)) {
913 mt76_wr(dev
, MT_BBP(AGC
, 2), 0x00007070);
914 mt76_set(dev
, MT_TXOP_HLDR_ET
,
915 MT_TXOP_HLDR_TX40M_BLK_EN
);
917 mt76_wr(dev
, MT_BBP(AGC
, 2), 0x003a6464);
918 mt76_clear(dev
, MT_TXOP_HLDR_ET
,
919 MT_TXOP_HLDR_TX40M_BLK_EN
);
922 mt76x02_edcca_tx_enable(dev
, true);
924 /* clear previous CCA timer value */
925 mt76_rr(dev
, MT_ED_CCA_TIMER
);
926 dev
->ed_time
= ktime_get_boottime();
928 EXPORT_SYMBOL_GPL(mt76x02_edcca_init
);
930 #define MT_EDCCA_TH 92
931 #define MT_EDCCA_BLOCK_TH 2
932 static void mt76x02_edcca_check(struct mt76x02_dev
*dev
)
935 u32 active
, val
, busy
;
937 cur_time
= ktime_get_boottime();
938 val
= mt76_rr(dev
, MT_ED_CCA_TIMER
);
940 active
= ktime_to_us(ktime_sub(cur_time
, dev
->ed_time
));
941 dev
->ed_time
= cur_time
;
943 busy
= (val
* 100) / active
;
944 busy
= min_t(u32
, busy
, 100);
946 if (busy
> MT_EDCCA_TH
) {
954 if (dev
->ed_trigger
> MT_EDCCA_BLOCK_TH
&&
956 mt76x02_edcca_tx_enable(dev
, false);
957 else if (dev
->ed_silent
> MT_EDCCA_BLOCK_TH
&&
959 mt76x02_edcca_tx_enable(dev
, true);
962 void mt76x02_mac_work(struct work_struct
*work
)
964 struct mt76x02_dev
*dev
= container_of(work
, struct mt76x02_dev
,
968 mutex_lock(&dev
->mt76
.mutex
);
970 mt76x02_update_channel(&dev
->mt76
);
971 for (i
= 0, idx
= 0; i
< 16; i
++) {
972 u32 val
= mt76_rr(dev
, MT_TX_AGG_CNT(i
));
974 dev
->aggr_stats
[idx
++] += val
& 0xffff;
975 dev
->aggr_stats
[idx
++] += val
>> 16;
978 if (!dev
->beacon_mask
)
979 mt76x02_check_mac_err(dev
);
982 mt76x02_edcca_check(dev
);
984 mutex_unlock(&dev
->mt76
.mutex
);
986 mt76_tx_status_check(&dev
->mt76
, NULL
, false);
988 ieee80211_queue_delayed_work(mt76_hw(dev
), &dev
->mac_work
,
989 MT_MAC_WORK_INTERVAL
);
992 void mt76x02_mac_set_bssid(struct mt76x02_dev
*dev
, u8 idx
, const u8
*addr
)
995 mt76_wr(dev
, MT_MAC_APC_BSSID_L(idx
), get_unaligned_le32(addr
));
996 mt76_rmw_field(dev
, MT_MAC_APC_BSSID_H(idx
), MT_MAC_APC_BSSID_H_ADDR
,
997 get_unaligned_le16(addr
+ 4));
1001 mt76x02_write_beacon(struct mt76x02_dev
*dev
, int offset
, struct sk_buff
*skb
)
1003 int beacon_len
= mt76x02_beacon_offsets
[1] - mt76x02_beacon_offsets
[0];
1004 struct mt76x02_txwi txwi
;
1006 if (WARN_ON_ONCE(beacon_len
< skb
->len
+ sizeof(struct mt76x02_txwi
)))
1009 mt76x02_mac_write_txwi(dev
, &txwi
, skb
, NULL
, NULL
, skb
->len
);
1011 mt76_wr_copy(dev
, offset
, &txwi
, sizeof(txwi
));
1012 offset
+= sizeof(txwi
);
1014 mt76_wr_copy(dev
, offset
, skb
->data
, skb
->len
);
1019 __mt76x02_mac_set_beacon(struct mt76x02_dev
*dev
, u8 bcn_idx
,
1020 struct sk_buff
*skb
)
1022 int beacon_len
= mt76x02_beacon_offsets
[1] - mt76x02_beacon_offsets
[0];
1023 int beacon_addr
= mt76x02_beacon_offsets
[bcn_idx
];
1027 /* Prevent corrupt transmissions during update */
1028 mt76_set(dev
, MT_BCN_BYPASS_MASK
, BIT(bcn_idx
));
1031 ret
= mt76x02_write_beacon(dev
, beacon_addr
, skb
);
1033 dev
->beacon_data_mask
|= BIT(bcn_idx
);
1035 dev
->beacon_data_mask
&= ~BIT(bcn_idx
);
1036 for (i
= 0; i
< beacon_len
; i
+= 4)
1037 mt76_wr(dev
, beacon_addr
+ i
, 0);
1040 mt76_wr(dev
, MT_BCN_BYPASS_MASK
, 0xff00 | ~dev
->beacon_data_mask
);
1045 int mt76x02_mac_set_beacon(struct mt76x02_dev
*dev
, u8 vif_idx
,
1046 struct sk_buff
*skb
)
1048 bool force_update
= false;
1052 for (i
= 0; i
< ARRAY_SIZE(dev
->beacons
); i
++) {
1054 force_update
= !!dev
->beacons
[i
] ^ !!skb
;
1056 if (dev
->beacons
[i
])
1057 dev_kfree_skb(dev
->beacons
[i
]);
1059 dev
->beacons
[i
] = skb
;
1060 __mt76x02_mac_set_beacon(dev
, bcn_idx
, skb
);
1061 } else if (force_update
&& dev
->beacons
[i
]) {
1062 __mt76x02_mac_set_beacon(dev
, bcn_idx
,
1066 bcn_idx
+= !!dev
->beacons
[i
];
1069 for (i
= bcn_idx
; i
< ARRAY_SIZE(dev
->beacons
); i
++) {
1070 if (!(dev
->beacon_data_mask
& BIT(i
)))
1073 __mt76x02_mac_set_beacon(dev
, i
, NULL
);
1076 mt76_rmw_field(dev
, MT_MAC_BSSID_DW1
, MT_MAC_BSSID_DW1_MBEACON_N
,
1082 __mt76x02_mac_set_beacon_enable(struct mt76x02_dev
*dev
, u8 vif_idx
,
1083 bool val
, struct sk_buff
*skb
)
1085 u8 old_mask
= dev
->beacon_mask
;
1090 dev
->beacon_mask
|= BIT(vif_idx
);
1092 mt76x02_mac_set_beacon(dev
, vif_idx
, skb
);
1094 dev
->beacon_mask
&= ~BIT(vif_idx
);
1095 mt76x02_mac_set_beacon(dev
, vif_idx
, NULL
);
1098 if (!!old_mask
== !!dev
->beacon_mask
)
1101 en
= dev
->beacon_mask
;
1103 reg
= MT_BEACON_TIME_CFG_BEACON_TX
|
1104 MT_BEACON_TIME_CFG_TBTT_EN
|
1105 MT_BEACON_TIME_CFG_TIMER_EN
;
1106 mt76_rmw(dev
, MT_BEACON_TIME_CFG
, reg
, reg
* en
);
1108 if (mt76_is_usb(dev
))
1111 mt76_rmw_field(dev
, MT_INT_TIMER_EN
, MT_INT_TIMER_EN_PRE_TBTT_EN
, en
);
1113 mt76x02_irq_enable(dev
, MT_INT_PRE_TBTT
| MT_INT_TBTT
);
1115 mt76x02_irq_disable(dev
, MT_INT_PRE_TBTT
| MT_INT_TBTT
);
1118 void mt76x02_mac_set_beacon_enable(struct mt76x02_dev
*dev
,
1119 struct ieee80211_vif
*vif
, bool val
)
1121 u8 vif_idx
= ((struct mt76x02_vif
*)vif
->drv_priv
)->idx
;
1122 struct sk_buff
*skb
= NULL
;
1124 if (mt76_is_mmio(dev
))
1125 tasklet_disable(&dev
->pre_tbtt_tasklet
);
1127 skb
= ieee80211_beacon_get(mt76_hw(dev
), vif
);
1129 if (!dev
->beacon_mask
)
1130 dev
->tbtt_count
= 0;
1132 __mt76x02_mac_set_beacon_enable(dev
, vif_idx
, val
, skb
);
1134 if (mt76_is_mmio(dev
))
1135 tasklet_enable(&dev
->pre_tbtt_tasklet
);