drivers/net/wireless/ralink/rt2x00/rt2800.h

   1 /*
   2         Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
   3         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   4         Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   5         Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   6         Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
   7         Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
   8         Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
   9         Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  10         Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
  11         <http://rt2x00.serialmonkey.com>
  12
  13         This program is free software; you can redistribute it and/or modify
  14         it under the terms of the GNU General Public License as published by
  15         the Free Software Foundation; either version 2 of the License, or
  16         (at your option) any later version.
  17
  18         This program is distributed in the hope that it will be useful,
  19         but WITHOUT ANY WARRANTY; without even the implied warranty of
  20         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21         GNU General Public License for more details.
  22
  23         You should have received a copy of the GNU General Public License
  24         along with this program; if not, see <http://www.gnu.org/licenses/>.
  25  */
  26
  27 /*
  28         Module: rt2800
  29         Abstract: Data structures and registers for the rt2800 modules.
  30         Supported chipsets: RT2800E, RT2800ED & RT2800U.
  31  */
  32
  33 #ifndef RT2800_H
  34 #define RT2800_H
  35
  36 /*
  37  * RF chip defines.
  38  *
  39  * RF2820 2.4G 2T3R
  40  * RF2850 2.4G/5G 2T3R
  41  * RF2720 2.4G 1T2R
  42  * RF2750 2.4G/5G 1T2R
  43  * RF3020 2.4G 1T1R
  44  * RF2020 2.4G B/G
  45  * RF3021 2.4G 1T2R
  46  * RF3022 2.4G 2T2R
  47  * RF3052 2.4G/5G 2T2R
  48  * RF2853 2.4G/5G 3T3R
  49  * RF3320 2.4G 1T1R(RT3350/RT3370/RT3390)
  50  * RF3322 2.4G 2T2R(RT3352/RT3371/RT3372/RT3391/RT3392)
  51  * RF3053 2.4G/5G 3T3R(RT3883/RT3563/RT3573/RT3593/RT3662)
  52  * RF5592 2.4G/5G 2T2R
  53  * RF3070 2.4G 1T1R
  54  * RF5360 2.4G 1T1R
  55  * RF5362 2.4G 1T1R
  56  * RF5370 2.4G 1T1R
  57  * RF5390 2.4G 1T1R
  58  */
  59 #define RF2820                          0x0001
  60 #define RF2850                          0x0002
  61 #define RF2720                          0x0003
  62 #define RF2750                          0x0004
  63 #define RF3020                          0x0005
  64 #define RF2020                          0x0006
  65 #define RF3021                          0x0007
  66 #define RF3022                          0x0008
  67 #define RF3052                          0x0009
  68 #define RF2853                          0x000a
  69 #define RF3320                          0x000b
  70 #define RF3322                          0x000c
  71 #define RF3053                          0x000d
  72 #define RF5592                          0x000f
  73 #define RF3070                          0x3070
  74 #define RF3290                          0x3290
  75 #define RF5360                          0x5360
  76 #define RF5362                          0x5362
  77 #define RF5370                          0x5370
  78 #define RF5372                          0x5372
  79 #define RF5390                          0x5390
  80 #define RF5392                          0x5392
  81
  82 /*
  83  * Chipset revisions.
  84  */
  85 #define REV_RT2860C                     0x0100
  86 #define REV_RT2860D                     0x0101
  87 #define REV_RT2872E                     0x0200
  88 #define REV_RT3070E                     0x0200
  89 #define REV_RT3070F                     0x0201
  90 #define REV_RT3071E                     0x0211
  91 #define REV_RT3090E                     0x0211
  92 #define REV_RT3390E                     0x0211
  93 #define REV_RT3593E                     0x0211
  94 #define REV_RT5390F                     0x0502
  95 #define REV_RT5390R                     0x1502
  96 #define REV_RT5592C                     0x0221
  97
  98 #define DEFAULT_RSSI_OFFSET             120
  99
 100 /*
 101  * Register layout information.
 102  */
 103 #define CSR_REG_BASE                    0x1000
 104 #define CSR_REG_SIZE                    0x0800
 105 #define EEPROM_BASE                     0x0000
 106 #define EEPROM_SIZE                     0x0200
 107 #define BBP_BASE                        0x0000
 108 #define BBP_SIZE                        0x00ff
 109 #define RF_BASE                         0x0004
 110 #define RF_SIZE                         0x0010
 111 #define RFCSR_BASE                      0x0000
 112 #define RFCSR_SIZE                      0x0040
 113
 114 /*
 115  * Number of TX queues.
 116  */
 117 #define NUM_TX_QUEUES                   4
 118
 119 /*
 120  * Registers.
 121  */
 122
 123
 124 /*
 125  * MAC_CSR0_3290: MAC_CSR0 for RT3290 to identity MAC version number.
 126  */
 127 #define MAC_CSR0_3290                   0x0000
 128
 129 /*
 130  * E2PROM_CSR: PCI EEPROM control register.
 131  * RELOAD: Write 1 to reload eeprom content.
 132  * TYPE: 0: 93c46, 1:93c66.
 133  * LOAD_STATUS: 1:loading, 0:done.
 134  */
 135 #define E2PROM_CSR                      0x0004
 136 #define E2PROM_CSR_DATA_CLOCK           FIELD32(0x00000001)
 137 #define E2PROM_CSR_CHIP_SELECT          FIELD32(0x00000002)
 138 #define E2PROM_CSR_DATA_IN              FIELD32(0x00000004)
 139 #define E2PROM_CSR_DATA_OUT             FIELD32(0x00000008)
 140 #define E2PROM_CSR_TYPE                 FIELD32(0x00000030)
 141 #define E2PROM_CSR_LOAD_STATUS          FIELD32(0x00000040)
 142 #define E2PROM_CSR_RELOAD               FIELD32(0x00000080)
 143
 144 /*
 145  * CMB_CTRL_CFG
 146  */
 147 #define CMB_CTRL                0x0020
 148 #define AUX_OPT_BIT0            FIELD32(0x00000001)
 149 #define AUX_OPT_BIT1            FIELD32(0x00000002)
 150 #define AUX_OPT_BIT2            FIELD32(0x00000004)
 151 #define AUX_OPT_BIT3            FIELD32(0x00000008)
 152 #define AUX_OPT_BIT4            FIELD32(0x00000010)
 153 #define AUX_OPT_BIT5            FIELD32(0x00000020)
 154 #define AUX_OPT_BIT6            FIELD32(0x00000040)
 155 #define AUX_OPT_BIT7            FIELD32(0x00000080)
 156 #define AUX_OPT_BIT8            FIELD32(0x00000100)
 157 #define AUX_OPT_BIT9            FIELD32(0x00000200)
 158 #define AUX_OPT_BIT10           FIELD32(0x00000400)
 159 #define AUX_OPT_BIT11           FIELD32(0x00000800)
 160 #define AUX_OPT_BIT12           FIELD32(0x00001000)
 161 #define AUX_OPT_BIT13           FIELD32(0x00002000)
 162 #define AUX_OPT_BIT14           FIELD32(0x00004000)
 163 #define AUX_OPT_BIT15           FIELD32(0x00008000)
 164 #define LDO25_LEVEL             FIELD32(0x00030000)
 165 #define LDO25_LARGEA            FIELD32(0x00040000)
 166 #define LDO25_FRC_ON            FIELD32(0x00080000)
 167 #define CMB_RSV                 FIELD32(0x00300000)
 168 #define XTAL_RDY                FIELD32(0x00400000)
 169 #define PLL_LD                  FIELD32(0x00800000)
 170 #define LDO_CORE_LEVEL          FIELD32(0x0F000000)
 171 #define LDO_BGSEL               FIELD32(0x30000000)
 172 #define LDO3_EN                 FIELD32(0x40000000)
 173 #define LDO0_EN                 FIELD32(0x80000000)
 174
 175 /*
 176  * EFUSE_CSR_3290: RT3290 EEPROM
 177  */
 178 #define EFUSE_CTRL_3290                 0x0024
 179
 180 /*
 181  * EFUSE_DATA3 of 3290
 182  */
 183 #define EFUSE_DATA3_3290                0x0028
 184
 185 /*
 186  * EFUSE_DATA2 of 3290
 187  */
 188 #define EFUSE_DATA2_3290                0x002c
 189
 190 /*
 191  * EFUSE_DATA1 of 3290
 192  */
 193 #define EFUSE_DATA1_3290                0x0030
 194
 195 /*
 196  * EFUSE_DATA0 of 3290
 197  */
 198 #define EFUSE_DATA0_3290                0x0034
 199
 200 /*
 201  * OSC_CTRL_CFG
 202  * Ring oscillator configuration
 203  */
 204 #define OSC_CTRL                0x0038
 205 #define OSC_REF_CYCLE           FIELD32(0x00001fff)
 206 #define OSC_RSV                 FIELD32(0x0000e000)
 207 #define OSC_CAL_CNT             FIELD32(0x0fff0000)
 208 #define OSC_CAL_ACK             FIELD32(0x10000000)
 209 #define OSC_CLK_32K_VLD         FIELD32(0x20000000)
 210 #define OSC_CAL_REQ             FIELD32(0x40000000)
 211 #define OSC_ROSC_EN             FIELD32(0x80000000)
 212
 213 /*
 214  * COEX_CFG_0
 215  */
 216 #define COEX_CFG0               0x0040
 217 #define COEX_CFG_ANT            FIELD32(0xff000000)
 218 /*
 219  * COEX_CFG_1
 220  */
 221 #define COEX_CFG1               0x0044
 222
 223 /*
 224  * COEX_CFG_2
 225  */
 226 #define COEX_CFG2               0x0048
 227 #define BT_COEX_CFG1            FIELD32(0xff000000)
 228 #define BT_COEX_CFG0            FIELD32(0x00ff0000)
 229 #define WL_COEX_CFG1            FIELD32(0x0000ff00)
 230 #define WL_COEX_CFG0            FIELD32(0x000000ff)
 231 /*
 232  * PLL_CTRL_CFG
 233  * PLL configuration register
 234  */
 235 #define PLL_CTRL                0x0050
 236 #define PLL_RESERVED_INPUT1     FIELD32(0x000000ff)
 237 #define PLL_RESERVED_INPUT2     FIELD32(0x0000ff00)
 238 #define PLL_CONTROL             FIELD32(0x00070000)
 239 #define PLL_LPF_R1              FIELD32(0x00080000)
 240 #define PLL_LPF_C1_CTRL         FIELD32(0x00300000)
 241 #define PLL_LPF_C2_CTRL         FIELD32(0x00c00000)
 242 #define PLL_CP_CURRENT_CTRL     FIELD32(0x03000000)
 243 #define PLL_PFD_DELAY_CTRL      FIELD32(0x0c000000)
 244 #define PLL_LOCK_CTRL           FIELD32(0x70000000)
 245 #define PLL_VBGBK_EN            FIELD32(0x80000000)
 246
 247
 248 /*
 249  * WLAN_CTRL_CFG
 250  * RT3290 wlan configuration
 251  */
 252 #define WLAN_FUN_CTRL                   0x0080
 253 #define WLAN_EN                         FIELD32(0x00000001)
 254 #define WLAN_CLK_EN                     FIELD32(0x00000002)
 255 #define WLAN_RSV1                       FIELD32(0x00000004)
 256 #define WLAN_RESET                      FIELD32(0x00000008)
 257 #define PCIE_APP0_CLK_REQ               FIELD32(0x00000010)
 258 #define FRC_WL_ANT_SET                  FIELD32(0x00000020)
 259 #define INV_TR_SW0                      FIELD32(0x00000040)
 260 #define WLAN_GPIO_IN_BIT0               FIELD32(0x00000100)
 261 #define WLAN_GPIO_IN_BIT1               FIELD32(0x00000200)
 262 #define WLAN_GPIO_IN_BIT2               FIELD32(0x00000400)
 263 #define WLAN_GPIO_IN_BIT3               FIELD32(0x00000800)
 264 #define WLAN_GPIO_IN_BIT4               FIELD32(0x00001000)
 265 #define WLAN_GPIO_IN_BIT5               FIELD32(0x00002000)
 266 #define WLAN_GPIO_IN_BIT6               FIELD32(0x00004000)
 267 #define WLAN_GPIO_IN_BIT7               FIELD32(0x00008000)
 268 #define WLAN_GPIO_IN_BIT_ALL            FIELD32(0x0000ff00)
 269 #define WLAN_GPIO_OUT_BIT0              FIELD32(0x00010000)
 270 #define WLAN_GPIO_OUT_BIT1              FIELD32(0x00020000)
 271 #define WLAN_GPIO_OUT_BIT2              FIELD32(0x00040000)
 272 #define WLAN_GPIO_OUT_BIT3              FIELD32(0x00050000)
 273 #define WLAN_GPIO_OUT_BIT4              FIELD32(0x00100000)
 274 #define WLAN_GPIO_OUT_BIT5              FIELD32(0x00200000)
 275 #define WLAN_GPIO_OUT_BIT6              FIELD32(0x00400000)
 276 #define WLAN_GPIO_OUT_BIT7              FIELD32(0x00800000)
 277 #define WLAN_GPIO_OUT_BIT_ALL           FIELD32(0x00ff0000)
 278 #define WLAN_GPIO_OUT_OE_BIT0           FIELD32(0x01000000)
 279 #define WLAN_GPIO_OUT_OE_BIT1           FIELD32(0x02000000)
 280 #define WLAN_GPIO_OUT_OE_BIT2           FIELD32(0x04000000)
 281 #define WLAN_GPIO_OUT_OE_BIT3           FIELD32(0x08000000)
 282 #define WLAN_GPIO_OUT_OE_BIT4           FIELD32(0x10000000)
 283 #define WLAN_GPIO_OUT_OE_BIT5           FIELD32(0x20000000)
 284 #define WLAN_GPIO_OUT_OE_BIT6           FIELD32(0x40000000)
 285 #define WLAN_GPIO_OUT_OE_BIT7           FIELD32(0x80000000)
 286 #define WLAN_GPIO_OUT_OE_BIT_ALL        FIELD32(0xff000000)
 287
 288 /*
 289  * AUX_CTRL: Aux/PCI-E related configuration
 290  */
 291 #define AUX_CTRL                        0x10c
 292 #define AUX_CTRL_WAKE_PCIE_EN           FIELD32(0x00000002)
 293 #define AUX_CTRL_FORCE_PCIE_CLK         FIELD32(0x00000400)
 294
 295 /*
 296  * OPT_14: Unknown register used by rt3xxx devices.
 297  */
 298 #define OPT_14_CSR                      0x0114
 299 #define OPT_14_CSR_BIT0                 FIELD32(0x00000001)
 300
 301 /*
 302  * INT_SOURCE_CSR: Interrupt source register.
 303  * Write one to clear corresponding bit.
 304  * TX_FIFO_STATUS: FIFO Statistics is full, sw should read TX_STA_FIFO
 305  */
 306 #define INT_SOURCE_CSR                  0x0200
 307 #define INT_SOURCE_CSR_RXDELAYINT       FIELD32(0x00000001)
 308 #define INT_SOURCE_CSR_TXDELAYINT       FIELD32(0x00000002)
 309 #define INT_SOURCE_CSR_RX_DONE          FIELD32(0x00000004)
 310 #define INT_SOURCE_CSR_AC0_DMA_DONE     FIELD32(0x00000008)
 311 #define INT_SOURCE_CSR_AC1_DMA_DONE     FIELD32(0x00000010)
 312 #define INT_SOURCE_CSR_AC2_DMA_DONE     FIELD32(0x00000020)
 313 #define INT_SOURCE_CSR_AC3_DMA_DONE     FIELD32(0x00000040)
 314 #define INT_SOURCE_CSR_HCCA_DMA_DONE    FIELD32(0x00000080)
 315 #define INT_SOURCE_CSR_MGMT_DMA_DONE    FIELD32(0x00000100)
 316 #define INT_SOURCE_CSR_MCU_COMMAND      FIELD32(0x00000200)
 317 #define INT_SOURCE_CSR_RXTX_COHERENT    FIELD32(0x00000400)
 318 #define INT_SOURCE_CSR_TBTT             FIELD32(0x00000800)
 319 #define INT_SOURCE_CSR_PRE_TBTT         FIELD32(0x00001000)
 320 #define INT_SOURCE_CSR_TX_FIFO_STATUS   FIELD32(0x00002000)
 321 #define INT_SOURCE_CSR_AUTO_WAKEUP      FIELD32(0x00004000)
 322 #define INT_SOURCE_CSR_GPTIMER          FIELD32(0x00008000)
 323 #define INT_SOURCE_CSR_RX_COHERENT      FIELD32(0x00010000)
 324 #define INT_SOURCE_CSR_TX_COHERENT      FIELD32(0x00020000)
 325
 326 /*
 327  * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
 328  */
 329 #define INT_MASK_CSR                    0x0204
 330 #define INT_MASK_CSR_RXDELAYINT         FIELD32(0x00000001)
 331 #define INT_MASK_CSR_TXDELAYINT         FIELD32(0x00000002)
 332 #define INT_MASK_CSR_RX_DONE            FIELD32(0x00000004)
 333 #define INT_MASK_CSR_AC0_DMA_DONE       FIELD32(0x00000008)
 334 #define INT_MASK_CSR_AC1_DMA_DONE       FIELD32(0x00000010)
 335 #define INT_MASK_CSR_AC2_DMA_DONE       FIELD32(0x00000020)
 336 #define INT_MASK_CSR_AC3_DMA_DONE       FIELD32(0x00000040)
 337 #define INT_MASK_CSR_HCCA_DMA_DONE      FIELD32(0x00000080)
 338 #define INT_MASK_CSR_MGMT_DMA_DONE      FIELD32(0x00000100)
 339 #define INT_MASK_CSR_MCU_COMMAND        FIELD32(0x00000200)
 340 #define INT_MASK_CSR_RXTX_COHERENT      FIELD32(0x00000400)
 341 #define INT_MASK_CSR_TBTT               FIELD32(0x00000800)
 342 #define INT_MASK_CSR_PRE_TBTT           FIELD32(0x00001000)
 343 #define INT_MASK_CSR_TX_FIFO_STATUS     FIELD32(0x00002000)
 344 #define INT_MASK_CSR_AUTO_WAKEUP        FIELD32(0x00004000)
 345 #define INT_MASK_CSR_GPTIMER            FIELD32(0x00008000)
 346 #define INT_MASK_CSR_RX_COHERENT        FIELD32(0x00010000)
 347 #define INT_MASK_CSR_TX_COHERENT        FIELD32(0x00020000)
 348
 349 /*
 350  * WPDMA_GLO_CFG
 351  */
 352 #define WPDMA_GLO_CFG                   0x0208
 353 #define WPDMA_GLO_CFG_ENABLE_TX_DMA     FIELD32(0x00000001)
 354 #define WPDMA_GLO_CFG_TX_DMA_BUSY       FIELD32(0x00000002)
 355 #define WPDMA_GLO_CFG_ENABLE_RX_DMA     FIELD32(0x00000004)
 356 #define WPDMA_GLO_CFG_RX_DMA_BUSY       FIELD32(0x00000008)
 357 #define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
 358 #define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
 359 #define WPDMA_GLO_CFG_BIG_ENDIAN        FIELD32(0x00000080)
 360 #define WPDMA_GLO_CFG_RX_HDR_SCATTER    FIELD32(0x0000ff00)
 361 #define WPDMA_GLO_CFG_HDR_SEG_LEN       FIELD32(0xffff0000)
 362
 363 /*
 364  * WPDMA_RST_IDX
 365  */
 366 #define WPDMA_RST_IDX                   0x020c
 367 #define WPDMA_RST_IDX_DTX_IDX0          FIELD32(0x00000001)
 368 #define WPDMA_RST_IDX_DTX_IDX1          FIELD32(0x00000002)
 369 #define WPDMA_RST_IDX_DTX_IDX2          FIELD32(0x00000004)
 370 #define WPDMA_RST_IDX_DTX_IDX3          FIELD32(0x00000008)
 371 #define WPDMA_RST_IDX_DTX_IDX4          FIELD32(0x00000010)
 372 #define WPDMA_RST_IDX_DTX_IDX5          FIELD32(0x00000020)
 373 #define WPDMA_RST_IDX_DRX_IDX0          FIELD32(0x00010000)
 374
 375 /*
 376  * DELAY_INT_CFG
 377  */
 378 #define DELAY_INT_CFG                   0x0210
 379 #define DELAY_INT_CFG_RXMAX_PTIME       FIELD32(0x000000ff)
 380 #define DELAY_INT_CFG_RXMAX_PINT        FIELD32(0x00007f00)
 381 #define DELAY_INT_CFG_RXDLY_INT_EN      FIELD32(0x00008000)
 382 #define DELAY_INT_CFG_TXMAX_PTIME       FIELD32(0x00ff0000)
 383 #define DELAY_INT_CFG_TXMAX_PINT        FIELD32(0x7f000000)
 384 #define DELAY_INT_CFG_TXDLY_INT_EN      FIELD32(0x80000000)
 385
 386 /*
 387  * WMM_AIFSN_CFG: Aifsn for each EDCA AC
 388  * AIFSN0: AC_VO
 389  * AIFSN1: AC_VI
 390  * AIFSN2: AC_BE
 391  * AIFSN3: AC_BK
 392  */
 393 #define WMM_AIFSN_CFG                   0x0214
 394 #define WMM_AIFSN_CFG_AIFSN0            FIELD32(0x0000000f)
 395 #define WMM_AIFSN_CFG_AIFSN1            FIELD32(0x000000f0)
 396 #define WMM_AIFSN_CFG_AIFSN2            FIELD32(0x00000f00)
 397 #define WMM_AIFSN_CFG_AIFSN3            FIELD32(0x0000f000)
 398
 399 /*
 400  * WMM_CWMIN_CSR: CWmin for each EDCA AC
 401  * CWMIN0: AC_VO
 402  * CWMIN1: AC_VI
 403  * CWMIN2: AC_BE
 404  * CWMIN3: AC_BK
 405  */
 406 #define WMM_CWMIN_CFG                   0x0218
 407 #define WMM_CWMIN_CFG_CWMIN0            FIELD32(0x0000000f)
 408 #define WMM_CWMIN_CFG_CWMIN1            FIELD32(0x000000f0)
 409 #define WMM_CWMIN_CFG_CWMIN2            FIELD32(0x00000f00)
 410 #define WMM_CWMIN_CFG_CWMIN3            FIELD32(0x0000f000)
 411
 412 /*
 413  * WMM_CWMAX_CSR: CWmax for each EDCA AC
 414  * CWMAX0: AC_VO
 415  * CWMAX1: AC_VI
 416  * CWMAX2: AC_BE
 417  * CWMAX3: AC_BK
 418  */
 419 #define WMM_CWMAX_CFG                   0x021c
 420 #define WMM_CWMAX_CFG_CWMAX0            FIELD32(0x0000000f)
 421 #define WMM_CWMAX_CFG_CWMAX1            FIELD32(0x000000f0)
 422 #define WMM_CWMAX_CFG_CWMAX2            FIELD32(0x00000f00)
 423 #define WMM_CWMAX_CFG_CWMAX3            FIELD32(0x0000f000)
 424
 425 /*
 426  * AC_TXOP0: AC_VO/AC_VI TXOP register
 427  * AC0TXOP: AC_VO in unit of 32us
 428  * AC1TXOP: AC_VI in unit of 32us
 429  */
 430 #define WMM_TXOP0_CFG                   0x0220
 431 #define WMM_TXOP0_CFG_AC0TXOP           FIELD32(0x0000ffff)
 432 #define WMM_TXOP0_CFG_AC1TXOP           FIELD32(0xffff0000)
 433
 434 /*
 435  * AC_TXOP1: AC_BE/AC_BK TXOP register
 436  * AC2TXOP: AC_BE in unit of 32us
 437  * AC3TXOP: AC_BK in unit of 32us
 438  */
 439 #define WMM_TXOP1_CFG                   0x0224
 440 #define WMM_TXOP1_CFG_AC2TXOP           FIELD32(0x0000ffff)
 441 #define WMM_TXOP1_CFG_AC3TXOP           FIELD32(0xffff0000)
 442
 443 /*
 444  * GPIO_CTRL:
 445  *      GPIO_CTRL_VALx: GPIO value
 446  *      GPIO_CTRL_DIRx: GPIO direction: 0 = output; 1 = input
 447  */
 448 #define GPIO_CTRL                       0x0228
 449 #define GPIO_CTRL_VAL0                  FIELD32(0x00000001)
 450 #define GPIO_CTRL_VAL1                  FIELD32(0x00000002)
 451 #define GPIO_CTRL_VAL2                  FIELD32(0x00000004)
 452 #define GPIO_CTRL_VAL3                  FIELD32(0x00000008)
 453 #define GPIO_CTRL_VAL4                  FIELD32(0x00000010)
 454 #define GPIO_CTRL_VAL5                  FIELD32(0x00000020)
 455 #define GPIO_CTRL_VAL6                  FIELD32(0x00000040)
 456 #define GPIO_CTRL_VAL7                  FIELD32(0x00000080)
 457 #define GPIO_CTRL_DIR0                  FIELD32(0x00000100)
 458 #define GPIO_CTRL_DIR1                  FIELD32(0x00000200)
 459 #define GPIO_CTRL_DIR2                  FIELD32(0x00000400)
 460 #define GPIO_CTRL_DIR3                  FIELD32(0x00000800)
 461 #define GPIO_CTRL_DIR4                  FIELD32(0x00001000)
 462 #define GPIO_CTRL_DIR5                  FIELD32(0x00002000)
 463 #define GPIO_CTRL_DIR6                  FIELD32(0x00004000)
 464 #define GPIO_CTRL_DIR7                  FIELD32(0x00008000)
 465 #define GPIO_CTRL_VAL8                  FIELD32(0x00010000)
 466 #define GPIO_CTRL_VAL9                  FIELD32(0x00020000)
 467 #define GPIO_CTRL_VAL10                 FIELD32(0x00040000)
 468 #define GPIO_CTRL_DIR8                  FIELD32(0x01000000)
 469 #define GPIO_CTRL_DIR9                  FIELD32(0x02000000)
 470 #define GPIO_CTRL_DIR10                 FIELD32(0x04000000)
 471
 472 /*
 473  * MCU_CMD_CFG
 474  */
 475 #define MCU_CMD_CFG                     0x022c
 476
 477 /*
 478  * AC_VO register offsets
 479  */
 480 #define TX_BASE_PTR0                    0x0230
 481 #define TX_MAX_CNT0                     0x0234
 482 #define TX_CTX_IDX0                     0x0238
 483 #define TX_DTX_IDX0                     0x023c
 484
 485 /*
 486  * AC_VI register offsets
 487  */
 488 #define TX_BASE_PTR1                    0x0240
 489 #define TX_MAX_CNT1                     0x0244
 490 #define TX_CTX_IDX1                     0x0248
 491 #define TX_DTX_IDX1                     0x024c
 492
 493 /*
 494  * AC_BE register offsets
 495  */
 496 #define TX_BASE_PTR2                    0x0250
 497 #define TX_MAX_CNT2                     0x0254
 498 #define TX_CTX_IDX2                     0x0258
 499 #define TX_DTX_IDX2                     0x025c
 500
 501 /*
 502  * AC_BK register offsets
 503  */
 504 #define TX_BASE_PTR3                    0x0260
 505 #define TX_MAX_CNT3                     0x0264
 506 #define TX_CTX_IDX3                     0x0268
 507 #define TX_DTX_IDX3                     0x026c
 508
 509 /*
 510  * HCCA register offsets
 511  */
 512 #define TX_BASE_PTR4                    0x0270
 513 #define TX_MAX_CNT4                     0x0274
 514 #define TX_CTX_IDX4                     0x0278
 515 #define TX_DTX_IDX4                     0x027c
 516
 517 /*
 518  * MGMT register offsets
 519  */
 520 #define TX_BASE_PTR5                    0x0280
 521 #define TX_MAX_CNT5                     0x0284
 522 #define TX_CTX_IDX5                     0x0288
 523 #define TX_DTX_IDX5                     0x028c
 524
 525 /*
 526  * RX register offsets
 527  */
 528 #define RX_BASE_PTR                     0x0290
 529 #define RX_MAX_CNT                      0x0294
 530 #define RX_CRX_IDX                      0x0298
 531 #define RX_DRX_IDX                      0x029c
 532
 533 /*
 534  * USB_DMA_CFG
 535  * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
 536  * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
 537  * PHY_CLEAR: phy watch dog enable.
 538  * TX_CLEAR: Clear USB DMA TX path.
 539  * TXOP_HALT: Halt TXOP count down when TX buffer is full.
 540  * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
 541  * RX_BULK_EN: Enable USB DMA Rx.
 542  * TX_BULK_EN: Enable USB DMA Tx.
 543  * EP_OUT_VALID: OUT endpoint data valid.
 544  * RX_BUSY: USB DMA RX FSM busy.
 545  * TX_BUSY: USB DMA TX FSM busy.
 546  */
 547 #define USB_DMA_CFG                     0x02a0
 548 #define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
 549 #define USB_DMA_CFG_RX_BULK_AGG_LIMIT   FIELD32(0x0000ff00)
 550 #define USB_DMA_CFG_PHY_CLEAR           FIELD32(0x00010000)
 551 #define USB_DMA_CFG_TX_CLEAR            FIELD32(0x00080000)
 552 #define USB_DMA_CFG_TXOP_HALT           FIELD32(0x00100000)
 553 #define USB_DMA_CFG_RX_BULK_AGG_EN      FIELD32(0x00200000)
 554 #define USB_DMA_CFG_RX_BULK_EN          FIELD32(0x00400000)
 555 #define USB_DMA_CFG_TX_BULK_EN          FIELD32(0x00800000)
 556 #define USB_DMA_CFG_EP_OUT_VALID        FIELD32(0x3f000000)
 557 #define USB_DMA_CFG_RX_BUSY             FIELD32(0x40000000)
 558 #define USB_DMA_CFG_TX_BUSY             FIELD32(0x80000000)
 559
 560 /*
 561  * US_CYC_CNT
 562  * BT_MODE_EN: Bluetooth mode enable
 563  * CLOCK CYCLE: Clock cycle count in 1us.
 564  * PCI:0x21, PCIE:0x7d, USB:0x1e
 565  */
 566 #define US_CYC_CNT                      0x02a4
 567 #define US_CYC_CNT_BT_MODE_EN           FIELD32(0x00000100)
 568 #define US_CYC_CNT_CLOCK_CYCLE          FIELD32(0x000000ff)
 569
 570 /*
 571  * PBF_SYS_CTRL
 572  * HOST_RAM_WRITE: enable Host program ram write selection
 573  */
 574 #define PBF_SYS_CTRL                    0x0400
 575 #define PBF_SYS_CTRL_READY              FIELD32(0x00000080)
 576 #define PBF_SYS_CTRL_HOST_RAM_WRITE     FIELD32(0x00010000)
 577
 578 /*
 579  * HOST-MCU shared memory
 580  */
 581 #define HOST_CMD_CSR                    0x0404
 582 #define HOST_CMD_CSR_HOST_COMMAND       FIELD32(0x000000ff)
 583
 584 /*
 585  * PBF registers
 586  * Most are for debug. Driver doesn't touch PBF register.
 587  */
 588 #define PBF_CFG                         0x0408
 589 #define PBF_MAX_PCNT                    0x040c
 590 #define PBF_CTRL                        0x0410
 591 #define PBF_INT_STA                     0x0414
 592 #define PBF_INT_ENA                     0x0418
 593
 594 /*
 595  * BCN_OFFSET0:
 596  */
 597 #define BCN_OFFSET0                     0x042c
 598 #define BCN_OFFSET0_BCN0                FIELD32(0x000000ff)
 599 #define BCN_OFFSET0_BCN1                FIELD32(0x0000ff00)
 600 #define BCN_OFFSET0_BCN2                FIELD32(0x00ff0000)
 601 #define BCN_OFFSET0_BCN3                FIELD32(0xff000000)
 602
 603 /*
 604  * BCN_OFFSET1:
 605  */
 606 #define BCN_OFFSET1                     0x0430
 607 #define BCN_OFFSET1_BCN4                FIELD32(0x000000ff)
 608 #define BCN_OFFSET1_BCN5                FIELD32(0x0000ff00)
 609 #define BCN_OFFSET1_BCN6                FIELD32(0x00ff0000)
 610 #define BCN_OFFSET1_BCN7                FIELD32(0xff000000)
 611
 612 /*
 613  * TXRXQ_PCNT: PBF register
 614  * PCNT_TX0Q: Page count for TX hardware queue 0
 615  * PCNT_TX1Q: Page count for TX hardware queue 1
 616  * PCNT_TX2Q: Page count for TX hardware queue 2
 617  * PCNT_RX0Q: Page count for RX hardware queue
 618  */
 619 #define TXRXQ_PCNT                      0x0438
 620 #define TXRXQ_PCNT_TX0Q                 FIELD32(0x000000ff)
 621 #define TXRXQ_PCNT_TX1Q                 FIELD32(0x0000ff00)
 622 #define TXRXQ_PCNT_TX2Q                 FIELD32(0x00ff0000)
 623 #define TXRXQ_PCNT_RX0Q                 FIELD32(0xff000000)
 624
 625 /*
 626  * PBF register
 627  * Debug. Driver doesn't touch PBF register.
 628  */
 629 #define PBF_DBG                         0x043c
 630
 631 /*
 632  * RF registers
 633  */
 634 #define RF_CSR_CFG                      0x0500
 635 #define RF_CSR_CFG_DATA                 FIELD32(0x000000ff)
 636 #define RF_CSR_CFG_REGNUM               FIELD32(0x00003f00)
 637 #define RF_CSR_CFG_WRITE                FIELD32(0x00010000)
 638 #define RF_CSR_CFG_BUSY                 FIELD32(0x00020000)
 639
 640 /*
 641  * EFUSE_CSR: RT30x0 EEPROM
 642  */
 643 #define EFUSE_CTRL                      0x0580
 644 #define EFUSE_CTRL_ADDRESS_IN           FIELD32(0x03fe0000)
 645 #define EFUSE_CTRL_MODE                 FIELD32(0x000000c0)
 646 #define EFUSE_CTRL_KICK                 FIELD32(0x40000000)
 647 #define EFUSE_CTRL_PRESENT              FIELD32(0x80000000)
 648
 649 /*
 650  * EFUSE_DATA0
 651  */
 652 #define EFUSE_DATA0                     0x0590
 653
 654 /*
 655  * EFUSE_DATA1
 656  */
 657 #define EFUSE_DATA1                     0x0594
 658
 659 /*
 660  * EFUSE_DATA2
 661  */
 662 #define EFUSE_DATA2                     0x0598
 663
 664 /*
 665  * EFUSE_DATA3
 666  */
 667 #define EFUSE_DATA3                     0x059c
 668
 669 /*
 670  * LDO_CFG0
 671  */
 672 #define LDO_CFG0                        0x05d4
 673 #define LDO_CFG0_DELAY3                 FIELD32(0x000000ff)
 674 #define LDO_CFG0_DELAY2                 FIELD32(0x0000ff00)
 675 #define LDO_CFG0_DELAY1                 FIELD32(0x00ff0000)
 676 #define LDO_CFG0_BGSEL                  FIELD32(0x03000000)
 677 #define LDO_CFG0_LDO_CORE_VLEVEL        FIELD32(0x1c000000)
 678 #define LD0_CFG0_LDO25_LEVEL            FIELD32(0x60000000)
 679 #define LDO_CFG0_LDO25_LARGEA           FIELD32(0x80000000)
 680
 681 /*
 682  * GPIO_SWITCH
 683  */
 684 #define GPIO_SWITCH                     0x05dc
 685 #define GPIO_SWITCH_0                   FIELD32(0x00000001)
 686 #define GPIO_SWITCH_1                   FIELD32(0x00000002)
 687 #define GPIO_SWITCH_2                   FIELD32(0x00000004)
 688 #define GPIO_SWITCH_3                   FIELD32(0x00000008)
 689 #define GPIO_SWITCH_4                   FIELD32(0x00000010)
 690 #define GPIO_SWITCH_5                   FIELD32(0x00000020)
 691 #define GPIO_SWITCH_6                   FIELD32(0x00000040)
 692 #define GPIO_SWITCH_7                   FIELD32(0x00000080)
 693
 694 /*
 695  * FIXME: where the DEBUG_INDEX name come from?
 696  */
 697 #define MAC_DEBUG_INDEX                 0x05e8
 698 #define MAC_DEBUG_INDEX_XTAL            FIELD32(0x80000000)
 699
 700 /*
 701  * MAC Control/Status Registers(CSR).
 702  * Some values are set in TU, whereas 1 TU == 1024 us.
 703  */
 704
 705 /*
 706  * MAC_CSR0: ASIC revision number.
 707  * ASIC_REV: 0
 708  * ASIC_VER: 2860 or 2870
 709  */
 710 #define MAC_CSR0                        0x1000
 711 #define MAC_CSR0_REVISION               FIELD32(0x0000ffff)
 712 #define MAC_CSR0_CHIPSET                FIELD32(0xffff0000)
 713
 714 /*
 715  * MAC_SYS_CTRL:
 716  */
 717 #define MAC_SYS_CTRL                    0x1004
 718 #define MAC_SYS_CTRL_RESET_CSR          FIELD32(0x00000001)
 719 #define MAC_SYS_CTRL_RESET_BBP          FIELD32(0x00000002)
 720 #define MAC_SYS_CTRL_ENABLE_TX          FIELD32(0x00000004)
 721 #define MAC_SYS_CTRL_ENABLE_RX          FIELD32(0x00000008)
 722 #define MAC_SYS_CTRL_CONTINUOUS_TX      FIELD32(0x00000010)
 723 #define MAC_SYS_CTRL_LOOPBACK           FIELD32(0x00000020)
 724 #define MAC_SYS_CTRL_WLAN_HALT          FIELD32(0x00000040)
 725 #define MAC_SYS_CTRL_RX_TIMESTAMP       FIELD32(0x00000080)
 726
 727 /*
 728  * MAC_ADDR_DW0: STA MAC register 0
 729  */
 730 #define MAC_ADDR_DW0                    0x1008
 731 #define MAC_ADDR_DW0_BYTE0              FIELD32(0x000000ff)
 732 #define MAC_ADDR_DW0_BYTE1              FIELD32(0x0000ff00)
 733 #define MAC_ADDR_DW0_BYTE2              FIELD32(0x00ff0000)
 734 #define MAC_ADDR_DW0_BYTE3              FIELD32(0xff000000)
 735
 736 /*
 737  * MAC_ADDR_DW1: STA MAC register 1
 738  * UNICAST_TO_ME_MASK:
 739  * Used to mask off bits from byte 5 of the MAC address
 740  * to determine the UNICAST_TO_ME bit for RX frames.
 741  * The full mask is complemented by BSS_ID_MASK:
 742  *    MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
 743  */
 744 #define MAC_ADDR_DW1                    0x100c
 745 #define MAC_ADDR_DW1_BYTE4              FIELD32(0x000000ff)
 746 #define MAC_ADDR_DW1_BYTE5              FIELD32(0x0000ff00)
 747 #define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
 748
 749 /*
 750  * MAC_BSSID_DW0: BSSID register 0
 751  */
 752 #define MAC_BSSID_DW0                   0x1010
 753 #define MAC_BSSID_DW0_BYTE0             FIELD32(0x000000ff)
 754 #define MAC_BSSID_DW0_BYTE1             FIELD32(0x0000ff00)
 755 #define MAC_BSSID_DW0_BYTE2             FIELD32(0x00ff0000)
 756 #define MAC_BSSID_DW0_BYTE3             FIELD32(0xff000000)
 757
 758 /*
 759  * MAC_BSSID_DW1: BSSID register 1
 760  * BSS_ID_MASK:
 761  *     0: 1-BSSID mode (BSS index = 0)
 762  *     1: 2-BSSID mode (BSS index: Byte5, bit 0)
 763  *     2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
 764  *     3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
 765  * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
 766  * BSSID. This will make sure that those bits will be ignored
 767  * when determining the MY_BSS of RX frames.
 768  */
 769 #define MAC_BSSID_DW1                   0x1014
 770 #define MAC_BSSID_DW1_BYTE4             FIELD32(0x000000ff)
 771 #define MAC_BSSID_DW1_BYTE5             FIELD32(0x0000ff00)
 772 #define MAC_BSSID_DW1_BSS_ID_MASK       FIELD32(0x00030000)
 773 #define MAC_BSSID_DW1_BSS_BCN_NUM       FIELD32(0x001c0000)
 774
 775 /*
 776  * MAX_LEN_CFG: Maximum frame length register.
 777  * MAX_MPDU: rt2860b max 16k bytes
 778  * MAX_PSDU: Maximum PSDU length
 779  *      (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
 780  */
 781 #define MAX_LEN_CFG                     0x1018
 782 #define MAX_LEN_CFG_MAX_MPDU            FIELD32(0x00000fff)
 783 #define MAX_LEN_CFG_MAX_PSDU            FIELD32(0x00003000)
 784 #define MAX_LEN_CFG_MIN_PSDU            FIELD32(0x0000c000)
 785 #define MAX_LEN_CFG_MIN_MPDU            FIELD32(0x000f0000)
 786
 787 /*
 788  * BBP_CSR_CFG: BBP serial control register
 789  * VALUE: Register value to program into BBP
 790  * REG_NUM: Selected BBP register
 791  * READ_CONTROL: 0 write BBP, 1 read BBP
 792  * BUSY: ASIC is busy executing BBP commands
 793  * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
 794  * BBP_RW_MODE: 0 serial, 1 parallel
 795  */
 796 #define BBP_CSR_CFG                     0x101c
 797 #define BBP_CSR_CFG_VALUE               FIELD32(0x000000ff)
 798 #define BBP_CSR_CFG_REGNUM              FIELD32(0x0000ff00)
 799 #define BBP_CSR_CFG_READ_CONTROL        FIELD32(0x00010000)
 800 #define BBP_CSR_CFG_BUSY                FIELD32(0x00020000)
 801 #define BBP_CSR_CFG_BBP_PAR_DUR         FIELD32(0x00040000)
 802 #define BBP_CSR_CFG_BBP_RW_MODE         FIELD32(0x00080000)
 803
 804 /*
 805  * RF_CSR_CFG0: RF control register
 806  * REGID_AND_VALUE: Register value to program into RF
 807  * BITWIDTH: Selected RF register
 808  * STANDBYMODE: 0 high when standby, 1 low when standby
 809  * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
 810  * BUSY: ASIC is busy executing RF commands
 811  */
 812 #define RF_CSR_CFG0                     0x1020
 813 #define RF_CSR_CFG0_REGID_AND_VALUE     FIELD32(0x00ffffff)
 814 #define RF_CSR_CFG0_BITWIDTH            FIELD32(0x1f000000)
 815 #define RF_CSR_CFG0_REG_VALUE_BW        FIELD32(0x1fffffff)
 816 #define RF_CSR_CFG0_STANDBYMODE         FIELD32(0x20000000)
 817 #define RF_CSR_CFG0_SEL                 FIELD32(0x40000000)
 818 #define RF_CSR_CFG0_BUSY                FIELD32(0x80000000)
 819
 820 /*
 821  * RF_CSR_CFG1: RF control register
 822  * REGID_AND_VALUE: Register value to program into RF
 823  * RFGAP: Gap between BB_CONTROL_RF and RF_LE
 824  *        0: 3 system clock cycle (37.5usec)
 825  *        1: 5 system clock cycle (62.5usec)
 826  */
 827 #define RF_CSR_CFG1                     0x1024
 828 #define RF_CSR_CFG1_REGID_AND_VALUE     FIELD32(0x00ffffff)
 829 #define RF_CSR_CFG1_RFGAP               FIELD32(0x1f000000)
 830
 831 /*
 832  * RF_CSR_CFG2: RF control register
 833  * VALUE: Register value to program into RF
 834  */
 835 #define RF_CSR_CFG2                     0x1028
 836 #define RF_CSR_CFG2_VALUE               FIELD32(0x00ffffff)
 837
 838 /*
 839  * LED_CFG: LED control
 840  * ON_PERIOD: LED active time (ms) during TX (only used for LED mode 1)
 841  * OFF_PERIOD: LED inactive time (ms) during TX (only used for LED mode 1)
 842  * SLOW_BLINK_PERIOD: LED blink interval in seconds (only used for LED mode 2)
 843  * color LED's:
 844  *   0: off
 845  *   1: blinking upon TX2
 846  *   2: periodic slow blinking
 847  *   3: always on
 848  * LED polarity:
 849  *   0: active low
 850  *   1: active high
 851  */
 852 #define LED_CFG                         0x102c
 853 #define LED_CFG_ON_PERIOD               FIELD32(0x000000ff)
 854 #define LED_CFG_OFF_PERIOD              FIELD32(0x0000ff00)
 855 #define LED_CFG_SLOW_BLINK_PERIOD       FIELD32(0x003f0000)
 856 #define LED_CFG_R_LED_MODE              FIELD32(0x03000000)
 857 #define LED_CFG_G_LED_MODE              FIELD32(0x0c000000)
 858 #define LED_CFG_Y_LED_MODE              FIELD32(0x30000000)
 859 #define LED_CFG_LED_POLAR               FIELD32(0x40000000)
 860
 861 /*
 862  * AMPDU_BA_WINSIZE: Force BlockAck window size
 863  * FORCE_WINSIZE_ENABLE:
 864  *   0: Disable forcing of BlockAck window size
 865  *   1: Enable forcing of BlockAck window size, overwrites values BlockAck
 866  *      window size values in the TXWI
 867  * FORCE_WINSIZE: BlockAck window size
 868  */
 869 #define AMPDU_BA_WINSIZE                0x1040
 870 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE FIELD32(0x00000020)
 871 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE  FIELD32(0x0000001f)
 872
 873 /*
 874  * XIFS_TIME_CFG: MAC timing
 875  * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
 876  * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
 877  * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
 878  *      when MAC doesn't reference BBP signal BBRXEND
 879  * EIFS: unit 1us
 880  * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
 881  *
 882  */
 883 #define XIFS_TIME_CFG                   0x1100
 884 #define XIFS_TIME_CFG_CCKM_SIFS_TIME    FIELD32(0x000000ff)
 885 #define XIFS_TIME_CFG_OFDM_SIFS_TIME    FIELD32(0x0000ff00)
 886 #define XIFS_TIME_CFG_OFDM_XIFS_TIME    FIELD32(0x000f0000)
 887 #define XIFS_TIME_CFG_EIFS              FIELD32(0x1ff00000)
 888 #define XIFS_TIME_CFG_BB_RXEND_ENABLE   FIELD32(0x20000000)
 889
 890 /*
 891  * BKOFF_SLOT_CFG:
 892  */
 893 #define BKOFF_SLOT_CFG                  0x1104
 894 #define BKOFF_SLOT_CFG_SLOT_TIME        FIELD32(0x000000ff)
 895 #define BKOFF_SLOT_CFG_CC_DELAY_TIME    FIELD32(0x0000ff00)
 896
 897 /*
 898  * NAV_TIME_CFG:
 899  */
 900 #define NAV_TIME_CFG                    0x1108
 901 #define NAV_TIME_CFG_SIFS               FIELD32(0x000000ff)
 902 #define NAV_TIME_CFG_SLOT_TIME          FIELD32(0x0000ff00)
 903 #define NAV_TIME_CFG_EIFS               FIELD32(0x01ff0000)
 904 #define NAV_TIME_ZERO_SIFS              FIELD32(0x02000000)
 905
 906 /*
 907  * CH_TIME_CFG: count as channel busy
 908  * EIFS_BUSY: Count EIFS as channel busy
 909  * NAV_BUSY: Count NAS as channel busy
 910  * RX_BUSY: Count RX as channel busy
 911  * TX_BUSY: Count TX as channel busy
 912  * TMR_EN: Enable channel statistics timer
 913  */
 914 #define CH_TIME_CFG                     0x110c
 915 #define CH_TIME_CFG_EIFS_BUSY           FIELD32(0x00000010)
 916 #define CH_TIME_CFG_NAV_BUSY            FIELD32(0x00000008)
 917 #define CH_TIME_CFG_RX_BUSY             FIELD32(0x00000004)
 918 #define CH_TIME_CFG_TX_BUSY             FIELD32(0x00000002)
 919 #define CH_TIME_CFG_TMR_EN              FIELD32(0x00000001)
 920
 921 /*
 922  * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
 923  */
 924 #define PBF_LIFE_TIMER                  0x1110
 925
 926 /*
 927  * BCN_TIME_CFG:
 928  * BEACON_INTERVAL: in unit of 1/16 TU
 929  * TSF_TICKING: Enable TSF auto counting
 930  * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
 931  * BEACON_GEN: Enable beacon generator
 932  */
 933 #define BCN_TIME_CFG                    0x1114
 934 #define BCN_TIME_CFG_BEACON_INTERVAL    FIELD32(0x0000ffff)
 935 #define BCN_TIME_CFG_TSF_TICKING        FIELD32(0x00010000)
 936 #define BCN_TIME_CFG_TSF_SYNC           FIELD32(0x00060000)
 937 #define BCN_TIME_CFG_TBTT_ENABLE        FIELD32(0x00080000)
 938 #define BCN_TIME_CFG_BEACON_GEN         FIELD32(0x00100000)
 939 #define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
 940
 941 /*
 942  * TBTT_SYNC_CFG:
 943  * BCN_AIFSN: Beacon AIFSN after TBTT interrupt in slots
 944  * BCN_CWMIN: Beacon CWMin after TBTT interrupt in slots
 945  */
 946 #define TBTT_SYNC_CFG                   0x1118
 947 #define TBTT_SYNC_CFG_TBTT_ADJUST       FIELD32(0x000000ff)
 948 #define TBTT_SYNC_CFG_BCN_EXP_WIN       FIELD32(0x0000ff00)
 949 #define TBTT_SYNC_CFG_BCN_AIFSN         FIELD32(0x000f0000)
 950 #define TBTT_SYNC_CFG_BCN_CWMIN         FIELD32(0x00f00000)
 951
 952 /*
 953  * TSF_TIMER_DW0: Local lsb TSF timer, read-only
 954  */
 955 #define TSF_TIMER_DW0                   0x111c
 956 #define TSF_TIMER_DW0_LOW_WORD          FIELD32(0xffffffff)
 957
 958 /*
 959  * TSF_TIMER_DW1: Local msb TSF timer, read-only
 960  */
 961 #define TSF_TIMER_DW1                   0x1120
 962 #define TSF_TIMER_DW1_HIGH_WORD         FIELD32(0xffffffff)
 963
 964 /*
 965  * TBTT_TIMER: TImer remains till next TBTT, read-only
 966  */
 967 #define TBTT_TIMER                      0x1124
 968
 969 /*
 970  * INT_TIMER_CFG: timer configuration
 971  * PRE_TBTT_TIMER: leadtime to tbtt for pretbtt interrupt in units of 1/16 TU
 972  * GP_TIMER: period of general purpose timer in units of 1/16 TU
 973  */
 974 #define INT_TIMER_CFG                   0x1128
 975 #define INT_TIMER_CFG_PRE_TBTT_TIMER    FIELD32(0x0000ffff)
 976 #define INT_TIMER_CFG_GP_TIMER          FIELD32(0xffff0000)
 977
 978 /*
 979  * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
 980  */
 981 #define INT_TIMER_EN                    0x112c
 982 #define INT_TIMER_EN_PRE_TBTT_TIMER     FIELD32(0x00000001)
 983 #define INT_TIMER_EN_GP_TIMER           FIELD32(0x00000002)
 984
 985 /*
 986  * CH_IDLE_STA: channel idle time (in us)
 987  */
 988 #define CH_IDLE_STA                     0x1130
 989
 990 /*
 991  * CH_BUSY_STA: channel busy time on primary channel (in us)
 992  */
 993 #define CH_BUSY_STA                     0x1134
 994
 995 /*
 996  * CH_BUSY_STA_SEC: channel busy time on secondary channel in HT40 mode (in us)
 997  */
 998 #define CH_BUSY_STA_SEC                 0x1138
 999
1000 /*
1001  * MAC_STATUS_CFG:
1002  * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
1003  *      if 1 or higher one of the 2 registers is busy.
1004  */
1005 #define MAC_STATUS_CFG                  0x1200
1006 #define MAC_STATUS_CFG_BBP_RF_BUSY      FIELD32(0x00000003)
1007
1008 /*
1009  * PWR_PIN_CFG:
1010  */
1011 #define PWR_PIN_CFG                     0x1204
1012
1013 /*
1014  * AUTOWAKEUP_CFG: Manual power control / status register
1015  * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
1016  * AUTOWAKE: 0:sleep, 1:awake
1017  */
1018 #define AUTOWAKEUP_CFG                  0x1208
1019 #define AUTOWAKEUP_CFG_AUTO_LEAD_TIME   FIELD32(0x000000ff)
1020 #define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
1021 #define AUTOWAKEUP_CFG_AUTOWAKE         FIELD32(0x00008000)
1022
1023 /*
1024  * EDCA_AC0_CFG:
1025  */
1026 #define EDCA_AC0_CFG                    0x1300
1027 #define EDCA_AC0_CFG_TX_OP              FIELD32(0x000000ff)
1028 #define EDCA_AC0_CFG_AIFSN              FIELD32(0x00000f00)
1029 #define EDCA_AC0_CFG_CWMIN              FIELD32(0x0000f000)
1030 #define EDCA_AC0_CFG_CWMAX              FIELD32(0x000f0000)
1031
1032 /*
1033  * EDCA_AC1_CFG:
1034  */
1035 #define EDCA_AC1_CFG                    0x1304
1036 #define EDCA_AC1_CFG_TX_OP              FIELD32(0x000000ff)
1037 #define EDCA_AC1_CFG_AIFSN              FIELD32(0x00000f00)
1038 #define EDCA_AC1_CFG_CWMIN              FIELD32(0x0000f000)
1039 #define EDCA_AC1_CFG_CWMAX              FIELD32(0x000f0000)
1040
1041 /*
1042  * EDCA_AC2_CFG:
1043  */
1044 #define EDCA_AC2_CFG                    0x1308
1045 #define EDCA_AC2_CFG_TX_OP              FIELD32(0x000000ff)
1046 #define EDCA_AC2_CFG_AIFSN              FIELD32(0x00000f00)
1047 #define EDCA_AC2_CFG_CWMIN              FIELD32(0x0000f000)
1048 #define EDCA_AC2_CFG_CWMAX              FIELD32(0x000f0000)
1049
1050 /*
1051  * EDCA_AC3_CFG:
1052  */
1053 #define EDCA_AC3_CFG                    0x130c
1054 #define EDCA_AC3_CFG_TX_OP              FIELD32(0x000000ff)
1055 #define EDCA_AC3_CFG_AIFSN              FIELD32(0x00000f00)
1056 #define EDCA_AC3_CFG_CWMIN              FIELD32(0x0000f000)
1057 #define EDCA_AC3_CFG_CWMAX              FIELD32(0x000f0000)
1058
1059 /*
1060  * EDCA_TID_AC_MAP:
1061  */
1062 #define EDCA_TID_AC_MAP                 0x1310
1063
1064 /*
1065  * TX_PWR_CFG:
1066  */
1067 #define TX_PWR_CFG_RATE0                FIELD32(0x0000000f)
1068 #define TX_PWR_CFG_RATE1                FIELD32(0x000000f0)
1069 #define TX_PWR_CFG_RATE2                FIELD32(0x00000f00)
1070 #define TX_PWR_CFG_RATE3                FIELD32(0x0000f000)
1071 #define TX_PWR_CFG_RATE4                FIELD32(0x000f0000)
1072 #define TX_PWR_CFG_RATE5                FIELD32(0x00f00000)
1073 #define TX_PWR_CFG_RATE6                FIELD32(0x0f000000)
1074 #define TX_PWR_CFG_RATE7                FIELD32(0xf0000000)
1075
1076 /*
1077  * TX_PWR_CFG_0:
1078  */
1079 #define TX_PWR_CFG_0                    0x1314
1080 #define TX_PWR_CFG_0_1MBS               FIELD32(0x0000000f)
1081 #define TX_PWR_CFG_0_2MBS               FIELD32(0x000000f0)
1082 #define TX_PWR_CFG_0_55MBS              FIELD32(0x00000f00)
1083 #define TX_PWR_CFG_0_11MBS              FIELD32(0x0000f000)
1084 #define TX_PWR_CFG_0_6MBS               FIELD32(0x000f0000)
1085 #define TX_PWR_CFG_0_9MBS               FIELD32(0x00f00000)
1086 #define TX_PWR_CFG_0_12MBS              FIELD32(0x0f000000)
1087 #define TX_PWR_CFG_0_18MBS              FIELD32(0xf0000000)
1088 /* bits for 3T devices */
1089 #define TX_PWR_CFG_0_CCK1_CH0           FIELD32(0x0000000f)
1090 #define TX_PWR_CFG_0_CCK1_CH1           FIELD32(0x000000f0)
1091 #define TX_PWR_CFG_0_CCK5_CH0           FIELD32(0x00000f00)
1092 #define TX_PWR_CFG_0_CCK5_CH1           FIELD32(0x0000f000)
1093 #define TX_PWR_CFG_0_OFDM6_CH0          FIELD32(0x000f0000)
1094 #define TX_PWR_CFG_0_OFDM6_CH1          FIELD32(0x00f00000)
1095 #define TX_PWR_CFG_0_OFDM12_CH0         FIELD32(0x0f000000)
1096 #define TX_PWR_CFG_0_OFDM12_CH1         FIELD32(0xf0000000)
1097
1098 /*
1099  * TX_PWR_CFG_1:
1100  */
1101 #define TX_PWR_CFG_1                    0x1318
1102 #define TX_PWR_CFG_1_24MBS              FIELD32(0x0000000f)
1103 #define TX_PWR_CFG_1_36MBS              FIELD32(0x000000f0)
1104 #define TX_PWR_CFG_1_48MBS              FIELD32(0x00000f00)
1105 #define TX_PWR_CFG_1_54MBS              FIELD32(0x0000f000)
1106 #define TX_PWR_CFG_1_MCS0               FIELD32(0x000f0000)
1107 #define TX_PWR_CFG_1_MCS1               FIELD32(0x00f00000)
1108 #define TX_PWR_CFG_1_MCS2               FIELD32(0x0f000000)
1109 #define TX_PWR_CFG_1_MCS3               FIELD32(0xf0000000)
1110 /* bits for 3T devices */
1111 #define TX_PWR_CFG_1_OFDM24_CH0         FIELD32(0x0000000f)
1112 #define TX_PWR_CFG_1_OFDM24_CH1         FIELD32(0x000000f0)
1113 #define TX_PWR_CFG_1_OFDM48_CH0         FIELD32(0x00000f00)
1114 #define TX_PWR_CFG_1_OFDM48_CH1         FIELD32(0x0000f000)
1115 #define TX_PWR_CFG_1_MCS0_CH0           FIELD32(0x000f0000)
1116 #define TX_PWR_CFG_1_MCS0_CH1           FIELD32(0x00f00000)
1117 #define TX_PWR_CFG_1_MCS2_CH0           FIELD32(0x0f000000)
1118 #define TX_PWR_CFG_1_MCS2_CH1           FIELD32(0xf0000000)
1119
1120 /*
1121  * TX_PWR_CFG_2:
1122  */
1123 #define TX_PWR_CFG_2                    0x131c
1124 #define TX_PWR_CFG_2_MCS4               FIELD32(0x0000000f)
1125 #define TX_PWR_CFG_2_MCS5               FIELD32(0x000000f0)
1126 #define TX_PWR_CFG_2_MCS6               FIELD32(0x00000f00)
1127 #define TX_PWR_CFG_2_MCS7               FIELD32(0x0000f000)
1128 #define TX_PWR_CFG_2_MCS8               FIELD32(0x000f0000)
1129 #define TX_PWR_CFG_2_MCS9               FIELD32(0x00f00000)
1130 #define TX_PWR_CFG_2_MCS10              FIELD32(0x0f000000)
1131 #define TX_PWR_CFG_2_MCS11              FIELD32(0xf0000000)
1132 /* bits for 3T devices */
1133 #define TX_PWR_CFG_2_MCS4_CH0           FIELD32(0x0000000f)
1134 #define TX_PWR_CFG_2_MCS4_CH1           FIELD32(0x000000f0)
1135 #define TX_PWR_CFG_2_MCS6_CH0           FIELD32(0x00000f00)
1136 #define TX_PWR_CFG_2_MCS6_CH1           FIELD32(0x0000f000)
1137 #define TX_PWR_CFG_2_MCS8_CH0           FIELD32(0x000f0000)
1138 #define TX_PWR_CFG_2_MCS8_CH1           FIELD32(0x00f00000)
1139 #define TX_PWR_CFG_2_MCS10_CH0          FIELD32(0x0f000000)
1140 #define TX_PWR_CFG_2_MCS10_CH1          FIELD32(0xf0000000)
1141
1142 /*
1143  * TX_PWR_CFG_3:
1144  */
1145 #define TX_PWR_CFG_3                    0x1320
1146 #define TX_PWR_CFG_3_MCS12              FIELD32(0x0000000f)
1147 #define TX_PWR_CFG_3_MCS13              FIELD32(0x000000f0)
1148 #define TX_PWR_CFG_3_MCS14              FIELD32(0x00000f00)
1149 #define TX_PWR_CFG_3_MCS15              FIELD32(0x0000f000)
1150 #define TX_PWR_CFG_3_UKNOWN1            FIELD32(0x000f0000)
1151 #define TX_PWR_CFG_3_UKNOWN2            FIELD32(0x00f00000)
1152 #define TX_PWR_CFG_3_UKNOWN3            FIELD32(0x0f000000)
1153 #define TX_PWR_CFG_3_UKNOWN4            FIELD32(0xf0000000)
1154 /* bits for 3T devices */
1155 #define TX_PWR_CFG_3_MCS12_CH0          FIELD32(0x0000000f)
1156 #define TX_PWR_CFG_3_MCS12_CH1          FIELD32(0x000000f0)
1157 #define TX_PWR_CFG_3_MCS14_CH0          FIELD32(0x00000f00)
1158 #define TX_PWR_CFG_3_MCS14_CH1          FIELD32(0x0000f000)
1159 #define TX_PWR_CFG_3_STBC0_CH0          FIELD32(0x000f0000)
1160 #define TX_PWR_CFG_3_STBC0_CH1          FIELD32(0x00f00000)
1161 #define TX_PWR_CFG_3_STBC2_CH0          FIELD32(0x0f000000)
1162 #define TX_PWR_CFG_3_STBC2_CH1          FIELD32(0xf0000000)
1163
1164 /*
1165  * TX_PWR_CFG_4:
1166  */
1167 #define TX_PWR_CFG_4                    0x1324
1168 #define TX_PWR_CFG_4_UKNOWN5            FIELD32(0x0000000f)
1169 #define TX_PWR_CFG_4_UKNOWN6            FIELD32(0x000000f0)
1170 #define TX_PWR_CFG_4_UKNOWN7            FIELD32(0x00000f00)
1171 #define TX_PWR_CFG_4_UKNOWN8            FIELD32(0x0000f000)
1172 /* bits for 3T devices */
1173 #define TX_PWR_CFG_3_STBC4_CH0          FIELD32(0x0000000f)
1174 #define TX_PWR_CFG_3_STBC4_CH1          FIELD32(0x000000f0)
1175 #define TX_PWR_CFG_3_STBC6_CH0          FIELD32(0x00000f00)
1176 #define TX_PWR_CFG_3_STBC6_CH1          FIELD32(0x0000f000)
1177
1178 /*
1179  * TX_PIN_CFG:
1180  */
1181 #define TX_PIN_CFG                      0x1328
1182 #define TX_PIN_CFG_PA_PE_DISABLE        0xfcfffff0
1183 #define TX_PIN_CFG_PA_PE_A0_EN          FIELD32(0x00000001)
1184 #define TX_PIN_CFG_PA_PE_G0_EN          FIELD32(0x00000002)
1185 #define TX_PIN_CFG_PA_PE_A1_EN          FIELD32(0x00000004)
1186 #define TX_PIN_CFG_PA_PE_G1_EN          FIELD32(0x00000008)
1187 #define TX_PIN_CFG_PA_PE_A0_POL         FIELD32(0x00000010)
1188 #define TX_PIN_CFG_PA_PE_G0_POL         FIELD32(0x00000020)
1189 #define TX_PIN_CFG_PA_PE_A1_POL         FIELD32(0x00000040)
1190 #define TX_PIN_CFG_PA_PE_G1_POL         FIELD32(0x00000080)
1191 #define TX_PIN_CFG_LNA_PE_A0_EN         FIELD32(0x00000100)
1192 #define TX_PIN_CFG_LNA_PE_G0_EN         FIELD32(0x00000200)
1193 #define TX_PIN_CFG_LNA_PE_A1_EN         FIELD32(0x00000400)
1194 #define TX_PIN_CFG_LNA_PE_G1_EN         FIELD32(0x00000800)
1195 #define TX_PIN_CFG_LNA_PE_A0_POL        FIELD32(0x00001000)
1196 #define TX_PIN_CFG_LNA_PE_G0_POL        FIELD32(0x00002000)
1197 #define TX_PIN_CFG_LNA_PE_A1_POL        FIELD32(0x00004000)
1198 #define TX_PIN_CFG_LNA_PE_G1_POL        FIELD32(0x00008000)
1199 #define TX_PIN_CFG_RFTR_EN              FIELD32(0x00010000)
1200 #define TX_PIN_CFG_RFTR_POL             FIELD32(0x00020000)
1201 #define TX_PIN_CFG_TRSW_EN              FIELD32(0x00040000)
1202 #define TX_PIN_CFG_TRSW_POL             FIELD32(0x00080000)
1203 #define TX_PIN_CFG_PA_PE_A2_EN          FIELD32(0x01000000)
1204 #define TX_PIN_CFG_PA_PE_G2_EN          FIELD32(0x02000000)
1205 #define TX_PIN_CFG_PA_PE_A2_POL         FIELD32(0x04000000)
1206 #define TX_PIN_CFG_PA_PE_G2_POL         FIELD32(0x08000000)
1207 #define TX_PIN_CFG_LNA_PE_A2_EN         FIELD32(0x10000000)
1208 #define TX_PIN_CFG_LNA_PE_G2_EN         FIELD32(0x20000000)
1209 #define TX_PIN_CFG_LNA_PE_A2_POL        FIELD32(0x40000000)
1210 #define TX_PIN_CFG_LNA_PE_G2_POL        FIELD32(0x80000000)
1211
1212 /*
1213  * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
1214  */
1215 #define TX_BAND_CFG                     0x132c
1216 #define TX_BAND_CFG_HT40_MINUS          FIELD32(0x00000001)
1217 #define TX_BAND_CFG_A                   FIELD32(0x00000002)
1218 #define TX_BAND_CFG_BG                  FIELD32(0x00000004)
1219
1220 /*
1221  * TX_SW_CFG0:
1222  */
1223 #define TX_SW_CFG0                      0x1330
1224
1225 /*
1226  * TX_SW_CFG1:
1227  */
1228 #define TX_SW_CFG1                      0x1334
1229
1230 /*
1231  * TX_SW_CFG2:
1232  */
1233 #define TX_SW_CFG2                      0x1338
1234
1235 /*
1236  * TXOP_THRES_CFG:
1237  */
1238 #define TXOP_THRES_CFG                  0x133c
1239
1240 /*
1241  * TXOP_CTRL_CFG:
1242  * TIMEOUT_TRUN_EN: Enable/Disable TXOP timeout truncation
1243  * AC_TRUN_EN: Enable/Disable truncation for AC change
1244  * TXRATEGRP_TRUN_EN: Enable/Disable truncation for TX rate group change
1245  * USER_MODE_TRUN_EN: Enable/Disable truncation for user TXOP mode
1246  * MIMO_PS_TRUN_EN: Enable/Disable truncation for MIMO PS RTS/CTS
1247  * RESERVED_TRUN_EN: Reserved
1248  * LSIG_TXOP_EN: Enable/Disable L-SIG TXOP protection
1249  * EXT_CCA_EN: Enable/Disable extension channel CCA reference (Defer 40Mhz
1250  *             transmissions if extension CCA is clear).
1251  * EXT_CCA_DLY: Extension CCA signal delay time (unit: us)
1252  * EXT_CWMIN: CwMin for extension channel backoff
1253  *            0: Disabled
1254  *
1255  */
1256 #define TXOP_CTRL_CFG                   0x1340
1257 #define TXOP_CTRL_CFG_TIMEOUT_TRUN_EN   FIELD32(0x00000001)
1258 #define TXOP_CTRL_CFG_AC_TRUN_EN        FIELD32(0x00000002)
1259 #define TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN FIELD32(0x00000004)
1260 #define TXOP_CTRL_CFG_USER_MODE_TRUN_EN FIELD32(0x00000008)
1261 #define TXOP_CTRL_CFG_MIMO_PS_TRUN_EN   FIELD32(0x00000010)
1262 #define TXOP_CTRL_CFG_RESERVED_TRUN_EN  FIELD32(0x00000020)
1263 #define TXOP_CTRL_CFG_LSIG_TXOP_EN      FIELD32(0x00000040)
1264 #define TXOP_CTRL_CFG_EXT_CCA_EN        FIELD32(0x00000080)
1265 #define TXOP_CTRL_CFG_EXT_CCA_DLY       FIELD32(0x0000ff00)
1266 #define TXOP_CTRL_CFG_EXT_CWMIN         FIELD32(0x000f0000)
1267
1268 /*
1269  * TX_RTS_CFG:
1270  * RTS_THRES: unit:byte
1271  * RTS_FBK_EN: enable rts rate fallback
1272  */
1273 #define TX_RTS_CFG                      0x1344
1274 #define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
1275 #define TX_RTS_CFG_RTS_THRES            FIELD32(0x00ffff00)
1276 #define TX_RTS_CFG_RTS_FBK_EN           FIELD32(0x01000000)
1277
1278 /*
1279  * TX_TIMEOUT_CFG:
1280  * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
1281  * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
1282  * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
1283  *                it is recommended that:
1284  *                (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
1285  */
1286 #define TX_TIMEOUT_CFG                  0x1348
1287 #define TX_TIMEOUT_CFG_MPDU_LIFETIME    FIELD32(0x000000f0)
1288 #define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT   FIELD32(0x0000ff00)
1289 #define TX_TIMEOUT_CFG_TX_OP_TIMEOUT    FIELD32(0x00ff0000)
1290
1291 /*
1292  * TX_RTY_CFG:
1293  * SHORT_RTY_LIMIT: short retry limit
1294  * LONG_RTY_LIMIT: long retry limit
1295  * LONG_RTY_THRE: Long retry threshoold
1296  * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
1297  *                   0:expired by retry limit, 1: expired by mpdu life timer
1298  * AGG_RTY_MODE: Aggregate MPDU retry mode
1299  *               0:expired by retry limit, 1: expired by mpdu life timer
1300  * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
1301  */
1302 #define TX_RTY_CFG                      0x134c
1303 #define TX_RTY_CFG_SHORT_RTY_LIMIT      FIELD32(0x000000ff)
1304 #define TX_RTY_CFG_LONG_RTY_LIMIT       FIELD32(0x0000ff00)
1305 #define TX_RTY_CFG_LONG_RTY_THRE        FIELD32(0x0fff0000)
1306 #define TX_RTY_CFG_NON_AGG_RTY_MODE     FIELD32(0x10000000)
1307 #define TX_RTY_CFG_AGG_RTY_MODE         FIELD32(0x20000000)
1308 #define TX_RTY_CFG_TX_AUTO_FB_ENABLE    FIELD32(0x40000000)
1309
1310 /*
1311  * TX_LINK_CFG:
1312  * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
1313  * MFB_ENABLE: TX apply remote MFB 1:enable
1314  * REMOTE_UMFS_ENABLE: remote unsolicit  MFB enable
1315  *                     0: not apply remote remote unsolicit (MFS=7)
1316  * TX_MRQ_EN: MCS request TX enable
1317  * TX_RDG_EN: RDG TX enable
1318  * TX_CF_ACK_EN: Piggyback CF-ACK enable
1319  * REMOTE_MFB: remote MCS feedback
1320  * REMOTE_MFS: remote MCS feedback sequence number
1321  */
1322 #define TX_LINK_CFG                     0x1350
1323 #define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
1324 #define TX_LINK_CFG_MFB_ENABLE          FIELD32(0x00000100)
1325 #define TX_LINK_CFG_REMOTE_UMFS_ENABLE  FIELD32(0x00000200)
1326 #define TX_LINK_CFG_TX_MRQ_EN           FIELD32(0x00000400)
1327 #define TX_LINK_CFG_TX_RDG_EN           FIELD32(0x00000800)
1328 #define TX_LINK_CFG_TX_CF_ACK_EN        FIELD32(0x00001000)
1329 #define TX_LINK_CFG_REMOTE_MFB          FIELD32(0x00ff0000)
1330 #define TX_LINK_CFG_REMOTE_MFS          FIELD32(0xff000000)
1331
1332 /*
1333  * HT_FBK_CFG0:
1334  */
1335 #define HT_FBK_CFG0                     0x1354
1336 #define HT_FBK_CFG0_HTMCS0FBK           FIELD32(0x0000000f)
1337 #define HT_FBK_CFG0_HTMCS1FBK           FIELD32(0x000000f0)
1338 #define HT_FBK_CFG0_HTMCS2FBK           FIELD32(0x00000f00)
1339 #define HT_FBK_CFG0_HTMCS3FBK           FIELD32(0x0000f000)
1340 #define HT_FBK_CFG0_HTMCS4FBK           FIELD32(0x000f0000)
1341 #define HT_FBK_CFG0_HTMCS5FBK           FIELD32(0x00f00000)
1342 #define HT_FBK_CFG0_HTMCS6FBK           FIELD32(0x0f000000)
1343 #define HT_FBK_CFG0_HTMCS7FBK           FIELD32(0xf0000000)
1344
1345 /*
1346  * HT_FBK_CFG1:
1347  */
1348 #define HT_FBK_CFG1                     0x1358
1349 #define HT_FBK_CFG1_HTMCS8FBK           FIELD32(0x0000000f)
1350 #define HT_FBK_CFG1_HTMCS9FBK           FIELD32(0x000000f0)
1351 #define HT_FBK_CFG1_HTMCS10FBK          FIELD32(0x00000f00)
1352 #define HT_FBK_CFG1_HTMCS11FBK          FIELD32(0x0000f000)
1353 #define HT_FBK_CFG1_HTMCS12FBK          FIELD32(0x000f0000)
1354 #define HT_FBK_CFG1_HTMCS13FBK          FIELD32(0x00f00000)
1355 #define HT_FBK_CFG1_HTMCS14FBK          FIELD32(0x0f000000)
1356 #define HT_FBK_CFG1_HTMCS15FBK          FIELD32(0xf0000000)
1357
1358 /*
1359  * LG_FBK_CFG0:
1360  */
1361 #define LG_FBK_CFG0                     0x135c
1362 #define LG_FBK_CFG0_OFDMMCS0FBK         FIELD32(0x0000000f)
1363 #define LG_FBK_CFG0_OFDMMCS1FBK         FIELD32(0x000000f0)
1364 #define LG_FBK_CFG0_OFDMMCS2FBK         FIELD32(0x00000f00)
1365 #define LG_FBK_CFG0_OFDMMCS3FBK         FIELD32(0x0000f000)
1366 #define LG_FBK_CFG0_OFDMMCS4FBK         FIELD32(0x000f0000)
1367 #define LG_FBK_CFG0_OFDMMCS5FBK         FIELD32(0x00f00000)
1368 #define LG_FBK_CFG0_OFDMMCS6FBK         FIELD32(0x0f000000)
1369 #define LG_FBK_CFG0_OFDMMCS7FBK         FIELD32(0xf0000000)
1370
1371 /*
1372  * LG_FBK_CFG1:
1373  */
1374 #define LG_FBK_CFG1                     0x1360
1375 #define LG_FBK_CFG0_CCKMCS0FBK          FIELD32(0x0000000f)
1376 #define LG_FBK_CFG0_CCKMCS1FBK          FIELD32(0x000000f0)
1377 #define LG_FBK_CFG0_CCKMCS2FBK          FIELD32(0x00000f00)
1378 #define LG_FBK_CFG0_CCKMCS3FBK          FIELD32(0x0000f000)
1379
1380 /*
1381  * CCK_PROT_CFG: CCK Protection
1382  * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
1383  * PROTECT_CTRL: Protection control frame type for CCK TX
1384  *               0:none, 1:RTS/CTS, 2:CTS-to-self
1385  * PROTECT_NAV_SHORT: TXOP protection type for CCK TX with short NAV
1386  * PROTECT_NAV_LONG: TXOP protection type for CCK TX with long NAV
1387  * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
1388  * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
1389  * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
1390  * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
1391  * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
1392  * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
1393  * RTS_TH_EN: RTS threshold enable on CCK TX
1394  */
1395 #define CCK_PROT_CFG                    0x1364
1396 #define CCK_PROT_CFG_PROTECT_RATE       FIELD32(0x0000ffff)
1397 #define CCK_PROT_CFG_PROTECT_CTRL       FIELD32(0x00030000)
1398 #define CCK_PROT_CFG_PROTECT_NAV_SHORT  FIELD32(0x00040000)
1399 #define CCK_PROT_CFG_PROTECT_NAV_LONG   FIELD32(0x00080000)
1400 #define CCK_PROT_CFG_TX_OP_ALLOW_CCK    FIELD32(0x00100000)
1401 #define CCK_PROT_CFG_TX_OP_ALLOW_OFDM   FIELD32(0x00200000)
1402 #define CCK_PROT_CFG_TX_OP_ALLOW_MM20   FIELD32(0x00400000)
1403 #define CCK_PROT_CFG_TX_OP_ALLOW_MM40   FIELD32(0x00800000)
1404 #define CCK_PROT_CFG_TX_OP_ALLOW_GF20   FIELD32(0x01000000)
1405 #define CCK_PROT_CFG_TX_OP_ALLOW_GF40   FIELD32(0x02000000)
1406 #define CCK_PROT_CFG_RTS_TH_EN          FIELD32(0x04000000)
1407
1408 /*
1409  * OFDM_PROT_CFG: OFDM Protection
1410  */
1411 #define OFDM_PROT_CFG                   0x1368
1412 #define OFDM_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
1413 #define OFDM_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
1414 #define OFDM_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1415 #define OFDM_PROT_CFG_PROTECT_NAV_LONG  FIELD32(0x00080000)
1416 #define OFDM_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
1417 #define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
1418 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
1419 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM40  FIELD32(0x00800000)
1420 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF20  FIELD32(0x01000000)
1421 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF40  FIELD32(0x02000000)
1422 #define OFDM_PROT_CFG_RTS_TH_EN         FIELD32(0x04000000)
1423
1424 /*
1425  * MM20_PROT_CFG: MM20 Protection
1426  */
1427 #define MM20_PROT_CFG                   0x136c
1428 #define MM20_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
1429 #define MM20_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
1430 #define MM20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1431 #define MM20_PROT_CFG_PROTECT_NAV_LONG  FIELD32(0x00080000)
1432 #define MM20_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
1433 #define MM20_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
1434 #define MM20_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
1435 #define MM20_PROT_CFG_TX_OP_ALLOW_MM40  FIELD32(0x00800000)
1436 #define MM20_PROT_CFG_TX_OP_ALLOW_GF20  FIELD32(0x01000000)
1437 #define MM20_PROT_CFG_TX_OP_ALLOW_GF40  FIELD32(0x02000000)
1438 #define MM20_PROT_CFG_RTS_TH_EN         FIELD32(0x04000000)
1439
1440 /*
1441  * MM40_PROT_CFG: MM40 Protection
1442  */
1443 #define MM40_PROT_CFG                   0x1370
1444 #define MM40_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
1445 #define MM40_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
1446 #define MM40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1447 #define MM40_PROT_CFG_PROTECT_NAV_LONG  FIELD32(0x00080000)
1448 #define MM40_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
1449 #define MM40_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
1450 #define MM40_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
1451 #define MM40_PROT_CFG_TX_OP_ALLOW_MM40  FIELD32(0x00800000)
1452 #define MM40_PROT_CFG_TX_OP_ALLOW_GF20  FIELD32(0x01000000)
1453 #define MM40_PROT_CFG_TX_OP_ALLOW_GF40  FIELD32(0x02000000)
1454 #define MM40_PROT_CFG_RTS_TH_EN         FIELD32(0x04000000)
1455
1456 /*
1457  * GF20_PROT_CFG: GF20 Protection
1458  */
1459 #define GF20_PROT_CFG                   0x1374
1460 #define GF20_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
1461 #define GF20_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
1462 #define GF20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1463 #define GF20_PROT_CFG_PROTECT_NAV_LONG  FIELD32(0x00080000)
1464 #define GF20_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
1465 #define GF20_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
1466 #define GF20_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
1467 #define GF20_PROT_CFG_TX_OP_ALLOW_MM40  FIELD32(0x00800000)
1468 #define GF20_PROT_CFG_TX_OP_ALLOW_GF20  FIELD32(0x01000000)
1469 #define GF20_PROT_CFG_TX_OP_ALLOW_GF40  FIELD32(0x02000000)
1470 #define GF20_PROT_CFG_RTS_TH_EN         FIELD32(0x04000000)
1471
1472 /*
1473  * GF40_PROT_CFG: GF40 Protection
1474  */
1475 #define GF40_PROT_CFG                   0x1378
1476 #define GF40_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
1477 #define GF40_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
1478 #define GF40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1479 #define GF40_PROT_CFG_PROTECT_NAV_LONG  FIELD32(0x00080000)
1480 #define GF40_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
1481 #define GF40_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
1482 #define GF40_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
1483 #define GF40_PROT_CFG_TX_OP_ALLOW_MM40  FIELD32(0x00800000)
1484 #define GF40_PROT_CFG_TX_OP_ALLOW_GF20  FIELD32(0x01000000)
1485 #define GF40_PROT_CFG_TX_OP_ALLOW_GF40  FIELD32(0x02000000)
1486 #define GF40_PROT_CFG_RTS_TH_EN         FIELD32(0x04000000)
1487
1488 /*
1489  * EXP_CTS_TIME:
1490  */
1491 #define EXP_CTS_TIME                    0x137c
1492
1493 /*
1494  * EXP_ACK_TIME:
1495  */
1496 #define EXP_ACK_TIME                    0x1380
1497
1498 /* TX_PWR_CFG_5 */
1499 #define TX_PWR_CFG_5                    0x1384
1500 #define TX_PWR_CFG_5_MCS16_CH0          FIELD32(0x0000000f)
1501 #define TX_PWR_CFG_5_MCS16_CH1          FIELD32(0x000000f0)
1502 #define TX_PWR_CFG_5_MCS16_CH2          FIELD32(0x00000f00)
1503 #define TX_PWR_CFG_5_MCS18_CH0          FIELD32(0x000f0000)
1504 #define TX_PWR_CFG_5_MCS18_CH1          FIELD32(0x00f00000)
1505 #define TX_PWR_CFG_5_MCS18_CH2          FIELD32(0x0f000000)
1506
1507 /* TX_PWR_CFG_6 */
1508 #define TX_PWR_CFG_6                    0x1388
1509 #define TX_PWR_CFG_6_MCS20_CH0          FIELD32(0x0000000f)
1510 #define TX_PWR_CFG_6_MCS20_CH1          FIELD32(0x000000f0)
1511 #define TX_PWR_CFG_6_MCS20_CH2          FIELD32(0x00000f00)
1512 #define TX_PWR_CFG_6_MCS22_CH0          FIELD32(0x000f0000)
1513 #define TX_PWR_CFG_6_MCS22_CH1          FIELD32(0x00f00000)
1514 #define TX_PWR_CFG_6_MCS22_CH2          FIELD32(0x0f000000)
1515
1516 /* TX_PWR_CFG_0_EXT */
1517 #define TX_PWR_CFG_0_EXT                0x1390
1518 #define TX_PWR_CFG_0_EXT_CCK1_CH2       FIELD32(0x0000000f)
1519 #define TX_PWR_CFG_0_EXT_CCK5_CH2       FIELD32(0x00000f00)
1520 #define TX_PWR_CFG_0_EXT_OFDM6_CH2      FIELD32(0x000f0000)
1521 #define TX_PWR_CFG_0_EXT_OFDM12_CH2     FIELD32(0x0f000000)
1522
1523 /* TX_PWR_CFG_1_EXT */
1524 #define TX_PWR_CFG_1_EXT                0x1394
1525 #define TX_PWR_CFG_1_EXT_OFDM24_CH2     FIELD32(0x0000000f)
1526 #define TX_PWR_CFG_1_EXT_OFDM48_CH2     FIELD32(0x00000f00)
1527 #define TX_PWR_CFG_1_EXT_MCS0_CH2       FIELD32(0x000f0000)
1528 #define TX_PWR_CFG_1_EXT_MCS2_CH2       FIELD32(0x0f000000)
1529
1530 /* TX_PWR_CFG_2_EXT */
1531 #define TX_PWR_CFG_2_EXT                0x1398
1532 #define TX_PWR_CFG_2_EXT_MCS4_CH2       FIELD32(0x0000000f)
1533 #define TX_PWR_CFG_2_EXT_MCS6_CH2       FIELD32(0x00000f00)
1534 #define TX_PWR_CFG_2_EXT_MCS8_CH2       FIELD32(0x000f0000)
1535 #define TX_PWR_CFG_2_EXT_MCS10_CH2      FIELD32(0x0f000000)
1536
1537 /* TX_PWR_CFG_3_EXT */
1538 #define TX_PWR_CFG_3_EXT                0x139c
1539 #define TX_PWR_CFG_3_EXT_MCS12_CH2      FIELD32(0x0000000f)
1540 #define TX_PWR_CFG_3_EXT_MCS14_CH2      FIELD32(0x00000f00)
1541 #define TX_PWR_CFG_3_EXT_STBC0_CH2      FIELD32(0x000f0000)
1542 #define TX_PWR_CFG_3_EXT_STBC2_CH2      FIELD32(0x0f000000)
1543
1544 /* TX_PWR_CFG_4_EXT */
1545 #define TX_PWR_CFG_4_EXT                0x13a0
1546 #define TX_PWR_CFG_4_EXT_STBC4_CH2      FIELD32(0x0000000f)
1547 #define TX_PWR_CFG_4_EXT_STBC6_CH2      FIELD32(0x00000f00)
1548
1549 /* TX_PWR_CFG_7 */
1550 #define TX_PWR_CFG_7                    0x13d4
1551 #define TX_PWR_CFG_7_OFDM54_CH0         FIELD32(0x0000000f)
1552 #define TX_PWR_CFG_7_OFDM54_CH1         FIELD32(0x000000f0)
1553 #define TX_PWR_CFG_7_OFDM54_CH2         FIELD32(0x00000f00)
1554 #define TX_PWR_CFG_7_MCS7_CH0           FIELD32(0x000f0000)
1555 #define TX_PWR_CFG_7_MCS7_CH1           FIELD32(0x00f00000)
1556 #define TX_PWR_CFG_7_MCS7_CH2           FIELD32(0x0f000000)
1557
1558 /* TX_PWR_CFG_8 */
1559 #define TX_PWR_CFG_8                    0x13d8
1560 #define TX_PWR_CFG_8_MCS15_CH0          FIELD32(0x0000000f)
1561 #define TX_PWR_CFG_8_MCS15_CH1          FIELD32(0x000000f0)
1562 #define TX_PWR_CFG_8_MCS15_CH2          FIELD32(0x00000f00)
1563 #define TX_PWR_CFG_8_MCS23_CH0          FIELD32(0x000f0000)
1564 #define TX_PWR_CFG_8_MCS23_CH1          FIELD32(0x00f00000)
1565 #define TX_PWR_CFG_8_MCS23_CH2          FIELD32(0x0f000000)
1566
1567 /* TX_PWR_CFG_9 */
1568 #define TX_PWR_CFG_9                    0x13dc
1569 #define TX_PWR_CFG_9_STBC7_CH0          FIELD32(0x0000000f)
1570 #define TX_PWR_CFG_9_STBC7_CH1          FIELD32(0x000000f0)
1571 #define TX_PWR_CFG_9_STBC7_CH2          FIELD32(0x00000f00)
1572
1573 /*
1574  * RX_FILTER_CFG: RX configuration register.
1575  */
1576 #define RX_FILTER_CFG                   0x1400
1577 #define RX_FILTER_CFG_DROP_CRC_ERROR    FIELD32(0x00000001)
1578 #define RX_FILTER_CFG_DROP_PHY_ERROR    FIELD32(0x00000002)
1579 #define RX_FILTER_CFG_DROP_NOT_TO_ME    FIELD32(0x00000004)
1580 #define RX_FILTER_CFG_DROP_NOT_MY_BSSD  FIELD32(0x00000008)
1581 #define RX_FILTER_CFG_DROP_VER_ERROR    FIELD32(0x00000010)
1582 #define RX_FILTER_CFG_DROP_MULTICAST    FIELD32(0x00000020)
1583 #define RX_FILTER_CFG_DROP_BROADCAST    FIELD32(0x00000040)
1584 #define RX_FILTER_CFG_DROP_DUPLICATE    FIELD32(0x00000080)
1585 #define RX_FILTER_CFG_DROP_CF_END_ACK   FIELD32(0x00000100)
1586 #define RX_FILTER_CFG_DROP_CF_END       FIELD32(0x00000200)
1587 #define RX_FILTER_CFG_DROP_ACK          FIELD32(0x00000400)
1588 #define RX_FILTER_CFG_DROP_CTS          FIELD32(0x00000800)
1589 #define RX_FILTER_CFG_DROP_RTS          FIELD32(0x00001000)
1590 #define RX_FILTER_CFG_DROP_PSPOLL       FIELD32(0x00002000)
1591 #define RX_FILTER_CFG_DROP_BA           FIELD32(0x00004000)
1592 #define RX_FILTER_CFG_DROP_BAR          FIELD32(0x00008000)
1593 #define RX_FILTER_CFG_DROP_CNTL         FIELD32(0x00010000)
1594
1595 /*
1596  * AUTO_RSP_CFG:
1597  * AUTORESPONDER: 0: disable, 1: enable
1598  * BAC_ACK_POLICY: 0:long, 1:short preamble
1599  * CTS_40_MMODE: Response CTS 40MHz duplicate mode
1600  * CTS_40_MREF: Response CTS 40MHz duplicate mode
1601  * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
1602  * DUAL_CTS_EN: Power bit value in control frame
1603  * ACK_CTS_PSM_BIT:Power bit value in control frame
1604  */
1605 #define AUTO_RSP_CFG                    0x1404
1606 #define AUTO_RSP_CFG_AUTORESPONDER      FIELD32(0x00000001)
1607 #define AUTO_RSP_CFG_BAC_ACK_POLICY     FIELD32(0x00000002)
1608 #define AUTO_RSP_CFG_CTS_40_MMODE       FIELD32(0x00000004)
1609 #define AUTO_RSP_CFG_CTS_40_MREF        FIELD32(0x00000008)
1610 #define AUTO_RSP_CFG_AR_PREAMBLE        FIELD32(0x00000010)
1611 #define AUTO_RSP_CFG_DUAL_CTS_EN        FIELD32(0x00000040)
1612 #define AUTO_RSP_CFG_ACK_CTS_PSM_BIT    FIELD32(0x00000080)
1613
1614 /*
1615  * LEGACY_BASIC_RATE:
1616  */
1617 #define LEGACY_BASIC_RATE               0x1408
1618
1619 /*
1620  * HT_BASIC_RATE:
1621  */
1622 #define HT_BASIC_RATE                   0x140c
1623
1624 /*
1625  * HT_CTRL_CFG:
1626  */
1627 #define HT_CTRL_CFG                     0x1410
1628
1629 /*
1630  * SIFS_COST_CFG:
1631  */
1632 #define SIFS_COST_CFG                   0x1414
1633
1634 /*
1635  * RX_PARSER_CFG:
1636  * Set NAV for all received frames
1637  */
1638 #define RX_PARSER_CFG                   0x1418
1639
1640 /*
1641  * TX_SEC_CNT0:
1642  */
1643 #define TX_SEC_CNT0                     0x1500
1644
1645 /*
1646  * RX_SEC_CNT0:
1647  */
1648 #define RX_SEC_CNT0                     0x1504
1649
1650 /*
1651  * CCMP_FC_MUTE:
1652  */
1653 #define CCMP_FC_MUTE                    0x1508
1654
1655 /*
1656  * TXOP_HLDR_ADDR0:
1657  */
1658 #define TXOP_HLDR_ADDR0                 0x1600
1659
1660 /*
1661  * TXOP_HLDR_ADDR1:
1662  */
1663 #define TXOP_HLDR_ADDR1                 0x1604
1664
1665 /*
1666  * TXOP_HLDR_ET:
1667  */
1668 #define TXOP_HLDR_ET                    0x1608
1669
1670 /*
1671  * QOS_CFPOLL_RA_DW0:
1672  */
1673 #define QOS_CFPOLL_RA_DW0               0x160c
1674
1675 /*
1676  * QOS_CFPOLL_RA_DW1:
1677  */
1678 #define QOS_CFPOLL_RA_DW1               0x1610
1679
1680 /*
1681  * QOS_CFPOLL_QC:
1682  */
1683 #define QOS_CFPOLL_QC                   0x1614
1684
1685 /*
1686  * RX_STA_CNT0: RX PLCP error count & RX CRC error count
1687  */
1688 #define RX_STA_CNT0                     0x1700
1689 #define RX_STA_CNT0_CRC_ERR             FIELD32(0x0000ffff)
1690 #define RX_STA_CNT0_PHY_ERR             FIELD32(0xffff0000)
1691
1692 /*
1693  * RX_STA_CNT1: RX False CCA count & RX LONG frame count
1694  */
1695 #define RX_STA_CNT1                     0x1704
1696 #define RX_STA_CNT1_FALSE_CCA           FIELD32(0x0000ffff)
1697 #define RX_STA_CNT1_PLCP_ERR            FIELD32(0xffff0000)
1698
1699 /*
1700  * RX_STA_CNT2:
1701  */
1702 #define RX_STA_CNT2                     0x1708
1703 #define RX_STA_CNT2_RX_DUPLI_COUNT      FIELD32(0x0000ffff)
1704 #define RX_STA_CNT2_RX_FIFO_OVERFLOW    FIELD32(0xffff0000)
1705
1706 /*
1707  * TX_STA_CNT0: TX Beacon count
1708  */
1709 #define TX_STA_CNT0                     0x170c
1710 #define TX_STA_CNT0_TX_FAIL_COUNT       FIELD32(0x0000ffff)
1711 #define TX_STA_CNT0_TX_BEACON_COUNT     FIELD32(0xffff0000)
1712
1713 /*
1714  * TX_STA_CNT1: TX tx count
1715  */
1716 #define TX_STA_CNT1                     0x1710
1717 #define TX_STA_CNT1_TX_SUCCESS          FIELD32(0x0000ffff)
1718 #define TX_STA_CNT1_TX_RETRANSMIT       FIELD32(0xffff0000)
1719
1720 /*
1721  * TX_STA_CNT2: TX tx count
1722  */
1723 #define TX_STA_CNT2                     0x1714
1724 #define TX_STA_CNT2_TX_ZERO_LEN_COUNT   FIELD32(0x0000ffff)
1725 #define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1726
1727 /*
1728  * TX_STA_FIFO: TX Result for specific PID status fifo register.
1729  *
1730  * This register is implemented as FIFO with 16 entries in the HW. Each
1731  * register read fetches the next tx result. If the FIFO is full because
1732  * it wasn't read fast enough after the according interrupt (TX_FIFO_STATUS)
1733  * triggered, the hw seems to simply drop further tx results.
1734  *
1735  * VALID: 1: this tx result is valid
1736  *        0: no valid tx result -> driver should stop reading
1737  * PID_TYPE: The PID latched from the PID field in the TXWI, can be used
1738  *           to match a frame with its tx result (even though the PID is
1739  *           only 4 bits wide).
1740  * PID_QUEUE: Part of PID_TYPE, this is the queue index number (0-3)
1741  * PID_ENTRY: Part of PID_TYPE, this is the queue entry index number (1-3)
1742  *            This identification number is calculated by ((idx % 3) + 1).
1743  * TX_SUCCESS: Indicates tx success (1) or failure (0)
1744  * TX_AGGRE: Indicates if the frame was part of an aggregate (1) or not (0)
1745  * TX_ACK_REQUIRED: Indicates if the frame needed to get ack'ed (1) or not (0)
1746  * WCID: The wireless client ID.
1747  * MCS: The tx rate used during the last transmission of this frame, be it
1748  *      successful or not.
1749  * PHYMODE: The phymode used for the transmission.
1750  */
1751 #define TX_STA_FIFO                     0x1718
1752 #define TX_STA_FIFO_VALID               FIELD32(0x00000001)
1753 #define TX_STA_FIFO_PID_TYPE            FIELD32(0x0000001e)
1754 #define TX_STA_FIFO_PID_QUEUE           FIELD32(0x00000006)
1755 #define TX_STA_FIFO_PID_ENTRY           FIELD32(0x00000018)
1756 #define TX_STA_FIFO_TX_SUCCESS          FIELD32(0x00000020)
1757 #define TX_STA_FIFO_TX_AGGRE            FIELD32(0x00000040)
1758 #define TX_STA_FIFO_TX_ACK_REQUIRED     FIELD32(0x00000080)
1759 #define TX_STA_FIFO_WCID                FIELD32(0x0000ff00)
1760 #define TX_STA_FIFO_SUCCESS_RATE        FIELD32(0xffff0000)
1761 #define TX_STA_FIFO_MCS                 FIELD32(0x007f0000)
1762 #define TX_STA_FIFO_PHYMODE             FIELD32(0xc0000000)
1763
1764 /*
1765  * TX_AGG_CNT: Debug counter
1766  */
1767 #define TX_AGG_CNT                      0x171c
1768 #define TX_AGG_CNT_NON_AGG_TX_COUNT     FIELD32(0x0000ffff)
1769 #define TX_AGG_CNT_AGG_TX_COUNT         FIELD32(0xffff0000)
1770
1771 /*
1772  * TX_AGG_CNT0:
1773  */
1774 #define TX_AGG_CNT0                     0x1720
1775 #define TX_AGG_CNT0_AGG_SIZE_1_COUNT    FIELD32(0x0000ffff)
1776 #define TX_AGG_CNT0_AGG_SIZE_2_COUNT    FIELD32(0xffff0000)
1777
1778 /*
1779  * TX_AGG_CNT1:
1780  */
1781 #define TX_AGG_CNT1                     0x1724
1782 #define TX_AGG_CNT1_AGG_SIZE_3_COUNT    FIELD32(0x0000ffff)
1783 #define TX_AGG_CNT1_AGG_SIZE_4_COUNT    FIELD32(0xffff0000)
1784
1785 /*
1786  * TX_AGG_CNT2:
1787  */
1788 #define TX_AGG_CNT2                     0x1728
1789 #define TX_AGG_CNT2_AGG_SIZE_5_COUNT    FIELD32(0x0000ffff)
1790 #define TX_AGG_CNT2_AGG_SIZE_6_COUNT    FIELD32(0xffff0000)
1791
1792 /*
1793  * TX_AGG_CNT3:
1794  */
1795 #define TX_AGG_CNT3                     0x172c
1796 #define TX_AGG_CNT3_AGG_SIZE_7_COUNT    FIELD32(0x0000ffff)
1797 #define TX_AGG_CNT3_AGG_SIZE_8_COUNT    FIELD32(0xffff0000)
1798
1799 /*
1800  * TX_AGG_CNT4:
1801  */
1802 #define TX_AGG_CNT4                     0x1730
1803 #define TX_AGG_CNT4_AGG_SIZE_9_COUNT    FIELD32(0x0000ffff)
1804 #define TX_AGG_CNT4_AGG_SIZE_10_COUNT   FIELD32(0xffff0000)
1805
1806 /*
1807  * TX_AGG_CNT5:
1808  */
1809 #define TX_AGG_CNT5                     0x1734
1810 #define TX_AGG_CNT5_AGG_SIZE_11_COUNT   FIELD32(0x0000ffff)
1811 #define TX_AGG_CNT5_AGG_SIZE_12_COUNT   FIELD32(0xffff0000)
1812
1813 /*
1814  * TX_AGG_CNT6:
1815  */
1816 #define TX_AGG_CNT6                     0x1738
1817 #define TX_AGG_CNT6_AGG_SIZE_13_COUNT   FIELD32(0x0000ffff)
1818 #define TX_AGG_CNT6_AGG_SIZE_14_COUNT   FIELD32(0xffff0000)
1819
1820 /*
1821  * TX_AGG_CNT7:
1822  */
1823 #define TX_AGG_CNT7                     0x173c
1824 #define TX_AGG_CNT7_AGG_SIZE_15_COUNT   FIELD32(0x0000ffff)
1825 #define TX_AGG_CNT7_AGG_SIZE_16_COUNT   FIELD32(0xffff0000)
1826
1827 /*
1828  * MPDU_DENSITY_CNT:
1829  * TX_ZERO_DEL: TX zero length delimiter count
1830  * RX_ZERO_DEL: RX zero length delimiter count
1831  */
1832 #define MPDU_DENSITY_CNT                0x1740
1833 #define MPDU_DENSITY_CNT_TX_ZERO_DEL    FIELD32(0x0000ffff)
1834 #define MPDU_DENSITY_CNT_RX_ZERO_DEL    FIELD32(0xffff0000)
1835
1836 /*
1837  * Security key table memory.
1838  *
1839  * The pairwise key table shares some memory with the beacon frame
1840  * buffers 6 and 7. That basically means that when beacon 6 & 7
1841  * are used we should only use the reduced pairwise key table which
1842  * has a maximum of 222 entries.
1843  *
1844  * ---------------------------------------------
1845  * |0x4000 | Pairwise Key   | Reduced Pairwise |
1846  * |       | Table          | Key Table        |
1847  * |       | Size: 256 * 32 | Size: 222 * 32   |
1848  * |0x5BC0 |                |-------------------
1849  * |       |                | Beacon 6         |
1850  * |0x5DC0 |                |-------------------
1851  * |       |                | Beacon 7         |
1852  * |0x5FC0 |                |-------------------
1853  * |0x5FFF |                |
1854  * --------------------------
1855  *
1856  * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
1857  * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
1858  * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
1859  * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
1860  * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
1861  * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
1862  */
1863 #define MAC_WCID_BASE                   0x1800
1864 #define PAIRWISE_KEY_TABLE_BASE         0x4000
1865 #define MAC_IVEIV_TABLE_BASE            0x6000
1866 #define MAC_WCID_ATTRIBUTE_BASE         0x6800
1867 #define SHARED_KEY_TABLE_BASE           0x6c00
1868 #define SHARED_KEY_MODE_BASE            0x7000
1869
1870 #define MAC_WCID_ENTRY(__idx) \
1871         (MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)))
1872 #define PAIRWISE_KEY_ENTRY(__idx) \
1873         (PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
1874 #define MAC_IVEIV_ENTRY(__idx) \
1875         (MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry)))
1876 #define MAC_WCID_ATTR_ENTRY(__idx) \
1877         (MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)))
1878 #define SHARED_KEY_ENTRY(__idx) \
1879         (SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
1880 #define SHARED_KEY_MODE_ENTRY(__idx) \
1881         (SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)))
1882
1883 struct mac_wcid_entry {
1884         u8 mac[6];
1885         u8 reserved[2];
1886 } __packed;
1887
1888 struct hw_key_entry {
1889         u8 key[16];
1890         u8 tx_mic[8];
1891         u8 rx_mic[8];
1892 } __packed;
1893
1894 struct mac_iveiv_entry {
1895         u8 iv[8];
1896 } __packed;
1897
1898 /*
1899  * MAC_WCID_ATTRIBUTE:
1900  */
1901 #define MAC_WCID_ATTRIBUTE_KEYTAB       FIELD32(0x00000001)
1902 #define MAC_WCID_ATTRIBUTE_CIPHER       FIELD32(0x0000000e)
1903 #define MAC_WCID_ATTRIBUTE_BSS_IDX      FIELD32(0x00000070)
1904 #define MAC_WCID_ATTRIBUTE_RX_WIUDF     FIELD32(0x00000380)
1905 #define MAC_WCID_ATTRIBUTE_CIPHER_EXT   FIELD32(0x00000400)
1906 #define MAC_WCID_ATTRIBUTE_BSS_IDX_EXT  FIELD32(0x00000800)
1907 #define MAC_WCID_ATTRIBUTE_WAPI_MCBC    FIELD32(0x00008000)
1908 #define MAC_WCID_ATTRIBUTE_WAPI_KEY_IDX FIELD32(0xff000000)
1909
1910 /*
1911  * SHARED_KEY_MODE:
1912  */
1913 #define SHARED_KEY_MODE_BSS0_KEY0       FIELD32(0x00000007)
1914 #define SHARED_KEY_MODE_BSS0_KEY1       FIELD32(0x00000070)
1915 #define SHARED_KEY_MODE_BSS0_KEY2       FIELD32(0x00000700)
1916 #define SHARED_KEY_MODE_BSS0_KEY3       FIELD32(0x00007000)
1917 #define SHARED_KEY_MODE_BSS1_KEY0       FIELD32(0x00070000)
1918 #define SHARED_KEY_MODE_BSS1_KEY1       FIELD32(0x00700000)
1919 #define SHARED_KEY_MODE_BSS1_KEY2       FIELD32(0x07000000)
1920 #define SHARED_KEY_MODE_BSS1_KEY3       FIELD32(0x70000000)
1921
1922 /*
1923  * HOST-MCU communication
1924  */
1925
1926 /*
1927  * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
1928  * CMD_TOKEN: Command id, 0xff disable status reporting.
1929  */
1930 #define H2M_MAILBOX_CSR                 0x7010
1931 #define H2M_MAILBOX_CSR_ARG0            FIELD32(0x000000ff)
1932 #define H2M_MAILBOX_CSR_ARG1            FIELD32(0x0000ff00)
1933 #define H2M_MAILBOX_CSR_CMD_TOKEN       FIELD32(0x00ff0000)
1934 #define H2M_MAILBOX_CSR_OWNER           FIELD32(0xff000000)
1935
1936 /*
1937  * H2M_MAILBOX_CID:
1938  * Free slots contain 0xff. MCU will store command's token to lowest free slot.
1939  * If all slots are occupied status will be dropped.
1940  */
1941 #define H2M_MAILBOX_CID                 0x7014
1942 #define H2M_MAILBOX_CID_CMD0            FIELD32(0x000000ff)
1943 #define H2M_MAILBOX_CID_CMD1            FIELD32(0x0000ff00)
1944 #define H2M_MAILBOX_CID_CMD2            FIELD32(0x00ff0000)
1945 #define H2M_MAILBOX_CID_CMD3            FIELD32(0xff000000)
1946
1947 /*
1948  * H2M_MAILBOX_STATUS:
1949  * Command status will be saved to same slot as command id.
1950  */
1951 #define H2M_MAILBOX_STATUS              0x701c
1952
1953 /*
1954  * H2M_INT_SRC:
1955  */
1956 #define H2M_INT_SRC                     0x7024
1957
1958 /*
1959  * H2M_BBP_AGENT:
1960  */
1961 #define H2M_BBP_AGENT                   0x7028
1962
1963 /*
1964  * MCU_LEDCS: LED control for MCU Mailbox.
1965  */
1966 #define MCU_LEDCS_LED_MODE              FIELD8(0x1f)
1967 #define MCU_LEDCS_POLARITY              FIELD8(0x01)
1968
1969 /*
1970  * HW_CS_CTS_BASE:
1971  * Carrier-sense CTS frame base address.
1972  * It's where mac stores carrier-sense frame for carrier-sense function.
1973  */
1974 #define HW_CS_CTS_BASE                  0x7700
1975
1976 /*
1977  * HW_DFS_CTS_BASE:
1978  * DFS CTS frame base address. It's where mac stores CTS frame for DFS.
1979  */
1980 #define HW_DFS_CTS_BASE                 0x7780
1981
1982 /*
1983  * TXRX control registers - base address 0x3000
1984  */
1985
1986 /*
1987  * TXRX_CSR1:
1988  * rt2860b  UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1989  */
1990 #define TXRX_CSR1                       0x77d0
1991
1992 /*
1993  * HW_DEBUG_SETTING_BASE:
1994  * since NULL frame won't be that long (256 byte)
1995  * We steal 16 tail bytes to save debugging settings
1996  */
1997 #define HW_DEBUG_SETTING_BASE           0x77f0
1998 #define HW_DEBUG_SETTING_BASE2          0x7770
1999
2000 /*
2001  * HW_BEACON_BASE
2002  * In order to support maximum 8 MBSS and its maximum length
2003  * is 512 bytes for each beacon
2004  * Three section discontinue memory segments will be used.
2005  * 1. The original region for BCN 0~3
2006  * 2. Extract memory from FCE table for BCN 4~5
2007  * 3. Extract memory from Pair-wise key table for BCN 6~7
2008  *    It occupied those memory of wcid 238~253 for BCN 6
2009  *    and wcid 222~237 for BCN 7 (see Security key table memory
2010  *    for more info).
2011  *
2012  * IMPORTANT NOTE: Not sure why legacy driver does this,
2013  * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
2014  */
2015 #define HW_BEACON_BASE0                 0x7800
2016 #define HW_BEACON_BASE1                 0x7a00
2017 #define HW_BEACON_BASE2                 0x7c00
2018 #define HW_BEACON_BASE3                 0x7e00
2019 #define HW_BEACON_BASE4                 0x7200
2020 #define HW_BEACON_BASE5                 0x7400
2021 #define HW_BEACON_BASE6                 0x5dc0
2022 #define HW_BEACON_BASE7                 0x5bc0
2023
2024 #define HW_BEACON_BASE(__index) \
2025         (((__index) < 4) ? (HW_BEACON_BASE0 + (__index * 0x0200)) : \
2026           (((__index) < 6) ? (HW_BEACON_BASE4 + ((__index - 4) * 0x0200)) : \
2027           (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))))
2028
2029 #define BEACON_BASE_TO_OFFSET(_base)    (((_base) - 0x4000) / 64)
2030
2031 /*
2032  * BBP registers.
2033  * The wordsize of the BBP is 8 bits.
2034  */
2035
2036 /*
2037  * BBP 1: TX Antenna & Power Control
2038  * POWER_CTRL:
2039  * 0 - normal,
2040  * 1 - drop tx power by 6dBm,
2041  * 2 - drop tx power by 12dBm,
2042  * 3 - increase tx power by 6dBm
2043  */
2044 #define BBP1_TX_POWER_CTRL              FIELD8(0x03)
2045 #define BBP1_TX_ANTENNA                 FIELD8(0x18)
2046
2047 /*
2048  * BBP 3: RX Antenna
2049  */
2050 #define BBP3_RX_ADC                     FIELD8(0x03)
2051 #define BBP3_RX_ANTENNA                 FIELD8(0x18)
2052 #define BBP3_HT40_MINUS                 FIELD8(0x20)
2053 #define BBP3_ADC_MODE_SWITCH            FIELD8(0x40)
2054 #define BBP3_ADC_INIT_MODE              FIELD8(0x80)
2055
2056 /*
2057  * BBP 4: Bandwidth
2058  */
2059 #define BBP4_TX_BF                      FIELD8(0x01)
2060 #define BBP4_BANDWIDTH                  FIELD8(0x18)
2061 #define BBP4_MAC_IF_CTRL                FIELD8(0x40)
2062
2063 /* BBP27 */
2064 #define BBP27_RX_CHAIN_SEL              FIELD8(0x60)
2065
2066 /*
2067  * BBP 47: Bandwidth
2068  */
2069 #define BBP47_TSSI_REPORT_SEL           FIELD8(0x03)
2070 #define BBP47_TSSI_UPDATE_REQ           FIELD8(0x04)
2071 #define BBP47_TSSI_TSSI_MODE            FIELD8(0x18)
2072 #define BBP47_TSSI_ADC6                 FIELD8(0x80)
2073
2074 /*
2075  * BBP 49
2076  */
2077 #define BBP49_UPDATE_FLAG               FIELD8(0x01)
2078
2079 /*
2080  * BBP 105:
2081  * - bit0: detect SIG on primary channel only (on 40MHz bandwidth)
2082  * - bit1: FEQ (Feed Forward Compensation) for independend streams
2083  * - bit2: MLD (Maximum Likehood Detection) for 2 streams (reserved on single
2084  *         stream)
2085  * - bit4: channel estimation updates based on remodulation of
2086  *         L-SIG and HT-SIG symbols
2087  */
2088 #define BBP105_DETECT_SIG_ON_PRIMARY    FIELD8(0x01)
2089 #define BBP105_FEQ                      FIELD8(0x02)
2090 #define BBP105_MLD                      FIELD8(0x04)
2091 #define BBP105_SIG_REMODULATION         FIELD8(0x08)
2092
2093 /*
2094  * BBP 109
2095  */
2096 #define BBP109_TX0_POWER                FIELD8(0x0f)
2097 #define BBP109_TX1_POWER                FIELD8(0xf0)
2098
2099 /* BBP 110 */
2100 #define BBP110_TX2_POWER                FIELD8(0x0f)
2101
2102
2103 /*
2104  * BBP 138: Unknown
2105  */
2106 #define BBP138_RX_ADC1                  FIELD8(0x02)
2107 #define BBP138_RX_ADC2                  FIELD8(0x04)
2108 #define BBP138_TX_DAC1                  FIELD8(0x20)
2109 #define BBP138_TX_DAC2                  FIELD8(0x40)
2110
2111 /*
2112  * BBP 152: Rx Ant
2113  */
2114 #define BBP152_RX_DEFAULT_ANT           FIELD8(0x80)
2115
2116 /*
2117  * BBP 254: unknown
2118  */
2119 #define BBP254_BIT7                     FIELD8(0x80)
2120
2121 /*
2122  * RFCSR registers
2123  * The wordsize of the RFCSR is 8 bits.
2124  */
2125
2126 /*
2127  * RFCSR 1:
2128  */
2129 #define RFCSR1_RF_BLOCK_EN              FIELD8(0x01)
2130 #define RFCSR1_PLL_PD                   FIELD8(0x02)
2131 #define RFCSR1_RX0_PD                   FIELD8(0x04)
2132 #define RFCSR1_TX0_PD                   FIELD8(0x08)
2133 #define RFCSR1_RX1_PD                   FIELD8(0x10)
2134 #define RFCSR1_TX1_PD                   FIELD8(0x20)
2135 #define RFCSR1_RX2_PD                   FIELD8(0x40)
2136 #define RFCSR1_TX2_PD                   FIELD8(0x80)
2137
2138 /*
2139  * RFCSR 2:
2140  */
2141 #define RFCSR2_RESCAL_EN                FIELD8(0x80)
2142
2143 /*
2144  * RFCSR 3:
2145  */
2146 #define RFCSR3_K                        FIELD8(0x0f)
2147 /* Bits [7-4] for RF3320 (RT3370/RT3390), on other chipsets reserved */
2148 #define RFCSR3_PA1_BIAS_CCK             FIELD8(0x70)
2149 #define RFCSR3_PA2_CASCODE_BIAS_CCKK    FIELD8(0x80)
2150 /* Bits for RF3290/RF5360/RF5362/RF5370/RF5372/RF5390/RF5392 */
2151 #define RFCSR3_VCOCAL_EN                FIELD8(0x80)
2152 /* Bits for RF3050 */
2153 #define RFCSR3_BIT1                     FIELD8(0x02)
2154 #define RFCSR3_BIT2                     FIELD8(0x04)
2155 #define RFCSR3_BIT3                     FIELD8(0x08)
2156 #define RFCSR3_BIT4                     FIELD8(0x10)
2157 #define RFCSR3_BIT5                     FIELD8(0x20)
2158
2159 /*
2160  * FRCSR 5:
2161  */
2162 #define RFCSR5_R1                       FIELD8(0x0c)
2163
2164 /*
2165  * RFCSR 6:
2166  */
2167 #define RFCSR6_R1                       FIELD8(0x03)
2168 #define RFCSR6_R2                       FIELD8(0x40)
2169 #define RFCSR6_TXDIV                    FIELD8(0x0c)
2170 /* bits for RF3053 */
2171 #define RFCSR6_VCO_IC                   FIELD8(0xc0)
2172
2173 /*
2174  * RFCSR 7:
2175  */
2176 #define RFCSR7_RF_TUNING                FIELD8(0x01)
2177 #define RFCSR7_BIT1                     FIELD8(0x02)
2178 #define RFCSR7_BIT2                     FIELD8(0x04)
2179 #define RFCSR7_BIT3                     FIELD8(0x08)
2180 #define RFCSR7_BIT4                     FIELD8(0x10)
2181 #define RFCSR7_BIT5                     FIELD8(0x20)
2182 #define RFCSR7_BITS67                   FIELD8(0xc0)
2183
2184 /*
2185  * RFCSR 9:
2186  */
2187 #define RFCSR9_K                        FIELD8(0x0f)
2188 #define RFCSR9_N                        FIELD8(0x10)
2189 #define RFCSR9_UNKNOWN                  FIELD8(0x60)
2190 #define RFCSR9_MOD                      FIELD8(0x80)
2191
2192 /*
2193  * RFCSR 11:
2194  */
2195 #define RFCSR11_R                       FIELD8(0x03)
2196 #define RFCSR11_PLL_MOD                 FIELD8(0x0c)
2197 #define RFCSR11_MOD                     FIELD8(0xc0)
2198 /* bits for RF3053 */
2199 /* TODO: verify RFCSR11_MOD usage on other chips */
2200 #define RFCSR11_PLL_IDOH                FIELD8(0x40)
2201
2202
2203 /*
2204  * RFCSR 12:
2205  */
2206 #define RFCSR12_TX_POWER                FIELD8(0x1f)
2207 #define RFCSR12_DR0                     FIELD8(0xe0)
2208
2209 /*
2210  * RFCSR 13:
2211  */
2212 #define RFCSR13_TX_POWER                FIELD8(0x1f)
2213 #define RFCSR13_DR0                     FIELD8(0xe0)
2214
2215 /*
2216  * RFCSR 15:
2217  */
2218 #define RFCSR15_TX_LO2_EN               FIELD8(0x08)
2219
2220 /*
2221  * RFCSR 16:
2222  */
2223 #define RFCSR16_TXMIXER_GAIN            FIELD8(0x07)
2224
2225 /*
2226  * RFCSR 17:
2227  */
2228 #define RFCSR17_TXMIXER_GAIN            FIELD8(0x07)
2229 #define RFCSR17_TX_LO1_EN               FIELD8(0x08)
2230 #define RFCSR17_R                       FIELD8(0x20)
2231 #define RFCSR17_CODE                    FIELD8(0x7f)
2232
2233 /* RFCSR 18 */
2234 #define RFCSR18_XO_TUNE_BYPASS          FIELD8(0x40)
2235
2236
2237 /*
2238  * RFCSR 20:
2239  */
2240 #define RFCSR20_RX_LO1_EN               FIELD8(0x08)
2241
2242 /*
2243  * RFCSR 21:
2244  */
2245 #define RFCSR21_RX_LO2_EN               FIELD8(0x08)
2246
2247 /*
2248  * RFCSR 22:
2249  */
2250 #define RFCSR22_BASEBAND_LOOPBACK       FIELD8(0x01)
2251
2252 /*
2253  * RFCSR 23:
2254  */
2255 #define RFCSR23_FREQ_OFFSET             FIELD8(0x7f)
2256
2257 /*
2258  * RFCSR 24:
2259  */
2260 #define RFCSR24_TX_AGC_FC               FIELD8(0x1f)
2261 #define RFCSR24_TX_H20M                 FIELD8(0x20)
2262 #define RFCSR24_TX_CALIB                FIELD8(0x7f)
2263
2264 /*
2265  * RFCSR 27:
2266  */
2267 #define RFCSR27_R1                      FIELD8(0x03)
2268 #define RFCSR27_R2                      FIELD8(0x04)
2269 #define RFCSR27_R3                      FIELD8(0x30)
2270 #define RFCSR27_R4                      FIELD8(0x40)
2271
2272 /*
2273  * RFCSR 29:
2274  */
2275 #define RFCSR29_ADC6_TEST               FIELD8(0x01)
2276 #define RFCSR29_ADC6_INT_TEST           FIELD8(0x02)
2277 #define RFCSR29_RSSI_RESET              FIELD8(0x04)
2278 #define RFCSR29_RSSI_ON                 FIELD8(0x08)
2279 #define RFCSR29_RSSI_RIP_CTRL           FIELD8(0x30)
2280 #define RFCSR29_RSSI_GAIN               FIELD8(0xc0)
2281
2282 /*
2283  * RFCSR 30:
2284  */
2285 #define RFCSR30_TX_H20M                 FIELD8(0x02)
2286 #define RFCSR30_RX_H20M                 FIELD8(0x04)
2287 #define RFCSR30_RX_VCM                  FIELD8(0x18)
2288 #define RFCSR30_RF_CALIBRATION          FIELD8(0x80)
2289
2290 /*
2291  * RFCSR 31:
2292  */
2293 #define RFCSR31_RX_AGC_FC               FIELD8(0x1f)
2294 #define RFCSR31_RX_H20M                 FIELD8(0x20)
2295 #define RFCSR31_RX_CALIB                FIELD8(0x7f)
2296
2297 /* RFCSR 32 bits for RF3053 */
2298 #define RFCSR32_TX_AGC_FC               FIELD8(0xf8)
2299
2300 /* RFCSR 36 bits for RF3053 */
2301 #define RFCSR36_RF_BS                   FIELD8(0x80)
2302
2303 /*
2304  * RFCSR 38:
2305  */
2306 #define RFCSR38_RX_LO1_EN               FIELD8(0x20)
2307
2308 /*
2309  * RFCSR 39:
2310  */
2311 #define RFCSR39_RX_DIV                  FIELD8(0x40)
2312 #define RFCSR39_RX_LO2_EN               FIELD8(0x80)
2313
2314 /*
2315  * RFCSR 49:
2316  */
2317 #define RFCSR49_TX                      FIELD8(0x3f)
2318 #define RFCSR49_EP                      FIELD8(0xc0)
2319 /* bits for RT3593 */
2320 #define RFCSR49_TX_LO1_IC               FIELD8(0x1c)
2321 #define RFCSR49_TX_DIV                  FIELD8(0x20)
2322
2323 /*
2324  * RFCSR 50:
2325  */
2326 #define RFCSR50_TX                      FIELD8(0x3f)
2327 #define RFCSR50_EP                      FIELD8(0xc0)
2328 /* bits for RT3593 */
2329 #define RFCSR50_TX_LO1_EN               FIELD8(0x20)
2330 #define RFCSR50_TX_LO2_EN               FIELD8(0x10)
2331
2332 /* RFCSR 51 */
2333 /* bits for RT3593 */
2334 #define RFCSR51_BITS01                  FIELD8(0x03)
2335 #define RFCSR51_BITS24                  FIELD8(0x1c)
2336 #define RFCSR51_BITS57                  FIELD8(0xe0)
2337
2338 #define RFCSR53_TX_POWER                FIELD8(0x3f)
2339 #define RFCSR53_UNKNOWN                 FIELD8(0xc0)
2340
2341 #define RFCSR54_TX_POWER                FIELD8(0x3f)
2342 #define RFCSR54_UNKNOWN                 FIELD8(0xc0)
2343
2344 #define RFCSR55_TX_POWER                FIELD8(0x3f)
2345 #define RFCSR55_UNKNOWN                 FIELD8(0xc0)
2346
2347 #define RFCSR57_DRV_CC                  FIELD8(0xfc)
2348
2349
2350 /*
2351  * RF registers
2352  */
2353
2354 /*
2355  * RF 2
2356  */
2357 #define RF2_ANTENNA_RX2                 FIELD32(0x00000040)
2358 #define RF2_ANTENNA_TX1                 FIELD32(0x00004000)
2359 #define RF2_ANTENNA_RX1                 FIELD32(0x00020000)
2360
2361 /*
2362  * RF 3
2363  */
2364 #define RF3_TXPOWER_G                   FIELD32(0x00003e00)
2365 #define RF3_TXPOWER_A_7DBM_BOOST        FIELD32(0x00000200)
2366 #define RF3_TXPOWER_A                   FIELD32(0x00003c00)
2367
2368 /*
2369  * RF 4
2370  */
2371 #define RF4_TXPOWER_G                   FIELD32(0x000007c0)
2372 #define RF4_TXPOWER_A_7DBM_BOOST        FIELD32(0x00000040)
2373 #define RF4_TXPOWER_A                   FIELD32(0x00000780)
2374 #define RF4_FREQ_OFFSET                 FIELD32(0x001f8000)
2375 #define RF4_HT40                        FIELD32(0x00200000)
2376
2377 /*
2378  * EEPROM content.
2379  * The wordsize of the EEPROM is 16 bits.
2380  */
2381
2382 enum rt2800_eeprom_word {
2383         EEPROM_CHIP_ID = 0,
2384         EEPROM_VERSION,
2385         EEPROM_MAC_ADDR_0,
2386         EEPROM_MAC_ADDR_1,
2387         EEPROM_MAC_ADDR_2,
2388         EEPROM_NIC_CONF0,
2389         EEPROM_NIC_CONF1,
2390         EEPROM_FREQ,
2391         EEPROM_LED_AG_CONF,
2392         EEPROM_LED_ACT_CONF,
2393         EEPROM_LED_POLARITY,
2394         EEPROM_NIC_CONF2,
2395         EEPROM_LNA,
2396         EEPROM_RSSI_BG,
2397         EEPROM_RSSI_BG2,
2398         EEPROM_TXMIXER_GAIN_BG,
2399         EEPROM_RSSI_A,
2400         EEPROM_RSSI_A2,
2401         EEPROM_TXMIXER_GAIN_A,
2402         EEPROM_EIRP_MAX_TX_POWER,
2403         EEPROM_TXPOWER_DELTA,
2404         EEPROM_TXPOWER_BG1,
2405         EEPROM_TXPOWER_BG2,
2406         EEPROM_TSSI_BOUND_BG1,
2407         EEPROM_TSSI_BOUND_BG2,
2408         EEPROM_TSSI_BOUND_BG3,
2409         EEPROM_TSSI_BOUND_BG4,
2410         EEPROM_TSSI_BOUND_BG5,
2411         EEPROM_TXPOWER_A1,
2412         EEPROM_TXPOWER_A2,
2413         EEPROM_TSSI_BOUND_A1,
2414         EEPROM_TSSI_BOUND_A2,
2415         EEPROM_TSSI_BOUND_A3,
2416         EEPROM_TSSI_BOUND_A4,
2417         EEPROM_TSSI_BOUND_A5,
2418         EEPROM_TXPOWER_BYRATE,
2419         EEPROM_BBP_START,
2420
2421         /* IDs for extended EEPROM format used by three-chain devices */
2422         EEPROM_EXT_LNA2,
2423         EEPROM_EXT_TXPOWER_BG3,
2424         EEPROM_EXT_TXPOWER_A3,
2425
2426         /* New values must be added before this */
2427         EEPROM_WORD_COUNT
2428 };
2429
2430 /*
2431  * EEPROM Version
2432  */
2433 #define EEPROM_VERSION_FAE              FIELD16(0x00ff)
2434 #define EEPROM_VERSION_VERSION          FIELD16(0xff00)
2435
2436 /*
2437  * HW MAC address.
2438  */
2439 #define EEPROM_MAC_ADDR_BYTE0           FIELD16(0x00ff)
2440 #define EEPROM_MAC_ADDR_BYTE1           FIELD16(0xff00)
2441 #define EEPROM_MAC_ADDR_BYTE2           FIELD16(0x00ff)
2442 #define EEPROM_MAC_ADDR_BYTE3           FIELD16(0xff00)
2443 #define EEPROM_MAC_ADDR_BYTE4           FIELD16(0x00ff)
2444 #define EEPROM_MAC_ADDR_BYTE5           FIELD16(0xff00)
2445
2446 /*
2447  * EEPROM NIC Configuration 0
2448  * RXPATH: 1: 1R, 2: 2R, 3: 3R
2449  * TXPATH: 1: 1T, 2: 2T, 3: 3T
2450  * RF_TYPE: RFIC type
2451  */
2452 #define EEPROM_NIC_CONF0_RXPATH         FIELD16(0x000f)
2453 #define EEPROM_NIC_CONF0_TXPATH         FIELD16(0x00f0)
2454 #define EEPROM_NIC_CONF0_RF_TYPE        FIELD16(0x0f00)
2455
2456 /*
2457  * EEPROM NIC Configuration 1
2458  * HW_RADIO: 0: disable, 1: enable
2459  * EXTERNAL_TX_ALC: 0: disable, 1: enable
2460  * EXTERNAL_LNA_2G: 0: disable, 1: enable
2461  * EXTERNAL_LNA_5G: 0: disable, 1: enable
2462  * CARDBUS_ACCEL: 0: enable, 1: disable
2463  * BW40M_SB_2G: 0: disable, 1: enable
2464  * BW40M_SB_5G: 0: disable, 1: enable
2465  * WPS_PBC: 0: disable, 1: enable
2466  * BW40M_2G: 0: enable, 1: disable
2467  * BW40M_5G: 0: enable, 1: disable
2468  * BROADBAND_EXT_LNA: 0: disable, 1: enable
2469  * ANT_DIVERSITY: 00: Disable, 01: Diversity,
2470  *                                10: Main antenna, 11: Aux antenna
2471  * INTERNAL_TX_ALC: 0: disable, 1: enable
2472  * BT_COEXIST: 0: disable, 1: enable
2473  * DAC_TEST: 0: disable, 1: enable
2474  */
2475 #define EEPROM_NIC_CONF1_HW_RADIO               FIELD16(0x0001)
2476 #define EEPROM_NIC_CONF1_EXTERNAL_TX_ALC        FIELD16(0x0002)
2477 #define EEPROM_NIC_CONF1_EXTERNAL_LNA_2G        FIELD16(0x0004)
2478 #define EEPROM_NIC_CONF1_EXTERNAL_LNA_5G        FIELD16(0x0008)
2479 #define EEPROM_NIC_CONF1_CARDBUS_ACCEL          FIELD16(0x0010)
2480 #define EEPROM_NIC_CONF1_BW40M_SB_2G            FIELD16(0x0020)
2481 #define EEPROM_NIC_CONF1_BW40M_SB_5G            FIELD16(0x0040)
2482 #define EEPROM_NIC_CONF1_WPS_PBC                FIELD16(0x0080)
2483 #define EEPROM_NIC_CONF1_BW40M_2G               FIELD16(0x0100)
2484 #define EEPROM_NIC_CONF1_BW40M_5G               FIELD16(0x0200)
2485 #define EEPROM_NIC_CONF1_BROADBAND_EXT_LNA      FIELD16(0x400)
2486 #define EEPROM_NIC_CONF1_ANT_DIVERSITY          FIELD16(0x1800)
2487 #define EEPROM_NIC_CONF1_INTERNAL_TX_ALC        FIELD16(0x2000)
2488 #define EEPROM_NIC_CONF1_BT_COEXIST             FIELD16(0x4000)
2489 #define EEPROM_NIC_CONF1_DAC_TEST               FIELD16(0x8000)
2490
2491 /*
2492  * EEPROM frequency
2493  */
2494 #define EEPROM_FREQ_OFFSET              FIELD16(0x00ff)
2495 #define EEPROM_FREQ_LED_MODE            FIELD16(0x7f00)
2496 #define EEPROM_FREQ_LED_POLARITY        FIELD16(0x1000)
2497
2498 /*
2499  * EEPROM LED
2500  * POLARITY_RDY_G: Polarity RDY_G setting.
2501  * POLARITY_RDY_A: Polarity RDY_A setting.
2502  * POLARITY_ACT: Polarity ACT setting.
2503  * POLARITY_GPIO_0: Polarity GPIO0 setting.
2504  * POLARITY_GPIO_1: Polarity GPIO1 setting.
2505  * POLARITY_GPIO_2: Polarity GPIO2 setting.
2506  * POLARITY_GPIO_3: Polarity GPIO3 setting.
2507  * POLARITY_GPIO_4: Polarity GPIO4 setting.
2508  * LED_MODE: Led mode.
2509  */
2510 #define EEPROM_LED_POLARITY_RDY_BG      FIELD16(0x0001)
2511 #define EEPROM_LED_POLARITY_RDY_A       FIELD16(0x0002)
2512 #define EEPROM_LED_POLARITY_ACT         FIELD16(0x0004)
2513 #define EEPROM_LED_POLARITY_GPIO_0      FIELD16(0x0008)
2514 #define EEPROM_LED_POLARITY_GPIO_1      FIELD16(0x0010)
2515 #define EEPROM_LED_POLARITY_GPIO_2      FIELD16(0x0020)
2516 #define EEPROM_LED_POLARITY_GPIO_3      FIELD16(0x0040)
2517 #define EEPROM_LED_POLARITY_GPIO_4      FIELD16(0x0080)
2518 #define EEPROM_LED_LED_MODE             FIELD16(0x1f00)
2519
2520 /*
2521  * EEPROM NIC Configuration 2
2522  * RX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
2523  * TX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
2524  * CRYSTAL: 00: Reserved, 01: One crystal, 10: Two crystal, 11: Reserved
2525  */
2526 #define EEPROM_NIC_CONF2_RX_STREAM      FIELD16(0x000f)
2527 #define EEPROM_NIC_CONF2_TX_STREAM      FIELD16(0x00f0)
2528 #define EEPROM_NIC_CONF2_CRYSTAL        FIELD16(0x0600)
2529
2530 /*
2531  * EEPROM LNA
2532  */
2533 #define EEPROM_LNA_BG                   FIELD16(0x00ff)
2534 #define EEPROM_LNA_A0                   FIELD16(0xff00)
2535
2536 /*
2537  * EEPROM RSSI BG offset
2538  */
2539 #define EEPROM_RSSI_BG_OFFSET0          FIELD16(0x00ff)
2540 #define EEPROM_RSSI_BG_OFFSET1          FIELD16(0xff00)
2541
2542 /*
2543  * EEPROM RSSI BG2 offset
2544  */
2545 #define EEPROM_RSSI_BG2_OFFSET2         FIELD16(0x00ff)
2546 #define EEPROM_RSSI_BG2_LNA_A1          FIELD16(0xff00)
2547
2548 /*
2549  * EEPROM TXMIXER GAIN BG offset (note overlaps with EEPROM RSSI BG2).
2550  */
2551 #define EEPROM_TXMIXER_GAIN_BG_VAL      FIELD16(0x0007)
2552
2553 /*
2554  * EEPROM RSSI A offset
2555  */
2556 #define EEPROM_RSSI_A_OFFSET0           FIELD16(0x00ff)
2557 #define EEPROM_RSSI_A_OFFSET1           FIELD16(0xff00)
2558
2559 /*
2560  * EEPROM RSSI A2 offset
2561  */
2562 #define EEPROM_RSSI_A2_OFFSET2          FIELD16(0x00ff)
2563 #define EEPROM_RSSI_A2_LNA_A2           FIELD16(0xff00)
2564
2565 /*
2566  * EEPROM TXMIXER GAIN A offset (note overlaps with EEPROM RSSI A2).
2567  */
2568 #define EEPROM_TXMIXER_GAIN_A_VAL       FIELD16(0x0007)
2569
2570 /*
2571  * EEPROM EIRP Maximum TX power values(unit: dbm)
2572  */
2573 #define EEPROM_EIRP_MAX_TX_POWER_2GHZ   FIELD16(0x00ff)
2574 #define EEPROM_EIRP_MAX_TX_POWER_5GHZ   FIELD16(0xff00)
2575
2576 /*
2577  * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
2578  * This is delta in 40MHZ.
2579  * VALUE: Tx Power dalta value, MAX=4(unit: dbm)
2580  * TYPE: 1: Plus the delta value, 0: minus the delta value
2581  * ENABLE: enable tx power compensation for 40BW
2582  */
2583 #define EEPROM_TXPOWER_DELTA_VALUE_2G   FIELD16(0x003f)
2584 #define EEPROM_TXPOWER_DELTA_TYPE_2G    FIELD16(0x0040)
2585 #define EEPROM_TXPOWER_DELTA_ENABLE_2G  FIELD16(0x0080)
2586 #define EEPROM_TXPOWER_DELTA_VALUE_5G   FIELD16(0x3f00)
2587 #define EEPROM_TXPOWER_DELTA_TYPE_5G    FIELD16(0x4000)
2588 #define EEPROM_TXPOWER_DELTA_ENABLE_5G  FIELD16(0x8000)
2589
2590 /*
2591  * EEPROM TXPOWER 802.11BG
2592  */
2593 #define EEPROM_TXPOWER_BG_SIZE          7
2594 #define EEPROM_TXPOWER_BG_1             FIELD16(0x00ff)
2595 #define EEPROM_TXPOWER_BG_2             FIELD16(0xff00)
2596
2597 /*
2598  * EEPROM temperature compensation boundaries 802.11BG
2599  * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
2600  *         reduced by (agc_step * -4)
2601  * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
2602  *         reduced by (agc_step * -3)
2603  */
2604 #define EEPROM_TSSI_BOUND_BG1_MINUS4    FIELD16(0x00ff)
2605 #define EEPROM_TSSI_BOUND_BG1_MINUS3    FIELD16(0xff00)
2606
2607 /*
2608  * EEPROM temperature compensation boundaries 802.11BG
2609  * MINUS2: If the actual TSSI is below this boundary, tx power needs to be
2610  *         reduced by (agc_step * -2)
2611  * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
2612  *         reduced by (agc_step * -1)
2613  */
2614 #define EEPROM_TSSI_BOUND_BG2_MINUS2    FIELD16(0x00ff)
2615 #define EEPROM_TSSI_BOUND_BG2_MINUS1    FIELD16(0xff00)
2616
2617 /*
2618  * EEPROM temperature compensation boundaries 802.11BG
2619  * REF: Reference TSSI value, no tx power changes needed
2620  * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
2621  *        increased by (agc_step * 1)
2622  */
2623 #define EEPROM_TSSI_BOUND_BG3_REF       FIELD16(0x00ff)
2624 #define EEPROM_TSSI_BOUND_BG3_PLUS1     FIELD16(0xff00)
2625
2626 /*
2627  * EEPROM temperature compensation boundaries 802.11BG
2628  * PLUS2: If the actual TSSI is above this boundary, tx power needs to be
2629  *        increased by (agc_step * 2)
2630  * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
2631  *        increased by (agc_step * 3)
2632  */
2633 #define EEPROM_TSSI_BOUND_BG4_PLUS2     FIELD16(0x00ff)
2634 #define EEPROM_TSSI_BOUND_BG4_PLUS3     FIELD16(0xff00)
2635
2636 /*
2637  * EEPROM temperature compensation boundaries 802.11BG
2638  * PLUS4: If the actual TSSI is above this boundary, tx power needs to be
2639  *        increased by (agc_step * 4)
2640  * AGC_STEP: Temperature compensation step.
2641  */
2642 #define EEPROM_TSSI_BOUND_BG5_PLUS4     FIELD16(0x00ff)
2643 #define EEPROM_TSSI_BOUND_BG5_AGC_STEP  FIELD16(0xff00)
2644
2645 /*
2646  * EEPROM TXPOWER 802.11A
2647  */
2648 #define EEPROM_TXPOWER_A_SIZE           6
2649 #define EEPROM_TXPOWER_A_1              FIELD16(0x00ff)
2650 #define EEPROM_TXPOWER_A_2              FIELD16(0xff00)
2651
2652 /* EEPROM_TXPOWER_{A,G} fields for RT3593 */
2653 #define EEPROM_TXPOWER_ALC              FIELD8(0x1f)
2654 #define EEPROM_TXPOWER_FINE_CTRL        FIELD8(0xe0)
2655
2656 /*
2657  * EEPROM temperature compensation boundaries 802.11A
2658  * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
2659  *         reduced by (agc_step * -4)
2660  * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
2661  *         reduced by (agc_step * -3)
2662  */
2663 #define EEPROM_TSSI_BOUND_A1_MINUS4     FIELD16(0x00ff)
2664 #define EEPROM_TSSI_BOUND_A1_MINUS3     FIELD16(0xff00)
2665
2666 /*
2667  * EEPROM temperature compensation boundaries 802.11A
2668  * MINUS2: If the actual TSSI is below this boundary, tx power needs to be
2669  *         reduced by (agc_step * -2)
2670  * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
2671  *         reduced by (agc_step * -1)
2672  */
2673 #define EEPROM_TSSI_BOUND_A2_MINUS2     FIELD16(0x00ff)
2674 #define EEPROM_TSSI_BOUND_A2_MINUS1     FIELD16(0xff00)
2675
2676 /*
2677  * EEPROM temperature compensation boundaries 802.11A
2678  * REF: Reference TSSI value, no tx power changes needed
2679  * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
2680  *        increased by (agc_step * 1)
2681  */
2682 #define EEPROM_TSSI_BOUND_A3_REF        FIELD16(0x00ff)
2683 #define EEPROM_TSSI_BOUND_A3_PLUS1      FIELD16(0xff00)
2684
2685 /*
2686  * EEPROM temperature compensation boundaries 802.11A
2687  * PLUS2: If the actual TSSI is above this boundary, tx power needs to be
2688  *        increased by (agc_step * 2)
2689  * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
2690  *        increased by (agc_step * 3)
2691  */
2692 #define EEPROM_TSSI_BOUND_A4_PLUS2      FIELD16(0x00ff)
2693 #define EEPROM_TSSI_BOUND_A4_PLUS3      FIELD16(0xff00)
2694
2695 /*
2696  * EEPROM temperature compensation boundaries 802.11A
2697  * PLUS4: If the actual TSSI is above this boundary, tx power needs to be
2698  *        increased by (agc_step * 4)
2699  * AGC_STEP: Temperature compensation step.
2700  */
2701 #define EEPROM_TSSI_BOUND_A5_PLUS4      FIELD16(0x00ff)
2702 #define EEPROM_TSSI_BOUND_A5_AGC_STEP   FIELD16(0xff00)
2703
2704 /*
2705  * EEPROM TXPOWER by rate: tx power per tx rate for HT20 mode
2706  */
2707 #define EEPROM_TXPOWER_BYRATE_SIZE      9
2708
2709 #define EEPROM_TXPOWER_BYRATE_RATE0     FIELD16(0x000f)
2710 #define EEPROM_TXPOWER_BYRATE_RATE1     FIELD16(0x00f0)
2711 #define EEPROM_TXPOWER_BYRATE_RATE2     FIELD16(0x0f00)
2712 #define EEPROM_TXPOWER_BYRATE_RATE3     FIELD16(0xf000)
2713
2714 /*
2715  * EEPROM BBP.
2716  */
2717 #define EEPROM_BBP_SIZE                 16
2718 #define EEPROM_BBP_VALUE                FIELD16(0x00ff)
2719 #define EEPROM_BBP_REG_ID               FIELD16(0xff00)
2720
2721 /* EEPROM_EXT_LNA2 */
2722 #define EEPROM_EXT_LNA2_A1              FIELD16(0x00ff)
2723 #define EEPROM_EXT_LNA2_A2              FIELD16(0xff00)
2724
2725 /*
2726  * EEPROM IQ Calibration, unlike other entries those are byte addresses.
2727  */
2728
2729 #define EEPROM_IQ_GAIN_CAL_TX0_2G                       0x130
2730 #define EEPROM_IQ_PHASE_CAL_TX0_2G                      0x131
2731 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_2G                 0x132
2732 #define EEPROM_IQ_GAIN_CAL_TX1_2G                       0x133
2733 #define EEPROM_IQ_PHASE_CAL_TX1_2G                      0x134
2734 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_2G                 0x135
2735 #define EEPROM_IQ_GAIN_CAL_RX0_2G                       0x136
2736 #define EEPROM_IQ_PHASE_CAL_RX0_2G                      0x137
2737 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_2G                 0x138
2738 #define EEPROM_IQ_GAIN_CAL_RX1_2G                       0x139
2739 #define EEPROM_IQ_PHASE_CAL_RX1_2G                      0x13A
2740 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_2G                 0x13B
2741 #define EEPROM_RF_IQ_COMPENSATION_CONTROL               0x13C
2742 #define EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL     0x13D
2743 #define EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G          0x144
2744 #define EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G         0x145
2745 #define EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G        0X146
2746 #define EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G       0x147
2747 #define EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G        0x148
2748 #define EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G       0x149
2749 #define EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G          0x14A
2750 #define EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G         0x14B
2751 #define EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G        0X14C
2752 #define EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G       0x14D
2753 #define EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G        0x14E
2754 #define EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G       0x14F
2755 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH36_TO_CH64_5G    0x150
2756 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH36_TO_CH64_5G    0x151
2757 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH100_TO_CH138_5G  0x152
2758 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH100_TO_CH138_5G  0x153
2759 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH140_TO_CH165_5G  0x154
2760 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH140_TO_CH165_5G  0x155
2761 #define EEPROM_IQ_GAIN_CAL_RX0_CH36_TO_CH64_5G          0x156
2762 #define EEPROM_IQ_PHASE_CAL_RX0_CH36_TO_CH64_5G         0x157
2763 #define EEPROM_IQ_GAIN_CAL_RX0_CH100_TO_CH138_5G        0X158
2764 #define EEPROM_IQ_PHASE_CAL_RX0_CH100_TO_CH138_5G       0x159
2765 #define EEPROM_IQ_GAIN_CAL_RX0_CH140_TO_CH165_5G        0x15A
2766 #define EEPROM_IQ_PHASE_CAL_RX0_CH140_TO_CH165_5G       0x15B
2767 #define EEPROM_IQ_GAIN_CAL_RX1_CH36_TO_CH64_5G          0x15C
2768 #define EEPROM_IQ_PHASE_CAL_RX1_CH36_TO_CH64_5G         0x15D
2769 #define EEPROM_IQ_GAIN_CAL_RX1_CH100_TO_CH138_5G        0X15E
2770 #define EEPROM_IQ_PHASE_CAL_RX1_CH100_TO_CH138_5G       0x15F
2771 #define EEPROM_IQ_GAIN_CAL_RX1_CH140_TO_CH165_5G        0x160
2772 #define EEPROM_IQ_PHASE_CAL_RX1_CH140_TO_CH165_5G       0x161
2773 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH36_TO_CH64_5G    0x162
2774 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH36_TO_CH64_5G    0x163
2775 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH100_TO_CH138_5G  0x164
2776 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH100_TO_CH138_5G  0x165
2777 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH140_TO_CH165_5G  0x166
2778 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH140_TO_CH165_5G  0x167
2779
2780 /*
2781  * MCU mailbox commands.
2782  * MCU_SLEEP - go to power-save mode.
2783  *             arg1: 1: save as much power as possible, 0: save less power.
2784  *             status: 1: success, 2: already asleep,
2785  *                     3: maybe MAC is busy so can't finish this task.
2786  * MCU_RADIO_OFF
2787  *             arg0: 0: do power-saving, NOT turn off radio.
2788  */
2789 #define MCU_SLEEP                       0x30
2790 #define MCU_WAKEUP                      0x31
2791 #define MCU_RADIO_OFF                   0x35
2792 #define MCU_CURRENT                     0x36
2793 #define MCU_LED                         0x50
2794 #define MCU_LED_STRENGTH                0x51
2795 #define MCU_LED_AG_CONF                 0x52
2796 #define MCU_LED_ACT_CONF                0x53
2797 #define MCU_LED_LED_POLARITY            0x54
2798 #define MCU_RADAR                       0x60
2799 #define MCU_BOOT_SIGNAL                 0x72
2800 #define MCU_ANT_SELECT                  0X73
2801 #define MCU_FREQ_OFFSET                 0x74
2802 #define MCU_BBP_SIGNAL                  0x80
2803 #define MCU_POWER_SAVE                  0x83
2804 #define MCU_BAND_SELECT                 0x91
2805
2806 /*
2807  * MCU mailbox tokens
2808  */
2809 #define TOKEN_SLEEP                     1
2810 #define TOKEN_RADIO_OFF                 2
2811 #define TOKEN_WAKEUP                    3
2812
2813
2814 /*
2815  * DMA descriptor defines.
2816  */
2817
2818 #define TXWI_DESC_SIZE_4WORDS           (4 * sizeof(__le32))
2819 #define TXWI_DESC_SIZE_5WORDS           (5 * sizeof(__le32))
2820
2821 #define RXWI_DESC_SIZE_4WORDS           (4 * sizeof(__le32))
2822 #define RXWI_DESC_SIZE_5WORDS           (5 * sizeof(__le32))
2823 #define RXWI_DESC_SIZE_6WORDS           (6 * sizeof(__le32))
2824
2825 /*
2826  * TX WI structure
2827  */
2828
2829 /*
2830  * Word0
2831  * FRAG: 1 To inform TKIP engine this is a fragment.
2832  * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
2833  * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
2834  * BW: Channel bandwidth 0:20MHz, 1:40 MHz (for legacy rates this will
2835  *     duplicate the frame to both channels).
2836  * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
2837  * AMPDU: 1: this frame is eligible for AMPDU aggregation, the hw will
2838  *        aggregate consecutive frames with the same RA and QoS TID. If
2839  *        a frame A with the same RA and QoS TID but AMPDU=0 is queued
2840  *        directly after a frame B with AMPDU=1, frame A might still
2841  *        get aggregated into the AMPDU started by frame B. So, setting
2842  *        AMPDU to 0 does _not_ necessarily mean the frame is sent as
2843  *        MPDU, it can still end up in an AMPDU if the previous frame
2844  *        was tagged as AMPDU.
2845  */
2846 #define TXWI_W0_FRAG                    FIELD32(0x00000001)
2847 #define TXWI_W0_MIMO_PS                 FIELD32(0x00000002)
2848 #define TXWI_W0_CF_ACK                  FIELD32(0x00000004)
2849 #define TXWI_W0_TS                      FIELD32(0x00000008)
2850 #define TXWI_W0_AMPDU                   FIELD32(0x00000010)
2851 #define TXWI_W0_MPDU_DENSITY            FIELD32(0x000000e0)
2852 #define TXWI_W0_TX_OP                   FIELD32(0x00000300)
2853 #define TXWI_W0_MCS                     FIELD32(0x007f0000)
2854 #define TXWI_W0_BW                      FIELD32(0x00800000)
2855 #define TXWI_W0_SHORT_GI                FIELD32(0x01000000)
2856 #define TXWI_W0_STBC                    FIELD32(0x06000000)
2857 #define TXWI_W0_IFS                     FIELD32(0x08000000)
2858 #define TXWI_W0_PHYMODE                 FIELD32(0xc0000000)
2859
2860 /*
2861  * Word1
2862  * ACK: 0: No Ack needed, 1: Ack needed
2863  * NSEQ: 0: Don't assign hw sequence number, 1: Assign hw sequence number
2864  * BW_WIN_SIZE: BA windows size of the recipient
2865  * WIRELESS_CLI_ID: Client ID for WCID table access
2866  * MPDU_TOTAL_BYTE_COUNT: Length of 802.11 frame
2867  * PACKETID: Will be latched into the TX_STA_FIFO register once the according
2868  *           frame was processed. If multiple frames are aggregated together
2869  *           (AMPDU==1) the reported tx status will always contain the packet
2870  *           id of the first frame. 0: Don't report tx status for this frame.
2871  * PACKETID_QUEUE: Part of PACKETID, This is the queue index (0-3)
2872  * PACKETID_ENTRY: Part of PACKETID, THis is the queue entry index (1-3)
2873  *                 This identification number is calculated by ((idx % 3) + 1).
2874  *                 The (+1) is required to prevent PACKETID to become 0.
2875  */
2876 #define TXWI_W1_ACK                     FIELD32(0x00000001)
2877 #define TXWI_W1_NSEQ                    FIELD32(0x00000002)
2878 #define TXWI_W1_BW_WIN_SIZE             FIELD32(0x000000fc)
2879 #define TXWI_W1_WIRELESS_CLI_ID         FIELD32(0x0000ff00)
2880 #define TXWI_W1_MPDU_TOTAL_BYTE_COUNT   FIELD32(0x0fff0000)
2881 #define TXWI_W1_PACKETID                FIELD32(0xf0000000)
2882 #define TXWI_W1_PACKETID_QUEUE          FIELD32(0x30000000)
2883 #define TXWI_W1_PACKETID_ENTRY          FIELD32(0xc0000000)
2884
2885 /*
2886  * Word2
2887  */
2888 #define TXWI_W2_IV                      FIELD32(0xffffffff)
2889
2890 /*
2891  * Word3
2892  */
2893 #define TXWI_W3_EIV                     FIELD32(0xffffffff)
2894
2895 /*
2896  * RX WI structure
2897  */
2898
2899 /*
2900  * Word0
2901  */
2902 #define RXWI_W0_WIRELESS_CLI_ID         FIELD32(0x000000ff)
2903 #define RXWI_W0_KEY_INDEX               FIELD32(0x00000300)
2904 #define RXWI_W0_BSSID                   FIELD32(0x00001c00)
2905 #define RXWI_W0_UDF                     FIELD32(0x0000e000)
2906 #define RXWI_W0_MPDU_TOTAL_BYTE_COUNT   FIELD32(0x0fff0000)
2907 #define RXWI_W0_TID                     FIELD32(0xf0000000)
2908
2909 /*
2910  * Word1
2911  */
2912 #define RXWI_W1_FRAG                    FIELD32(0x0000000f)
2913 #define RXWI_W1_SEQUENCE                FIELD32(0x0000fff0)
2914 #define RXWI_W1_MCS                     FIELD32(0x007f0000)
2915 #define RXWI_W1_BW                      FIELD32(0x00800000)
2916 #define RXWI_W1_SHORT_GI                FIELD32(0x01000000)
2917 #define RXWI_W1_STBC                    FIELD32(0x06000000)
2918 #define RXWI_W1_PHYMODE                 FIELD32(0xc0000000)
2919
2920 /*
2921  * Word2
2922  */
2923 #define RXWI_W2_RSSI0                   FIELD32(0x000000ff)
2924 #define RXWI_W2_RSSI1                   FIELD32(0x0000ff00)
2925 #define RXWI_W2_RSSI2                   FIELD32(0x00ff0000)
2926
2927 /*
2928  * Word3
2929  */
2930 #define RXWI_W3_SNR0                    FIELD32(0x000000ff)
2931 #define RXWI_W3_SNR1                    FIELD32(0x0000ff00)
2932
2933 /*
2934  * Macros for converting txpower from EEPROM to mac80211 value
2935  * and from mac80211 value to register value.
2936  */
2937 #define MIN_G_TXPOWER   0
2938 #define MIN_A_TXPOWER   -7
2939 #define MAX_G_TXPOWER   31
2940 #define MAX_A_TXPOWER   15
2941 #define DEFAULT_TXPOWER 5
2942
2943 #define MIN_A_TXPOWER_3593      0
2944 #define MAX_A_TXPOWER_3593      31
2945
2946 #define TXPOWER_G_FROM_DEV(__txpower) \
2947         ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
2948
2949 #define TXPOWER_A_FROM_DEV(__txpower) \
2950         ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
2951
2952 /*
2953  *  Board's maximun TX power limitation
2954  */
2955 #define EIRP_MAX_TX_POWER_LIMIT 0x50
2956
2957 /*
2958  * Number of TBTT intervals after which we have to adjust
2959  * the hw beacon timer.
2960  */
2961 #define BCN_TBTT_OFFSET 64
2962
2963 /*
2964  * Hardware has 255 WCID table entries. First 32 entries are reserved for
2965  * shared keys. Since parts of the pairwise key table might be shared with
2966  * the beacon frame buffers 6 & 7 we could only use the first 222 entries.
2967  */
2968 #define WCID_START      33
2969 #define WCID_END        222
2970 #define STA_IDS_SIZE    (WCID_END - WCID_START + 2)
2971
2972 /*
2973  * RT2800 driver data structure
2974  */
2975 struct rt2800_drv_data {
2976         u8 calibration_bw20;
2977         u8 calibration_bw40;
2978         u8 bbp25;
2979         u8 bbp26;
2980         u8 txmixer_gain_24g;
2981         u8 txmixer_gain_5g;
2982         unsigned int tbtt_tick;
2983         DECLARE_BITMAP(sta_ids, STA_IDS_SIZE);
2984 };
2985
2986 #endif /* RT2800_H */