2 * Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2011 PetaLogix
4 * Copyright (C) 2010 Xilinx, Inc. All rights reserved.
6 * SPDX-License-Identifier: GPL-2.0+
18 DECLARE_GLOBAL_DATA_PTR
;
21 #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
22 #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
23 #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
24 #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
26 /* Interrupt Status/Enable/Mask Registers bit definitions */
27 #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
28 #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */
30 /* Receive Configuration Word 1 (RCW1) Register bit definitions */
31 #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
33 /* Transmitter Configuration (TC) Register bit definitions */
34 #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
36 #define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF
38 /* MDIO Management Configuration (MC) Register bit definitions */
39 #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/
41 /* MDIO Management Control Register (MCR) Register bit definitions */
42 #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
43 #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */
44 #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
45 #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */
46 #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */
47 #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */
48 #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */
49 #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */
51 #define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */
54 /* Bitmasks of XAXIDMA_CR_OFFSET register */
55 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
56 #define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */
58 /* Bitmasks of XAXIDMA_SR_OFFSET register */
59 #define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */
61 /* Bitmask for interrupts */
62 #define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */
63 #define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */
64 #define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */
66 /* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */
67 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
68 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
72 static u8 rxframe
[PKTSIZE_ALIGN
] __attribute((aligned(DMAALIGN
)));
74 /* Reflect dma offsets */
76 u32 control
; /* DMACR */
77 u32 status
; /* DMASR */
78 u32 current
; /* CURDESC */
80 u32 tail
; /* TAILDESC */
83 /* Private driver structures */
85 struct axidma_reg
*dmatx
;
86 struct axidma_reg
*dmarx
;
88 struct axi_regs
*iobase
;
89 phy_interface_t interface
;
90 struct phy_device
*phydev
;
96 u32 next
; /* Next descriptor pointer */
98 u32 phys
; /* Buffer address */
102 u32 cntrl
; /* Control */
103 u32 status
; /* Status */
105 u32 app1
; /* TX start << 16 | insert */
106 u32 app2
; /* TX csum seed */
114 /* Static BDs - driver uses only one BD */
115 static struct axidma_bd tx_bd
__attribute((aligned(DMAALIGN
)));
116 static struct axidma_bd rx_bd
__attribute((aligned(DMAALIGN
)));
120 u32 is
; /* 0xC: Interrupt status */
122 u32 ie
; /* 0x14: Interrupt enable */
124 u32 rcw1
; /* 0x404: Rx Configuration Word 1 */
125 u32 tc
; /* 0x408: Tx Configuration */
127 u32 emmc
; /* 0x410: EMAC mode configuration */
129 u32 mdio_mc
; /* 0x500: MII Management Config */
130 u32 mdio_mcr
; /* 0x504: MII Management Control */
131 u32 mdio_mwd
; /* 0x508: MII Management Write Data */
132 u32 mdio_mrd
; /* 0x50C: MII Management Read Data */
134 u32 uaw0
; /* 0x700: Unicast address word 0 */
135 u32 uaw1
; /* 0x704: Unicast address word 1 */
138 /* Use MII register 1 (MII status register) to detect PHY */
139 #define PHY_DETECT_REG 1
142 * Mask used to verify certain PHY features (or register contents)
143 * in the register above:
144 * 0x1000: 10Mbps full duplex support
145 * 0x0800: 10Mbps half duplex support
146 * 0x0008: Auto-negotiation support
148 #define PHY_DETECT_MASK 0x1808
150 static inline int mdio_wait(struct axi_regs
*regs
)
154 /* Wait till MDIO interface is ready to accept a new transaction. */
155 while (timeout
&& (!(in_be32(®s
->mdio_mcr
)
156 & XAE_MDIO_MCR_READY_MASK
))) {
161 printf("%s: Timeout\n", __func__
);
167 static u32
phyread(struct axidma_priv
*priv
, u32 phyaddress
, u32 registernum
,
170 struct axi_regs
*regs
= priv
->iobase
;
176 mdioctrlreg
= ((phyaddress
<< XAE_MDIO_MCR_PHYAD_SHIFT
) &
177 XAE_MDIO_MCR_PHYAD_MASK
) |
178 ((registernum
<< XAE_MDIO_MCR_REGAD_SHIFT
)
179 & XAE_MDIO_MCR_REGAD_MASK
) |
180 XAE_MDIO_MCR_INITIATE_MASK
|
181 XAE_MDIO_MCR_OP_READ_MASK
;
183 out_be32(®s
->mdio_mcr
, mdioctrlreg
);
189 *val
= in_be32(®s
->mdio_mrd
);
193 static u32
phywrite(struct axidma_priv
*priv
, u32 phyaddress
, u32 registernum
,
196 struct axi_regs
*regs
= priv
->iobase
;
202 mdioctrlreg
= ((phyaddress
<< XAE_MDIO_MCR_PHYAD_SHIFT
) &
203 XAE_MDIO_MCR_PHYAD_MASK
) |
204 ((registernum
<< XAE_MDIO_MCR_REGAD_SHIFT
)
205 & XAE_MDIO_MCR_REGAD_MASK
) |
206 XAE_MDIO_MCR_INITIATE_MASK
|
207 XAE_MDIO_MCR_OP_WRITE_MASK
;
210 out_be32(®s
->mdio_mwd
, data
);
212 out_be32(®s
->mdio_mcr
, mdioctrlreg
);
220 static int axiemac_phy_init(struct udevice
*dev
)
224 struct axidma_priv
*priv
= dev_get_priv(dev
);
225 struct axi_regs
*regs
= priv
->iobase
;
226 struct phy_device
*phydev
;
228 u32 supported
= SUPPORTED_10baseT_Half
|
229 SUPPORTED_10baseT_Full
|
230 SUPPORTED_100baseT_Half
|
231 SUPPORTED_100baseT_Full
|
232 SUPPORTED_1000baseT_Half
|
233 SUPPORTED_1000baseT_Full
;
235 /* Set default MDIO divisor */
236 out_be32(®s
->mdio_mc
, XAE_MDIO_DIV_DFT
| XAE_MDIO_MC_MDIOEN_MASK
);
238 if (priv
->phyaddr
== -1) {
239 /* Detect the PHY address */
240 for (i
= 31; i
>= 0; i
--) {
241 ret
= phyread(priv
, i
, PHY_DETECT_REG
, &phyreg
);
242 if (!ret
&& (phyreg
!= 0xFFFF) &&
243 ((phyreg
& PHY_DETECT_MASK
) == PHY_DETECT_MASK
)) {
244 /* Found a valid PHY address */
246 debug("axiemac: Found valid phy address, %x\n",
253 /* Interface - look at tsec */
254 phydev
= phy_connect(priv
->bus
, priv
->phyaddr
, dev
, priv
->interface
);
256 phydev
->supported
&= supported
;
257 phydev
->advertising
= phydev
->supported
;
258 priv
->phydev
= phydev
;
264 /* Setting axi emac and phy to proper setting */
265 static int setup_phy(struct udevice
*dev
)
268 struct axidma_priv
*priv
= dev_get_priv(dev
);
269 struct axi_regs
*regs
= priv
->iobase
;
270 struct phy_device
*phydev
= priv
->phydev
;
272 if (phy_startup(phydev
)) {
273 printf("axiemac: could not initialize PHY %s\n",
278 printf("%s: No link.\n", phydev
->dev
->name
);
282 switch (phydev
->speed
) {
284 speed
= XAE_EMMC_LINKSPD_1000
;
287 speed
= XAE_EMMC_LINKSPD_100
;
290 speed
= XAE_EMMC_LINKSPD_10
;
296 /* Setup the emac for the phy speed */
297 emmc_reg
= in_be32(®s
->emmc
);
298 emmc_reg
&= ~XAE_EMMC_LINKSPEED_MASK
;
301 /* Write new speed setting out to Axi Ethernet */
302 out_be32(®s
->emmc
, emmc_reg
);
305 * Setting the operating speed of the MAC needs a delay. There
306 * doesn't seem to be register to poll, so please consider this
307 * during your application design.
314 /* STOP DMA transfers */
315 static void axiemac_stop(struct udevice
*dev
)
317 struct axidma_priv
*priv
= dev_get_priv(dev
);
320 /* Stop the hardware */
321 temp
= in_be32(&priv
->dmatx
->control
);
322 temp
&= ~XAXIDMA_CR_RUNSTOP_MASK
;
323 out_be32(&priv
->dmatx
->control
, temp
);
325 temp
= in_be32(&priv
->dmarx
->control
);
326 temp
&= ~XAXIDMA_CR_RUNSTOP_MASK
;
327 out_be32(&priv
->dmarx
->control
, temp
);
329 debug("axiemac: Halted\n");
332 static int axi_ethernet_init(struct axidma_priv
*priv
)
334 struct axi_regs
*regs
= priv
->iobase
;
338 * Check the status of the MgtRdy bit in the interrupt status
339 * registers. This must be done to allow the MGT clock to become stable
340 * for the Sgmii and 1000BaseX PHY interfaces. No other register reads
341 * will be valid until this bit is valid.
342 * The bit is always a 1 for all other PHY interfaces.
344 while (timeout
&& (!(in_be32(®s
->is
) & XAE_INT_MGTRDY_MASK
))) {
349 printf("%s: Timeout\n", __func__
);
353 /* Stop the device and reset HW */
354 /* Disable interrupts */
355 out_be32(®s
->ie
, 0);
357 /* Disable the receiver */
358 out_be32(®s
->rcw1
, in_be32(®s
->rcw1
) & ~XAE_RCW1_RX_MASK
);
361 * Stopping the receiver in mid-packet causes a dropped packet
362 * indication from HW. Clear it.
364 /* Set the interrupt status register to clear the interrupt */
365 out_be32(®s
->is
, XAE_INT_RXRJECT_MASK
);
368 /* Set default MDIO divisor */
369 out_be32(®s
->mdio_mc
, XAE_MDIO_DIV_DFT
| XAE_MDIO_MC_MDIOEN_MASK
);
371 debug("axiemac: InitHw done\n");
375 static int axiemac_write_hwaddr(struct udevice
*dev
)
377 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
378 struct axidma_priv
*priv
= dev_get_priv(dev
);
379 struct axi_regs
*regs
= priv
->iobase
;
381 /* Set the MAC address */
382 int val
= ((pdata
->enetaddr
[3] << 24) | (pdata
->enetaddr
[2] << 16) |
383 (pdata
->enetaddr
[1] << 8) | (pdata
->enetaddr
[0]));
384 out_be32(®s
->uaw0
, val
);
386 val
= (pdata
->enetaddr
[5] << 8) | pdata
->enetaddr
[4];
387 val
|= in_be32(®s
->uaw1
) & ~XAE_UAW1_UNICASTADDR_MASK
;
388 out_be32(®s
->uaw1
, val
);
392 /* Reset DMA engine */
393 static void axi_dma_init(struct axidma_priv
*priv
)
397 /* Reset the engine so the hardware starts from a known state */
398 out_be32(&priv
->dmatx
->control
, XAXIDMA_CR_RESET_MASK
);
399 out_be32(&priv
->dmarx
->control
, XAXIDMA_CR_RESET_MASK
);
401 /* At the initialization time, hardware should finish reset quickly */
403 /* Check transmit/receive channel */
404 /* Reset is done when the reset bit is low */
405 if (!((in_be32(&priv
->dmatx
->control
) |
406 in_be32(&priv
->dmarx
->control
))
407 & XAXIDMA_CR_RESET_MASK
)) {
412 printf("%s: Timeout\n", __func__
);
415 static int axiemac_start(struct udevice
*dev
)
417 struct axidma_priv
*priv
= dev_get_priv(dev
);
418 struct axi_regs
*regs
= priv
->iobase
;
421 debug("axiemac: Init started\n");
423 * Initialize AXIDMA engine. AXIDMA engine must be initialized before
424 * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
425 * reset, and since AXIDMA reset line is connected to AxiEthernet, this
426 * would ensure a reset of AxiEthernet.
430 /* Initialize AxiEthernet hardware. */
431 if (axi_ethernet_init(priv
))
434 /* Disable all RX interrupts before RxBD space setup */
435 temp
= in_be32(&priv
->dmarx
->control
);
436 temp
&= ~XAXIDMA_IRQ_ALL_MASK
;
437 out_be32(&priv
->dmarx
->control
, temp
);
439 /* Start DMA RX channel. Now it's ready to receive data.*/
440 out_be32(&priv
->dmarx
->current
, (u32
)&rx_bd
);
443 memset(&rx_bd
, 0, sizeof(rx_bd
));
444 rx_bd
.next
= (u32
)&rx_bd
;
445 rx_bd
.phys
= (u32
)&rxframe
;
446 rx_bd
.cntrl
= sizeof(rxframe
);
447 /* Flush the last BD so DMA core could see the updates */
448 flush_cache((u32
)&rx_bd
, sizeof(rx_bd
));
450 /* It is necessary to flush rxframe because if you don't do it
451 * then cache can contain uninitialized data */
452 flush_cache((u32
)&rxframe
, sizeof(rxframe
));
454 /* Start the hardware */
455 temp
= in_be32(&priv
->dmarx
->control
);
456 temp
|= XAXIDMA_CR_RUNSTOP_MASK
;
457 out_be32(&priv
->dmarx
->control
, temp
);
459 /* Rx BD is ready - start */
460 out_be32(&priv
->dmarx
->tail
, (u32
)&rx_bd
);
463 out_be32(®s
->tc
, XAE_TC_TX_MASK
);
465 out_be32(®s
->rcw1
, XAE_RCW1_RX_MASK
);
468 if (!setup_phy(dev
)) {
473 debug("axiemac: Init complete\n");
477 static int axiemac_send(struct udevice
*dev
, void *ptr
, int len
)
479 struct axidma_priv
*priv
= dev_get_priv(dev
);
482 if (len
> PKTSIZE_ALIGN
)
485 /* Flush packet to main memory to be trasfered by DMA */
486 flush_cache((u32
)ptr
, len
);
489 memset(&tx_bd
, 0, sizeof(tx_bd
));
490 /* At the end of the ring, link the last BD back to the top */
491 tx_bd
.next
= (u32
)&tx_bd
;
492 tx_bd
.phys
= (u32
)ptr
;
494 tx_bd
.cntrl
= len
| XAXIDMA_BD_CTRL_TXSOF_MASK
|
495 XAXIDMA_BD_CTRL_TXEOF_MASK
;
497 /* Flush the last BD so DMA core could see the updates */
498 flush_cache((u32
)&tx_bd
, sizeof(tx_bd
));
500 if (in_be32(&priv
->dmatx
->status
) & XAXIDMA_HALTED_MASK
) {
502 out_be32(&priv
->dmatx
->current
, (u32
)&tx_bd
);
503 /* Start the hardware */
504 temp
= in_be32(&priv
->dmatx
->control
);
505 temp
|= XAXIDMA_CR_RUNSTOP_MASK
;
506 out_be32(&priv
->dmatx
->control
, temp
);
510 out_be32(&priv
->dmatx
->tail
, (u32
)&tx_bd
);
512 /* Wait for transmission to complete */
513 debug("axiemac: Waiting for tx to be done\n");
515 while (timeout
&& (!(in_be32(&priv
->dmatx
->status
) &
516 (XAXIDMA_IRQ_DELAY_MASK
| XAXIDMA_IRQ_IOC_MASK
)))) {
521 printf("%s: Timeout\n", __func__
);
525 debug("axiemac: Sending complete\n");
529 static int isrxready(struct axidma_priv
*priv
)
533 /* Read pending interrupts */
534 status
= in_be32(&priv
->dmarx
->status
);
536 /* Acknowledge pending interrupts */
537 out_be32(&priv
->dmarx
->status
, status
& XAXIDMA_IRQ_ALL_MASK
);
540 * If Reception done interrupt is asserted, call RX call back function
541 * to handle the processed BDs and then raise the according flag.
543 if ((status
& (XAXIDMA_IRQ_DELAY_MASK
| XAXIDMA_IRQ_IOC_MASK
)))
549 static int axiemac_recv(struct udevice
*dev
, int flags
, uchar
**packetp
)
552 struct axidma_priv
*priv
= dev_get_priv(dev
);
555 /* Wait for an incoming packet */
556 if (!isrxready(priv
))
559 debug("axiemac: RX data ready\n");
561 /* Disable IRQ for a moment till packet is handled */
562 temp
= in_be32(&priv
->dmarx
->control
);
563 temp
&= ~XAXIDMA_IRQ_ALL_MASK
;
564 out_be32(&priv
->dmarx
->control
, temp
);
566 length
= rx_bd
.app4
& 0xFFFF; /* max length mask */
568 print_buffer(&rxframe
, &rxframe
[0], 1, length
, 16);
575 static int axiemac_free_pkt(struct udevice
*dev
, uchar
*packet
, int length
)
577 struct axidma_priv
*priv
= dev_get_priv(dev
);
580 /* It is useful to clear buffer to be sure that it is consistent */
581 memset(rxframe
, 0, sizeof(rxframe
));
584 /* Clear the whole buffer and setup it again - all flags are cleared */
585 memset(&rx_bd
, 0, sizeof(rx_bd
));
586 rx_bd
.next
= (u32
)&rx_bd
;
587 rx_bd
.phys
= (u32
)&rxframe
;
588 rx_bd
.cntrl
= sizeof(rxframe
);
591 flush_cache((u32
)&rx_bd
, sizeof(rx_bd
));
593 /* It is necessary to flush rxframe because if you don't do it
594 * then cache will contain previous packet */
595 flush_cache((u32
)&rxframe
, sizeof(rxframe
));
597 /* Rx BD is ready - start again */
598 out_be32(&priv
->dmarx
->tail
, (u32
)&rx_bd
);
600 debug("axiemac: RX completed, framelength = %d\n", length
);
605 static int axiemac_miiphy_read(struct mii_dev
*bus
, int addr
,
611 ret
= phyread(bus
->priv
, addr
, reg
, &value
);
612 debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr
, reg
,
617 static int axiemac_miiphy_write(struct mii_dev
*bus
, int addr
, int devad
,
620 debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr
, reg
, value
);
621 return phywrite(bus
->priv
, addr
, reg
, value
);
624 static int axi_emac_probe(struct udevice
*dev
)
626 struct axidma_priv
*priv
= dev_get_priv(dev
);
629 priv
->bus
= mdio_alloc();
630 priv
->bus
->read
= axiemac_miiphy_read
;
631 priv
->bus
->write
= axiemac_miiphy_write
;
632 priv
->bus
->priv
= priv
;
633 strcpy(priv
->bus
->name
, "axi_emac");
635 ret
= mdio_register(priv
->bus
);
639 axiemac_phy_init(dev
);
644 static int axi_emac_remove(struct udevice
*dev
)
646 struct axidma_priv
*priv
= dev_get_priv(dev
);
649 mdio_unregister(priv
->bus
);
650 mdio_free(priv
->bus
);
655 static const struct eth_ops axi_emac_ops
= {
656 .start
= axiemac_start
,
657 .send
= axiemac_send
,
658 .recv
= axiemac_recv
,
659 .free_pkt
= axiemac_free_pkt
,
660 .stop
= axiemac_stop
,
661 .write_hwaddr
= axiemac_write_hwaddr
,
664 static int axi_emac_ofdata_to_platdata(struct udevice
*dev
)
666 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
667 struct axidma_priv
*priv
= dev_get_priv(dev
);
669 const char *phy_mode
;
671 pdata
->iobase
= (phys_addr_t
)dev_get_addr(dev
);
672 priv
->iobase
= (struct axi_regs
*)pdata
->iobase
;
674 offset
= fdtdec_lookup_phandle(gd
->fdt_blob
, dev
->of_offset
,
675 "axistream-connected");
677 printf("%s: axistream is not found\n", __func__
);
680 priv
->dmatx
= (struct axidma_reg
*)fdtdec_get_int(gd
->fdt_blob
,
683 printf("%s: axi_dma register space not found\n", __func__
);
686 /* RX channel offset is 0x30 */
687 priv
->dmarx
= (struct axidma_reg
*)((u32
)priv
->dmatx
+ 0x30);
691 offset
= fdtdec_lookup_phandle(gd
->fdt_blob
, dev
->of_offset
,
694 priv
->phyaddr
= fdtdec_get_int(gd
->fdt_blob
, offset
, "reg", -1);
696 phy_mode
= fdt_getprop(gd
->fdt_blob
, dev
->of_offset
, "phy-mode", NULL
);
698 pdata
->phy_interface
= phy_get_interface_by_name(phy_mode
);
699 if (pdata
->phy_interface
== -1) {
700 debug("%s: Invalid PHY interface '%s'\n", __func__
, phy_mode
);
703 priv
->interface
= pdata
->phy_interface
;
705 printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong
)priv
->iobase
,
706 priv
->phyaddr
, phy_string_for_interface(priv
->interface
));
711 static const struct udevice_id axi_emac_ids
[] = {
712 { .compatible
= "xlnx,axi-ethernet-1.00.a" },
716 U_BOOT_DRIVER(axi_emac
) = {
719 .of_match
= axi_emac_ids
,
720 .ofdata_to_platdata
= axi_emac_ofdata_to_platdata
,
721 .probe
= axi_emac_probe
,
722 .remove
= axi_emac_remove
,
723 .ops
= &axi_emac_ops
,
724 .priv_auto_alloc_size
= sizeof(struct axidma_priv
),
725 .platdata_auto_alloc_size
= sizeof(struct eth_pdata
),