drivers/net/xilinx_axi_emac.c

   1 /*
   2  * Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
   3  * Copyright (C) 2011 PetaLogix
   4  * Copyright (C) 2010 Xilinx, Inc. All rights reserved.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <config.h>
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <net.h>
  13 #include <malloc.h>
  14 #include <asm/io.h>
  15 #include <phy.h>
  16 #include <miiphy.h>
  17 #include <wait_bit.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 /* Link setup */
  22 #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
  23 #define XAE_EMMC_LINKSPD_10     0x00000000 /* Link Speed mask for 10 Mbit */
  24 #define XAE_EMMC_LINKSPD_100    0x40000000 /* Link Speed mask for 100 Mbit */
  25 #define XAE_EMMC_LINKSPD_1000   0x80000000 /* Link Speed mask for 1000 Mbit */
  26
  27 /* Interrupt Status/Enable/Mask Registers bit definitions */
  28 #define XAE_INT_RXRJECT_MASK    0x00000008 /* Rx frame rejected */
  29 #define XAE_INT_MGTRDY_MASK     0x00000080 /* MGT clock Lock */
  30
  31 /* Receive Configuration Word 1 (RCW1) Register bit definitions */
  32 #define XAE_RCW1_RX_MASK        0x10000000 /* Receiver enable */
  33
  34 /* Transmitter Configuration (TC) Register bit definitions */
  35 #define XAE_TC_TX_MASK          0x10000000 /* Transmitter enable */
  36
  37 #define XAE_UAW1_UNICASTADDR_MASK       0x0000FFFF
  38
  39 /* MDIO Management Configuration (MC) Register bit definitions */
  40 #define XAE_MDIO_MC_MDIOEN_MASK         0x00000040 /* MII management enable*/
  41
  42 /* MDIO Management Control Register (MCR) Register bit definitions */
  43 #define XAE_MDIO_MCR_PHYAD_MASK         0x1F000000 /* Phy Address Mask */
  44 #define XAE_MDIO_MCR_PHYAD_SHIFT        24         /* Phy Address Shift */
  45 #define XAE_MDIO_MCR_REGAD_MASK         0x001F0000 /* Reg Address Mask */
  46 #define XAE_MDIO_MCR_REGAD_SHIFT        16         /* Reg Address Shift */
  47 #define XAE_MDIO_MCR_OP_READ_MASK       0x00008000 /* Op Code Read Mask */
  48 #define XAE_MDIO_MCR_OP_WRITE_MASK      0x00004000 /* Op Code Write Mask */
  49 #define XAE_MDIO_MCR_INITIATE_MASK      0x00000800 /* Ready Mask */
  50 #define XAE_MDIO_MCR_READY_MASK         0x00000080 /* Ready Mask */
  51
  52 #define XAE_MDIO_DIV_DFT        29      /* Default MDIO clock divisor */
  53
  54 #define XAXIDMA_BD_STS_ACTUAL_LEN_MASK  0x007FFFFF /* Actual len */
  55
  56 /* DMA macros */
  57 /* Bitmasks of XAXIDMA_CR_OFFSET register */
  58 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
  59 #define XAXIDMA_CR_RESET_MASK   0x00000004 /* Reset DMA engine */
  60
  61 /* Bitmasks of XAXIDMA_SR_OFFSET register */
  62 #define XAXIDMA_HALTED_MASK     0x00000001  /* DMA channel halted */
  63
  64 /* Bitmask for interrupts */
  65 #define XAXIDMA_IRQ_IOC_MASK    0x00001000 /* Completion intr */
  66 #define XAXIDMA_IRQ_DELAY_MASK  0x00002000 /* Delay interrupt */
  67 #define XAXIDMA_IRQ_ALL_MASK    0x00007000 /* All interrupts */
  68
  69 /* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */
  70 #define XAXIDMA_BD_CTRL_TXSOF_MASK      0x08000000 /* First tx packet */
  71 #define XAXIDMA_BD_CTRL_TXEOF_MASK      0x04000000 /* Last tx packet */
  72
  73 #define DMAALIGN        128
  74
  75 static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
  76
  77 /* Reflect dma offsets */
  78 struct axidma_reg {
  79         u32 control; /* DMACR */
  80         u32 status; /* DMASR */
  81         u32 current; /* CURDESC */
  82         u32 reserved;
  83         u32 tail; /* TAILDESC */
  84 };
  85
  86 /* Private driver structures */
  87 struct axidma_priv {
  88         struct axidma_reg *dmatx;
  89         struct axidma_reg *dmarx;
  90         int phyaddr;
  91         struct axi_regs *iobase;
  92         phy_interface_t interface;
  93         struct phy_device *phydev;
  94         struct mii_dev *bus;
  95         u8 eth_hasnobuf;
  96 };
  97
  98 /* BD descriptors */
  99 struct axidma_bd {
 100         u32 next;       /* Next descriptor pointer */
 101         u32 reserved1;
 102         u32 phys;       /* Buffer address */
 103         u32 reserved2;
 104         u32 reserved3;
 105         u32 reserved4;
 106         u32 cntrl;      /* Control */
 107         u32 status;     /* Status */
 108         u32 app0;
 109         u32 app1;       /* TX start << 16 | insert */
 110         u32 app2;       /* TX csum seed */
 111         u32 app3;
 112         u32 app4;
 113         u32 sw_id_offset;
 114         u32 reserved5;
 115         u32 reserved6;
 116 };
 117
 118 /* Static BDs - driver uses only one BD */
 119 static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN)));
 120 static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN)));
 121
 122 struct axi_regs {
 123         u32 reserved[3];
 124         u32 is; /* 0xC: Interrupt status */
 125         u32 reserved2;
 126         u32 ie; /* 0x14: Interrupt enable */
 127         u32 reserved3[251];
 128         u32 rcw1; /* 0x404: Rx Configuration Word 1 */
 129         u32 tc; /* 0x408: Tx Configuration */
 130         u32 reserved4;
 131         u32 emmc; /* 0x410: EMAC mode configuration */
 132         u32 reserved5[59];
 133         u32 mdio_mc; /* 0x500: MII Management Config */
 134         u32 mdio_mcr; /* 0x504: MII Management Control */
 135         u32 mdio_mwd; /* 0x508: MII Management Write Data */
 136         u32 mdio_mrd; /* 0x50C: MII Management Read Data */
 137         u32 reserved6[124];
 138         u32 uaw0; /* 0x700: Unicast address word 0 */
 139         u32 uaw1; /* 0x704: Unicast address word 1 */
 140 };
 141
 142 /* Use MII register 1 (MII status register) to detect PHY */
 143 #define PHY_DETECT_REG  1
 144
 145 /*
 146  * Mask used to verify certain PHY features (or register contents)
 147  * in the register above:
 148  *  0x1000: 10Mbps full duplex support
 149  *  0x0800: 10Mbps half duplex support
 150  *  0x0008: Auto-negotiation support
 151  */
 152 #define PHY_DETECT_MASK 0x1808
 153
 154 static inline int mdio_wait(struct axi_regs *regs)
 155 {
 156         u32 timeout = 200;
 157
 158         /* Wait till MDIO interface is ready to accept a new transaction. */
 159         while (timeout && (!(readl(&regs->mdio_mcr)
 160                                                 & XAE_MDIO_MCR_READY_MASK))) {
 161                 timeout--;
 162                 udelay(1);
 163         }
 164         if (!timeout) {
 165                 printf("%s: Timeout\n", __func__);
 166                 return 1;
 167         }
 168         return 0;
 169 }
 170
 171 static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
 172                    u16 *val)
 173 {
 174         struct axi_regs *regs = priv->iobase;
 175         u32 mdioctrlreg = 0;
 176
 177         if (mdio_wait(regs))
 178                 return 1;
 179
 180         mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
 181                         XAE_MDIO_MCR_PHYAD_MASK) |
 182                         ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
 183                         & XAE_MDIO_MCR_REGAD_MASK) |
 184                         XAE_MDIO_MCR_INITIATE_MASK |
 185                         XAE_MDIO_MCR_OP_READ_MASK;
 186
 187         writel(mdioctrlreg, &regs->mdio_mcr);
 188
 189         if (mdio_wait(regs))
 190                 return 1;
 191
 192         /* Read data */
 193         *val = readl(&regs->mdio_mrd);
 194         return 0;
 195 }
 196
 197 static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
 198                     u32 data)
 199 {
 200         struct axi_regs *regs = priv->iobase;
 201         u32 mdioctrlreg = 0;
 202
 203         if (mdio_wait(regs))
 204                 return 1;
 205
 206         mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
 207                         XAE_MDIO_MCR_PHYAD_MASK) |
 208                         ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
 209                         & XAE_MDIO_MCR_REGAD_MASK) |
 210                         XAE_MDIO_MCR_INITIATE_MASK |
 211                         XAE_MDIO_MCR_OP_WRITE_MASK;
 212
 213         /* Write data */
 214         writel(data, &regs->mdio_mwd);
 215
 216         writel(mdioctrlreg, &regs->mdio_mcr);
 217
 218         if (mdio_wait(regs))
 219                 return 1;
 220
 221         return 0;
 222 }
 223
 224 static int axiemac_phy_init(struct udevice *dev)
 225 {
 226         u16 phyreg;
 227         u32 i, ret;
 228         struct axidma_priv *priv = dev_get_priv(dev);
 229         struct axi_regs *regs = priv->iobase;
 230         struct phy_device *phydev;
 231
 232         u32 supported = SUPPORTED_10baseT_Half |
 233                         SUPPORTED_10baseT_Full |
 234                         SUPPORTED_100baseT_Half |
 235                         SUPPORTED_100baseT_Full |
 236                         SUPPORTED_1000baseT_Half |
 237                         SUPPORTED_1000baseT_Full;
 238
 239         /* Set default MDIO divisor */
 240         writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, &regs->mdio_mc);
 241
 242         if (priv->phyaddr == -1) {
 243                 /* Detect the PHY address */
 244                 for (i = 31; i >= 0; i--) {
 245                         ret = phyread(priv, i, PHY_DETECT_REG, &phyreg);
 246                         if (!ret && (phyreg != 0xFFFF) &&
 247                         ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
 248                                 /* Found a valid PHY address */
 249                                 priv->phyaddr = i;
 250                                 debug("axiemac: Found valid phy address, %x\n",
 251                                       i);
 252                                 break;
 253                         }
 254                 }
 255         }
 256
 257         /* Interface - look at tsec */
 258         phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
 259
 260         phydev->supported &= supported;
 261         phydev->advertising = phydev->supported;
 262         priv->phydev = phydev;
 263         phy_config(phydev);
 264
 265         return 0;
 266 }
 267
 268 /* Setting axi emac and phy to proper setting */
 269 static int setup_phy(struct udevice *dev)
 270 {
 271         u16 temp;
 272         u32 speed, emmc_reg, ret;
 273         struct axidma_priv *priv = dev_get_priv(dev);
 274         struct axi_regs *regs = priv->iobase;
 275         struct phy_device *phydev = priv->phydev;
 276
 277         if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
 278                 /*
 279                  * In SGMII cases the isolate bit might set
 280                  * after DMA and ethernet resets and hence
 281                  * check and clear if set.
 282                  */
 283                 ret = phyread(priv, priv->phyaddr, MII_BMCR, &temp);
 284                 if (ret)
 285                         return 0;
 286                 if (temp & BMCR_ISOLATE) {
 287                         temp &= ~BMCR_ISOLATE;
 288                         ret = phywrite(priv, priv->phyaddr, MII_BMCR, temp);
 289                         if (ret)
 290                                 return 0;
 291                 }
 292         }
 293
 294         if (phy_startup(phydev)) {
 295                 printf("axiemac: could not initialize PHY %s\n",
 296                        phydev->dev->name);
 297                 return 0;
 298         }
 299         if (!phydev->link) {
 300                 printf("%s: No link.\n", phydev->dev->name);
 301                 return 0;
 302         }
 303
 304         switch (phydev->speed) {
 305         case 1000:
 306                 speed = XAE_EMMC_LINKSPD_1000;
 307                 break;
 308         case 100:
 309                 speed = XAE_EMMC_LINKSPD_100;
 310                 break;
 311         case 10:
 312                 speed = XAE_EMMC_LINKSPD_10;
 313                 break;
 314         default:
 315                 return 0;
 316         }
 317
 318         /* Setup the emac for the phy speed */
 319         emmc_reg = readl(&regs->emmc);
 320         emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
 321         emmc_reg |= speed;
 322
 323         /* Write new speed setting out to Axi Ethernet */
 324         writel(emmc_reg, &regs->emmc);
 325
 326         /*
 327         * Setting the operating speed of the MAC needs a delay. There
 328         * doesn't seem to be register to poll, so please consider this
 329         * during your application design.
 330         */
 331         udelay(1);
 332
 333         return 1;
 334 }
 335
 336 /* STOP DMA transfers */
 337 static void axiemac_stop(struct udevice *dev)
 338 {
 339         struct axidma_priv *priv = dev_get_priv(dev);
 340         u32 temp;
 341
 342         /* Stop the hardware */
 343         temp = readl(&priv->dmatx->control);
 344         temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
 345         writel(temp, &priv->dmatx->control);
 346
 347         temp = readl(&priv->dmarx->control);
 348         temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
 349         writel(temp, &priv->dmarx->control);
 350
 351         debug("axiemac: Halted\n");
 352 }
 353
 354 static int axi_ethernet_init(struct axidma_priv *priv)
 355 {
 356         struct axi_regs *regs = priv->iobase;
 357         int err;
 358
 359         /*
 360          * Check the status of the MgtRdy bit in the interrupt status
 361          * registers. This must be done to allow the MGT clock to become stable
 362          * for the Sgmii and 1000BaseX PHY interfaces. No other register reads
 363          * will be valid until this bit is valid.
 364          * The bit is always a 1 for all other PHY interfaces.
 365          * Interrupt status and enable registers are not available in non
 366          * processor mode and hence bypass in this mode
 367          */
 368         if (!priv->eth_hasnobuf) {
 369                 err = wait_for_bit(__func__, (const u32 *)&regs->is,
 370                                    XAE_INT_MGTRDY_MASK, true, 200, false);
 371                 if (err) {
 372                         printf("%s: Timeout\n", __func__);
 373                         return 1;
 374                 }
 375
 376                 /*
 377                  * Stop the device and reset HW
 378                  * Disable interrupts
 379                  */
 380                 writel(0, &regs->ie);
 381         }
 382
 383         /* Disable the receiver */
 384         writel(readl(&regs->rcw1) & ~XAE_RCW1_RX_MASK, &regs->rcw1);
 385
 386         /*
 387          * Stopping the receiver in mid-packet causes a dropped packet
 388          * indication from HW. Clear it.
 389          */
 390         if (!priv->eth_hasnobuf) {
 391                 /* Set the interrupt status register to clear the interrupt */
 392                 writel(XAE_INT_RXRJECT_MASK, &regs->is);
 393         }
 394
 395         /* Setup HW */
 396         /* Set default MDIO divisor */
 397         writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, &regs->mdio_mc);
 398
 399         debug("axiemac: InitHw done\n");
 400         return 0;
 401 }
 402
 403 static int axiemac_write_hwaddr(struct udevice *dev)
 404 {
 405         struct eth_pdata *pdata = dev_get_platdata(dev);
 406         struct axidma_priv *priv = dev_get_priv(dev);
 407         struct axi_regs *regs = priv->iobase;
 408
 409         /* Set the MAC address */
 410         int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) |
 411                 (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0]));
 412         writel(val, &regs->uaw0);
 413
 414         val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4];
 415         val |= readl(&regs->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
 416         writel(val, &regs->uaw1);
 417         return 0;
 418 }
 419
 420 /* Reset DMA engine */
 421 static void axi_dma_init(struct axidma_priv *priv)
 422 {
 423         u32 timeout = 500;
 424
 425         /* Reset the engine so the hardware starts from a known state */
 426         writel(XAXIDMA_CR_RESET_MASK, &priv->dmatx->control);
 427         writel(XAXIDMA_CR_RESET_MASK, &priv->dmarx->control);
 428
 429         /* At the initialization time, hardware should finish reset quickly */
 430         while (timeout--) {
 431                 /* Check transmit/receive channel */
 432                 /* Reset is done when the reset bit is low */
 433                 if (!((readl(&priv->dmatx->control) |
 434                                 readl(&priv->dmarx->control))
 435                                                 & XAXIDMA_CR_RESET_MASK)) {
 436                         break;
 437                 }
 438         }
 439         if (!timeout)
 440                 printf("%s: Timeout\n", __func__);
 441 }
 442
 443 static int axiemac_start(struct udevice *dev)
 444 {
 445         struct axidma_priv *priv = dev_get_priv(dev);
 446         struct axi_regs *regs = priv->iobase;
 447         u32 temp;
 448
 449         debug("axiemac: Init started\n");
 450         /*
 451          * Initialize AXIDMA engine. AXIDMA engine must be initialized before
 452          * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
 453          * reset, and since AXIDMA reset line is connected to AxiEthernet, this
 454          * would ensure a reset of AxiEthernet.
 455          */
 456         axi_dma_init(priv);
 457
 458         /* Initialize AxiEthernet hardware. */
 459         if (axi_ethernet_init(priv))
 460                 return -1;
 461
 462         /* Disable all RX interrupts before RxBD space setup */
 463         temp = readl(&priv->dmarx->control);
 464         temp &= ~XAXIDMA_IRQ_ALL_MASK;
 465         writel(temp, &priv->dmarx->control);
 466
 467         /* Start DMA RX channel. Now it's ready to receive data.*/
 468         writel((u32)&rx_bd, &priv->dmarx->current);
 469
 470         /* Setup the BD. */
 471         memset(&rx_bd, 0, sizeof(rx_bd));
 472         rx_bd.next = (u32)&rx_bd;
 473         rx_bd.phys = (u32)&rxframe;
 474         rx_bd.cntrl = sizeof(rxframe);
 475         /* Flush the last BD so DMA core could see the updates */
 476         flush_cache((u32)&rx_bd, sizeof(rx_bd));
 477
 478         /* It is necessary to flush rxframe because if you don't do it
 479          * then cache can contain uninitialized data */
 480         flush_cache((u32)&rxframe, sizeof(rxframe));
 481
 482         /* Start the hardware */
 483         temp = readl(&priv->dmarx->control);
 484         temp |= XAXIDMA_CR_RUNSTOP_MASK;
 485         writel(temp, &priv->dmarx->control);
 486
 487         /* Rx BD is ready - start */
 488         writel((u32)&rx_bd, &priv->dmarx->tail);
 489
 490         /* Enable TX */
 491         writel(XAE_TC_TX_MASK, &regs->tc);
 492         /* Enable RX */
 493         writel(XAE_RCW1_RX_MASK, &regs->rcw1);
 494
 495         /* PHY setup */
 496         if (!setup_phy(dev)) {
 497                 axiemac_stop(dev);
 498                 return -1;
 499         }
 500
 501         debug("axiemac: Init complete\n");
 502         return 0;
 503 }
 504
 505 static int axiemac_send(struct udevice *dev, void *ptr, int len)
 506 {
 507         struct axidma_priv *priv = dev_get_priv(dev);
 508         u32 timeout;
 509
 510         if (len > PKTSIZE_ALIGN)
 511                 len = PKTSIZE_ALIGN;
 512
 513         /* Flush packet to main memory to be trasfered by DMA */
 514         flush_cache((u32)ptr, len);
 515
 516         /* Setup Tx BD */
 517         memset(&tx_bd, 0, sizeof(tx_bd));
 518         /* At the end of the ring, link the last BD back to the top */
 519         tx_bd.next = (u32)&tx_bd;
 520         tx_bd.phys = (u32)ptr;
 521         /* Save len */
 522         tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK |
 523                                                 XAXIDMA_BD_CTRL_TXEOF_MASK;
 524
 525         /* Flush the last BD so DMA core could see the updates */
 526         flush_cache((u32)&tx_bd, sizeof(tx_bd));
 527
 528         if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
 529                 u32 temp;
 530                 writel((u32)&tx_bd, &priv->dmatx->current);
 531                 /* Start the hardware */
 532                 temp = readl(&priv->dmatx->control);
 533                 temp |= XAXIDMA_CR_RUNSTOP_MASK;
 534                 writel(temp, &priv->dmatx->control);
 535         }
 536
 537         /* Start transfer */
 538         writel((u32)&tx_bd, &priv->dmatx->tail);
 539
 540         /* Wait for transmission to complete */
 541         debug("axiemac: Waiting for tx to be done\n");
 542         timeout = 200;
 543         while (timeout && (!(readl(&priv->dmatx->status) &
 544                         (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) {
 545                 timeout--;
 546                 udelay(1);
 547         }
 548         if (!timeout) {
 549                 printf("%s: Timeout\n", __func__);
 550                 return 1;
 551         }
 552
 553         debug("axiemac: Sending complete\n");
 554         return 0;
 555 }
 556
 557 static int isrxready(struct axidma_priv *priv)
 558 {
 559         u32 status;
 560
 561         /* Read pending interrupts */
 562         status = readl(&priv->dmarx->status);
 563
 564         /* Acknowledge pending interrupts */
 565         writel(status & XAXIDMA_IRQ_ALL_MASK, &priv->dmarx->status);
 566
 567         /*
 568          * If Reception done interrupt is asserted, call RX call back function
 569          * to handle the processed BDs and then raise the according flag.
 570          */
 571         if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))
 572                 return 1;
 573
 574         return 0;
 575 }
 576
 577 static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp)
 578 {
 579         u32 length;
 580         struct axidma_priv *priv = dev_get_priv(dev);
 581         u32 temp;
 582
 583         /* Wait for an incoming packet */
 584         if (!isrxready(priv))
 585                 return -1;
 586
 587         debug("axiemac: RX data ready\n");
 588
 589         /* Disable IRQ for a moment till packet is handled */
 590         temp = readl(&priv->dmarx->control);
 591         temp &= ~XAXIDMA_IRQ_ALL_MASK;
 592         writel(temp, &priv->dmarx->control);
 593         if (!priv->eth_hasnobuf)
 594                 length = rx_bd.app4 & 0xFFFF; /* max length mask */
 595         else
 596                 length = rx_bd.status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
 597
 598 #ifdef DEBUG
 599         print_buffer(&rxframe, &rxframe[0], 1, length, 16);
 600 #endif
 601
 602         *packetp = rxframe;
 603         return length;
 604 }
 605
 606 static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length)
 607 {
 608         struct axidma_priv *priv = dev_get_priv(dev);
 609
 610 #ifdef DEBUG
 611         /* It is useful to clear buffer to be sure that it is consistent */
 612         memset(rxframe, 0, sizeof(rxframe));
 613 #endif
 614         /* Setup RxBD */
 615         /* Clear the whole buffer and setup it again - all flags are cleared */
 616         memset(&rx_bd, 0, sizeof(rx_bd));
 617         rx_bd.next = (u32)&rx_bd;
 618         rx_bd.phys = (u32)&rxframe;
 619         rx_bd.cntrl = sizeof(rxframe);
 620
 621         /* Write bd to HW */
 622         flush_cache((u32)&rx_bd, sizeof(rx_bd));
 623
 624         /* It is necessary to flush rxframe because if you don't do it
 625          * then cache will contain previous packet */
 626         flush_cache((u32)&rxframe, sizeof(rxframe));
 627
 628         /* Rx BD is ready - start again */
 629         writel((u32)&rx_bd, &priv->dmarx->tail);
 630
 631         debug("axiemac: RX completed, framelength = %d\n", length);
 632
 633         return 0;
 634 }
 635
 636 static int axiemac_miiphy_read(struct mii_dev *bus, int addr,
 637                                int devad, int reg)
 638 {
 639         int ret;
 640         u16 value;
 641
 642         ret = phyread(bus->priv, addr, reg, &value);
 643         debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg,
 644               value, ret);
 645         return value;
 646 }
 647
 648 static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad,
 649                                 int reg, u16 value)
 650 {
 651         debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
 652         return phywrite(bus->priv, addr, reg, value);
 653 }
 654
 655 static int axi_emac_probe(struct udevice *dev)
 656 {
 657         struct axidma_priv *priv = dev_get_priv(dev);
 658         int ret;
 659
 660         priv->bus = mdio_alloc();
 661         priv->bus->read = axiemac_miiphy_read;
 662         priv->bus->write = axiemac_miiphy_write;
 663         priv->bus->priv = priv;
 664
 665         ret = mdio_register_seq(priv->bus, dev->seq);
 666         if (ret)
 667                 return ret;
 668
 669         axiemac_phy_init(dev);
 670
 671         return 0;
 672 }
 673
 674 static int axi_emac_remove(struct udevice *dev)
 675 {
 676         struct axidma_priv *priv = dev_get_priv(dev);
 677
 678         free(priv->phydev);
 679         mdio_unregister(priv->bus);
 680         mdio_free(priv->bus);
 681
 682         return 0;
 683 }
 684
 685 static const struct eth_ops axi_emac_ops = {
 686         .start                  = axiemac_start,
 687         .send                   = axiemac_send,
 688         .recv                   = axiemac_recv,
 689         .free_pkt               = axiemac_free_pkt,
 690         .stop                   = axiemac_stop,
 691         .write_hwaddr           = axiemac_write_hwaddr,
 692 };
 693
 694 static int axi_emac_ofdata_to_platdata(struct udevice *dev)
 695 {
 696         struct eth_pdata *pdata = dev_get_platdata(dev);
 697         struct axidma_priv *priv = dev_get_priv(dev);
 698         int node = dev_of_offset(dev);
 699         int offset = 0;
 700         const char *phy_mode;
 701
 702         pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
 703         priv->iobase = (struct axi_regs *)pdata->iobase;
 704
 705         offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
 706                                        "axistream-connected");
 707         if (offset <= 0) {
 708                 printf("%s: axistream is not found\n", __func__);
 709                 return -EINVAL;
 710         }
 711         priv->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob,
 712                                                           offset, "reg");
 713         if (!priv->dmatx) {
 714                 printf("%s: axi_dma register space not found\n", __func__);
 715                 return -EINVAL;
 716         }
 717         /* RX channel offset is 0x30 */
 718         priv->dmarx = (struct axidma_reg *)((u32)priv->dmatx + 0x30);
 719
 720         priv->phyaddr = -1;
 721
 722         offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
 723         if (offset > 0)
 724                 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
 725
 726         phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
 727         if (phy_mode)
 728                 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
 729         if (pdata->phy_interface == -1) {
 730                 printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
 731                 return -EINVAL;
 732         }
 733         priv->interface = pdata->phy_interface;
 734
 735         priv->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
 736                                              "xlnx,eth-hasnobuf");
 737
 738         printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
 739                priv->phyaddr, phy_string_for_interface(priv->interface));
 740
 741         return 0;
 742 }
 743
 744 static const struct udevice_id axi_emac_ids[] = {
 745         { .compatible = "xlnx,axi-ethernet-1.00.a" },
 746         { }
 747 };
 748
 749 U_BOOT_DRIVER(axi_emac) = {
 750         .name   = "axi_emac",
 751         .id     = UCLASS_ETH,
 752         .of_match = axi_emac_ids,
 753         .ofdata_to_platdata = axi_emac_ofdata_to_platdata,
 754         .probe  = axi_emac_probe,
 755         .remove = axi_emac_remove,
 756         .ops    = &axi_emac_ops,
 757         .priv_auto_alloc_size = sizeof(struct axidma_priv),
 758         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
 759 };