2 * Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2011 PetaLogix
4 * Copyright (C) 2010 Xilinx, Inc. All rights reserved.
6 * SPDX-License-Identifier: GPL-2.0+
19 DECLARE_GLOBAL_DATA_PTR
;
22 #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
23 #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
24 #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
25 #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
27 /* Interrupt Status/Enable/Mask Registers bit definitions */
28 #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
29 #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */
31 /* Receive Configuration Word 1 (RCW1) Register bit definitions */
32 #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
34 /* Transmitter Configuration (TC) Register bit definitions */
35 #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
37 #define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF
39 /* MDIO Management Configuration (MC) Register bit definitions */
40 #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/
42 /* MDIO Management Control Register (MCR) Register bit definitions */
43 #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
44 #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */
45 #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
46 #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */
47 #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */
48 #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */
49 #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */
50 #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */
52 #define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */
54 #define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF /* Actual len */
57 /* Bitmasks of XAXIDMA_CR_OFFSET register */
58 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
59 #define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */
61 /* Bitmasks of XAXIDMA_SR_OFFSET register */
62 #define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */
64 /* Bitmask for interrupts */
65 #define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */
66 #define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */
67 #define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */
69 /* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */
70 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
71 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
75 static u8 rxframe
[PKTSIZE_ALIGN
] __attribute((aligned(DMAALIGN
)));
77 /* Reflect dma offsets */
79 u32 control
; /* DMACR */
80 u32 status
; /* DMASR */
81 u32 current
; /* CURDESC */
83 u32 tail
; /* TAILDESC */
86 /* Private driver structures */
88 struct axidma_reg
*dmatx
;
89 struct axidma_reg
*dmarx
;
91 struct axi_regs
*iobase
;
92 phy_interface_t interface
;
93 struct phy_device
*phydev
;
100 u32 next
; /* Next descriptor pointer */
102 u32 phys
; /* Buffer address */
106 u32 cntrl
; /* Control */
107 u32 status
; /* Status */
109 u32 app1
; /* TX start << 16 | insert */
110 u32 app2
; /* TX csum seed */
118 /* Static BDs - driver uses only one BD */
119 static struct axidma_bd tx_bd
__attribute((aligned(DMAALIGN
)));
120 static struct axidma_bd rx_bd
__attribute((aligned(DMAALIGN
)));
124 u32 is
; /* 0xC: Interrupt status */
126 u32 ie
; /* 0x14: Interrupt enable */
128 u32 rcw1
; /* 0x404: Rx Configuration Word 1 */
129 u32 tc
; /* 0x408: Tx Configuration */
131 u32 emmc
; /* 0x410: EMAC mode configuration */
133 u32 mdio_mc
; /* 0x500: MII Management Config */
134 u32 mdio_mcr
; /* 0x504: MII Management Control */
135 u32 mdio_mwd
; /* 0x508: MII Management Write Data */
136 u32 mdio_mrd
; /* 0x50C: MII Management Read Data */
138 u32 uaw0
; /* 0x700: Unicast address word 0 */
139 u32 uaw1
; /* 0x704: Unicast address word 1 */
142 /* Use MII register 1 (MII status register) to detect PHY */
143 #define PHY_DETECT_REG 1
146 * Mask used to verify certain PHY features (or register contents)
147 * in the register above:
148 * 0x1000: 10Mbps full duplex support
149 * 0x0800: 10Mbps half duplex support
150 * 0x0008: Auto-negotiation support
152 #define PHY_DETECT_MASK 0x1808
154 static inline int mdio_wait(struct axi_regs
*regs
)
158 /* Wait till MDIO interface is ready to accept a new transaction. */
159 while (timeout
&& (!(readl(®s
->mdio_mcr
)
160 & XAE_MDIO_MCR_READY_MASK
))) {
165 printf("%s: Timeout\n", __func__
);
171 static u32
phyread(struct axidma_priv
*priv
, u32 phyaddress
, u32 registernum
,
174 struct axi_regs
*regs
= priv
->iobase
;
180 mdioctrlreg
= ((phyaddress
<< XAE_MDIO_MCR_PHYAD_SHIFT
) &
181 XAE_MDIO_MCR_PHYAD_MASK
) |
182 ((registernum
<< XAE_MDIO_MCR_REGAD_SHIFT
)
183 & XAE_MDIO_MCR_REGAD_MASK
) |
184 XAE_MDIO_MCR_INITIATE_MASK
|
185 XAE_MDIO_MCR_OP_READ_MASK
;
187 writel(mdioctrlreg
, ®s
->mdio_mcr
);
193 *val
= readl(®s
->mdio_mrd
);
197 static u32
phywrite(struct axidma_priv
*priv
, u32 phyaddress
, u32 registernum
,
200 struct axi_regs
*regs
= priv
->iobase
;
206 mdioctrlreg
= ((phyaddress
<< XAE_MDIO_MCR_PHYAD_SHIFT
) &
207 XAE_MDIO_MCR_PHYAD_MASK
) |
208 ((registernum
<< XAE_MDIO_MCR_REGAD_SHIFT
)
209 & XAE_MDIO_MCR_REGAD_MASK
) |
210 XAE_MDIO_MCR_INITIATE_MASK
|
211 XAE_MDIO_MCR_OP_WRITE_MASK
;
214 writel(data
, ®s
->mdio_mwd
);
216 writel(mdioctrlreg
, ®s
->mdio_mcr
);
224 static int axiemac_phy_init(struct udevice
*dev
)
228 struct axidma_priv
*priv
= dev_get_priv(dev
);
229 struct axi_regs
*regs
= priv
->iobase
;
230 struct phy_device
*phydev
;
232 u32 supported
= SUPPORTED_10baseT_Half
|
233 SUPPORTED_10baseT_Full
|
234 SUPPORTED_100baseT_Half
|
235 SUPPORTED_100baseT_Full
|
236 SUPPORTED_1000baseT_Half
|
237 SUPPORTED_1000baseT_Full
;
239 /* Set default MDIO divisor */
240 writel(XAE_MDIO_DIV_DFT
| XAE_MDIO_MC_MDIOEN_MASK
, ®s
->mdio_mc
);
242 if (priv
->phyaddr
== -1) {
243 /* Detect the PHY address */
244 for (i
= 31; i
>= 0; i
--) {
245 ret
= phyread(priv
, i
, PHY_DETECT_REG
, &phyreg
);
246 if (!ret
&& (phyreg
!= 0xFFFF) &&
247 ((phyreg
& PHY_DETECT_MASK
) == PHY_DETECT_MASK
)) {
248 /* Found a valid PHY address */
250 debug("axiemac: Found valid phy address, %x\n",
257 /* Interface - look at tsec */
258 phydev
= phy_connect(priv
->bus
, priv
->phyaddr
, dev
, priv
->interface
);
260 phydev
->supported
&= supported
;
261 phydev
->advertising
= phydev
->supported
;
262 priv
->phydev
= phydev
;
268 /* Setting axi emac and phy to proper setting */
269 static int setup_phy(struct udevice
*dev
)
272 u32 speed
, emmc_reg
, ret
;
273 struct axidma_priv
*priv
= dev_get_priv(dev
);
274 struct axi_regs
*regs
= priv
->iobase
;
275 struct phy_device
*phydev
= priv
->phydev
;
277 if (priv
->interface
== PHY_INTERFACE_MODE_SGMII
) {
279 * In SGMII cases the isolate bit might set
280 * after DMA and ethernet resets and hence
281 * check and clear if set.
283 ret
= phyread(priv
, priv
->phyaddr
, MII_BMCR
, &temp
);
286 if (temp
& BMCR_ISOLATE
) {
287 temp
&= ~BMCR_ISOLATE
;
288 ret
= phywrite(priv
, priv
->phyaddr
, MII_BMCR
, temp
);
294 if (phy_startup(phydev
)) {
295 printf("axiemac: could not initialize PHY %s\n",
300 printf("%s: No link.\n", phydev
->dev
->name
);
304 switch (phydev
->speed
) {
306 speed
= XAE_EMMC_LINKSPD_1000
;
309 speed
= XAE_EMMC_LINKSPD_100
;
312 speed
= XAE_EMMC_LINKSPD_10
;
318 /* Setup the emac for the phy speed */
319 emmc_reg
= readl(®s
->emmc
);
320 emmc_reg
&= ~XAE_EMMC_LINKSPEED_MASK
;
323 /* Write new speed setting out to Axi Ethernet */
324 writel(emmc_reg
, ®s
->emmc
);
327 * Setting the operating speed of the MAC needs a delay. There
328 * doesn't seem to be register to poll, so please consider this
329 * during your application design.
336 /* STOP DMA transfers */
337 static void axiemac_stop(struct udevice
*dev
)
339 struct axidma_priv
*priv
= dev_get_priv(dev
);
342 /* Stop the hardware */
343 temp
= readl(&priv
->dmatx
->control
);
344 temp
&= ~XAXIDMA_CR_RUNSTOP_MASK
;
345 writel(temp
, &priv
->dmatx
->control
);
347 temp
= readl(&priv
->dmarx
->control
);
348 temp
&= ~XAXIDMA_CR_RUNSTOP_MASK
;
349 writel(temp
, &priv
->dmarx
->control
);
351 debug("axiemac: Halted\n");
354 static int axi_ethernet_init(struct axidma_priv
*priv
)
356 struct axi_regs
*regs
= priv
->iobase
;
360 * Check the status of the MgtRdy bit in the interrupt status
361 * registers. This must be done to allow the MGT clock to become stable
362 * for the Sgmii and 1000BaseX PHY interfaces. No other register reads
363 * will be valid until this bit is valid.
364 * The bit is always a 1 for all other PHY interfaces.
365 * Interrupt status and enable registers are not available in non
366 * processor mode and hence bypass in this mode
368 if (!priv
->eth_hasnobuf
) {
369 err
= wait_for_bit(__func__
, (const u32
*)®s
->is
,
370 XAE_INT_MGTRDY_MASK
, true, 200, false);
372 printf("%s: Timeout\n", __func__
);
377 * Stop the device and reset HW
380 writel(0, ®s
->ie
);
383 /* Disable the receiver */
384 writel(readl(®s
->rcw1
) & ~XAE_RCW1_RX_MASK
, ®s
->rcw1
);
387 * Stopping the receiver in mid-packet causes a dropped packet
388 * indication from HW. Clear it.
390 if (!priv
->eth_hasnobuf
) {
391 /* Set the interrupt status register to clear the interrupt */
392 writel(XAE_INT_RXRJECT_MASK
, ®s
->is
);
396 /* Set default MDIO divisor */
397 writel(XAE_MDIO_DIV_DFT
| XAE_MDIO_MC_MDIOEN_MASK
, ®s
->mdio_mc
);
399 debug("axiemac: InitHw done\n");
403 static int axiemac_write_hwaddr(struct udevice
*dev
)
405 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
406 struct axidma_priv
*priv
= dev_get_priv(dev
);
407 struct axi_regs
*regs
= priv
->iobase
;
409 /* Set the MAC address */
410 int val
= ((pdata
->enetaddr
[3] << 24) | (pdata
->enetaddr
[2] << 16) |
411 (pdata
->enetaddr
[1] << 8) | (pdata
->enetaddr
[0]));
412 writel(val
, ®s
->uaw0
);
414 val
= (pdata
->enetaddr
[5] << 8) | pdata
->enetaddr
[4];
415 val
|= readl(®s
->uaw1
) & ~XAE_UAW1_UNICASTADDR_MASK
;
416 writel(val
, ®s
->uaw1
);
420 /* Reset DMA engine */
421 static void axi_dma_init(struct axidma_priv
*priv
)
425 /* Reset the engine so the hardware starts from a known state */
426 writel(XAXIDMA_CR_RESET_MASK
, &priv
->dmatx
->control
);
427 writel(XAXIDMA_CR_RESET_MASK
, &priv
->dmarx
->control
);
429 /* At the initialization time, hardware should finish reset quickly */
431 /* Check transmit/receive channel */
432 /* Reset is done when the reset bit is low */
433 if (!((readl(&priv
->dmatx
->control
) |
434 readl(&priv
->dmarx
->control
))
435 & XAXIDMA_CR_RESET_MASK
)) {
440 printf("%s: Timeout\n", __func__
);
443 static int axiemac_start(struct udevice
*dev
)
445 struct axidma_priv
*priv
= dev_get_priv(dev
);
446 struct axi_regs
*regs
= priv
->iobase
;
449 debug("axiemac: Init started\n");
451 * Initialize AXIDMA engine. AXIDMA engine must be initialized before
452 * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
453 * reset, and since AXIDMA reset line is connected to AxiEthernet, this
454 * would ensure a reset of AxiEthernet.
458 /* Initialize AxiEthernet hardware. */
459 if (axi_ethernet_init(priv
))
462 /* Disable all RX interrupts before RxBD space setup */
463 temp
= readl(&priv
->dmarx
->control
);
464 temp
&= ~XAXIDMA_IRQ_ALL_MASK
;
465 writel(temp
, &priv
->dmarx
->control
);
467 /* Start DMA RX channel. Now it's ready to receive data.*/
468 writel((u32
)&rx_bd
, &priv
->dmarx
->current
);
471 memset(&rx_bd
, 0, sizeof(rx_bd
));
472 rx_bd
.next
= (u32
)&rx_bd
;
473 rx_bd
.phys
= (u32
)&rxframe
;
474 rx_bd
.cntrl
= sizeof(rxframe
);
475 /* Flush the last BD so DMA core could see the updates */
476 flush_cache((u32
)&rx_bd
, sizeof(rx_bd
));
478 /* It is necessary to flush rxframe because if you don't do it
479 * then cache can contain uninitialized data */
480 flush_cache((u32
)&rxframe
, sizeof(rxframe
));
482 /* Start the hardware */
483 temp
= readl(&priv
->dmarx
->control
);
484 temp
|= XAXIDMA_CR_RUNSTOP_MASK
;
485 writel(temp
, &priv
->dmarx
->control
);
487 /* Rx BD is ready - start */
488 writel((u32
)&rx_bd
, &priv
->dmarx
->tail
);
491 writel(XAE_TC_TX_MASK
, ®s
->tc
);
493 writel(XAE_RCW1_RX_MASK
, ®s
->rcw1
);
496 if (!setup_phy(dev
)) {
501 debug("axiemac: Init complete\n");
505 static int axiemac_send(struct udevice
*dev
, void *ptr
, int len
)
507 struct axidma_priv
*priv
= dev_get_priv(dev
);
510 if (len
> PKTSIZE_ALIGN
)
513 /* Flush packet to main memory to be trasfered by DMA */
514 flush_cache((u32
)ptr
, len
);
517 memset(&tx_bd
, 0, sizeof(tx_bd
));
518 /* At the end of the ring, link the last BD back to the top */
519 tx_bd
.next
= (u32
)&tx_bd
;
520 tx_bd
.phys
= (u32
)ptr
;
522 tx_bd
.cntrl
= len
| XAXIDMA_BD_CTRL_TXSOF_MASK
|
523 XAXIDMA_BD_CTRL_TXEOF_MASK
;
525 /* Flush the last BD so DMA core could see the updates */
526 flush_cache((u32
)&tx_bd
, sizeof(tx_bd
));
528 if (readl(&priv
->dmatx
->status
) & XAXIDMA_HALTED_MASK
) {
530 writel((u32
)&tx_bd
, &priv
->dmatx
->current
);
531 /* Start the hardware */
532 temp
= readl(&priv
->dmatx
->control
);
533 temp
|= XAXIDMA_CR_RUNSTOP_MASK
;
534 writel(temp
, &priv
->dmatx
->control
);
538 writel((u32
)&tx_bd
, &priv
->dmatx
->tail
);
540 /* Wait for transmission to complete */
541 debug("axiemac: Waiting for tx to be done\n");
543 while (timeout
&& (!(readl(&priv
->dmatx
->status
) &
544 (XAXIDMA_IRQ_DELAY_MASK
| XAXIDMA_IRQ_IOC_MASK
)))) {
549 printf("%s: Timeout\n", __func__
);
553 debug("axiemac: Sending complete\n");
557 static int isrxready(struct axidma_priv
*priv
)
561 /* Read pending interrupts */
562 status
= readl(&priv
->dmarx
->status
);
564 /* Acknowledge pending interrupts */
565 writel(status
& XAXIDMA_IRQ_ALL_MASK
, &priv
->dmarx
->status
);
568 * If Reception done interrupt is asserted, call RX call back function
569 * to handle the processed BDs and then raise the according flag.
571 if ((status
& (XAXIDMA_IRQ_DELAY_MASK
| XAXIDMA_IRQ_IOC_MASK
)))
577 static int axiemac_recv(struct udevice
*dev
, int flags
, uchar
**packetp
)
580 struct axidma_priv
*priv
= dev_get_priv(dev
);
583 /* Wait for an incoming packet */
584 if (!isrxready(priv
))
587 debug("axiemac: RX data ready\n");
589 /* Disable IRQ for a moment till packet is handled */
590 temp
= readl(&priv
->dmarx
->control
);
591 temp
&= ~XAXIDMA_IRQ_ALL_MASK
;
592 writel(temp
, &priv
->dmarx
->control
);
593 if (!priv
->eth_hasnobuf
)
594 length
= rx_bd
.app4
& 0xFFFF; /* max length mask */
596 length
= rx_bd
.status
& XAXIDMA_BD_STS_ACTUAL_LEN_MASK
;
599 print_buffer(&rxframe
, &rxframe
[0], 1, length
, 16);
606 static int axiemac_free_pkt(struct udevice
*dev
, uchar
*packet
, int length
)
608 struct axidma_priv
*priv
= dev_get_priv(dev
);
611 /* It is useful to clear buffer to be sure that it is consistent */
612 memset(rxframe
, 0, sizeof(rxframe
));
615 /* Clear the whole buffer and setup it again - all flags are cleared */
616 memset(&rx_bd
, 0, sizeof(rx_bd
));
617 rx_bd
.next
= (u32
)&rx_bd
;
618 rx_bd
.phys
= (u32
)&rxframe
;
619 rx_bd
.cntrl
= sizeof(rxframe
);
622 flush_cache((u32
)&rx_bd
, sizeof(rx_bd
));
624 /* It is necessary to flush rxframe because if you don't do it
625 * then cache will contain previous packet */
626 flush_cache((u32
)&rxframe
, sizeof(rxframe
));
628 /* Rx BD is ready - start again */
629 writel((u32
)&rx_bd
, &priv
->dmarx
->tail
);
631 debug("axiemac: RX completed, framelength = %d\n", length
);
636 static int axiemac_miiphy_read(struct mii_dev
*bus
, int addr
,
642 ret
= phyread(bus
->priv
, addr
, reg
, &value
);
643 debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr
, reg
,
648 static int axiemac_miiphy_write(struct mii_dev
*bus
, int addr
, int devad
,
651 debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr
, reg
, value
);
652 return phywrite(bus
->priv
, addr
, reg
, value
);
655 static int axi_emac_probe(struct udevice
*dev
)
657 struct axidma_priv
*priv
= dev_get_priv(dev
);
660 priv
->bus
= mdio_alloc();
661 priv
->bus
->read
= axiemac_miiphy_read
;
662 priv
->bus
->write
= axiemac_miiphy_write
;
663 priv
->bus
->priv
= priv
;
665 ret
= mdio_register_seq(priv
->bus
, dev
->seq
);
669 axiemac_phy_init(dev
);
674 static int axi_emac_remove(struct udevice
*dev
)
676 struct axidma_priv
*priv
= dev_get_priv(dev
);
679 mdio_unregister(priv
->bus
);
680 mdio_free(priv
->bus
);
685 static const struct eth_ops axi_emac_ops
= {
686 .start
= axiemac_start
,
687 .send
= axiemac_send
,
688 .recv
= axiemac_recv
,
689 .free_pkt
= axiemac_free_pkt
,
690 .stop
= axiemac_stop
,
691 .write_hwaddr
= axiemac_write_hwaddr
,
694 static int axi_emac_ofdata_to_platdata(struct udevice
*dev
)
696 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
697 struct axidma_priv
*priv
= dev_get_priv(dev
);
698 int node
= dev_of_offset(dev
);
700 const char *phy_mode
;
702 pdata
->iobase
= (phys_addr_t
)devfdt_get_addr(dev
);
703 priv
->iobase
= (struct axi_regs
*)pdata
->iobase
;
705 offset
= fdtdec_lookup_phandle(gd
->fdt_blob
, node
,
706 "axistream-connected");
708 printf("%s: axistream is not found\n", __func__
);
711 priv
->dmatx
= (struct axidma_reg
*)fdtdec_get_addr(gd
->fdt_blob
,
714 printf("%s: axi_dma register space not found\n", __func__
);
717 /* RX channel offset is 0x30 */
718 priv
->dmarx
= (struct axidma_reg
*)((u32
)priv
->dmatx
+ 0x30);
722 offset
= fdtdec_lookup_phandle(gd
->fdt_blob
, node
, "phy-handle");
724 priv
->phyaddr
= fdtdec_get_int(gd
->fdt_blob
, offset
, "reg", -1);
726 phy_mode
= fdt_getprop(gd
->fdt_blob
, node
, "phy-mode", NULL
);
728 pdata
->phy_interface
= phy_get_interface_by_name(phy_mode
);
729 if (pdata
->phy_interface
== -1) {
730 printf("%s: Invalid PHY interface '%s'\n", __func__
, phy_mode
);
733 priv
->interface
= pdata
->phy_interface
;
735 priv
->eth_hasnobuf
= fdtdec_get_bool(gd
->fdt_blob
, node
,
736 "xlnx,eth-hasnobuf");
738 printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong
)priv
->iobase
,
739 priv
->phyaddr
, phy_string_for_interface(priv
->interface
));
744 static const struct udevice_id axi_emac_ids
[] = {
745 { .compatible
= "xlnx,axi-ethernet-1.00.a" },
749 U_BOOT_DRIVER(axi_emac
) = {
752 .of_match
= axi_emac_ids
,
753 .ofdata_to_platdata
= axi_emac_ofdata_to_platdata
,
754 .probe
= axi_emac_probe
,
755 .remove
= axi_emac_remove
,
756 .ops
= &axi_emac_ops
,
757 .priv_auto_alloc_size
= sizeof(struct axidma_priv
),
758 .platdata_auto_alloc_size
= sizeof(struct eth_pdata
),