drivers/net/xilinx_axi_emac.c

   1 /*
   2  * Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
   3  * Copyright (C) 2011 PetaLogix
   4  * Copyright (C) 2010 Xilinx, Inc. All rights reserved.
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <net.h>
  28 #include <malloc.h>
  29 #include <asm/io.h>
  30 #include <phy.h>
  31 #include <miiphy.h>
  32
  33 #if !defined(CONFIG_PHYLIB)
  34 # error AXI_ETHERNET requires PHYLIB
  35 #endif
  36
  37 /* Link setup */
  38 #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
  39 #define XAE_EMMC_LINKSPD_10     0x00000000 /* Link Speed mask for 10 Mbit */
  40 #define XAE_EMMC_LINKSPD_100    0x40000000 /* Link Speed mask for 100 Mbit */
  41 #define XAE_EMMC_LINKSPD_1000   0x80000000 /* Link Speed mask for 1000 Mbit */
  42
  43 /* Interrupt Status/Enable/Mask Registers bit definitions */
  44 #define XAE_INT_RXRJECT_MASK    0x00000008 /* Rx frame rejected */
  45 #define XAE_INT_MGTRDY_MASK     0x00000080 /* MGT clock Lock */
  46
  47 /* Receive Configuration Word 1 (RCW1) Register bit definitions */
  48 #define XAE_RCW1_RX_MASK        0x10000000 /* Receiver enable */
  49
  50 /* Transmitter Configuration (TC) Register bit definitions */
  51 #define XAE_TC_TX_MASK          0x10000000 /* Transmitter enable */
  52
  53 #define XAE_UAW1_UNICASTADDR_MASK       0x0000FFFF
  54
  55 /* MDIO Management Configuration (MC) Register bit definitions */
  56 #define XAE_MDIO_MC_MDIOEN_MASK         0x00000040 /* MII management enable*/
  57
  58 /* MDIO Management Control Register (MCR) Register bit definitions */
  59 #define XAE_MDIO_MCR_PHYAD_MASK         0x1F000000 /* Phy Address Mask */
  60 #define XAE_MDIO_MCR_PHYAD_SHIFT        24         /* Phy Address Shift */
  61 #define XAE_MDIO_MCR_REGAD_MASK         0x001F0000 /* Reg Address Mask */
  62 #define XAE_MDIO_MCR_REGAD_SHIFT        16         /* Reg Address Shift */
  63 #define XAE_MDIO_MCR_OP_READ_MASK       0x00008000 /* Op Code Read Mask */
  64 #define XAE_MDIO_MCR_OP_WRITE_MASK      0x00004000 /* Op Code Write Mask */
  65 #define XAE_MDIO_MCR_INITIATE_MASK      0x00000800 /* Ready Mask */
  66 #define XAE_MDIO_MCR_READY_MASK         0x00000080 /* Ready Mask */
  67
  68 #define XAE_MDIO_DIV_DFT        29      /* Default MDIO clock divisor */
  69
  70 /* DMA macros */
  71 /* Bitmasks of XAXIDMA_CR_OFFSET register */
  72 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
  73 #define XAXIDMA_CR_RESET_MASK   0x00000004 /* Reset DMA engine */
  74
  75 /* Bitmasks of XAXIDMA_SR_OFFSET register */
  76 #define XAXIDMA_HALTED_MASK     0x00000001  /* DMA channel halted */
  77
  78 /* Bitmask for interrupts */
  79 #define XAXIDMA_IRQ_IOC_MASK    0x00001000 /* Completion intr */
  80 #define XAXIDMA_IRQ_DELAY_MASK  0x00002000 /* Delay interrupt */
  81 #define XAXIDMA_IRQ_ALL_MASK    0x00007000 /* All interrupts */
  82
  83 /* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */
  84 #define XAXIDMA_BD_CTRL_TXSOF_MASK      0x08000000 /* First tx packet */
  85 #define XAXIDMA_BD_CTRL_TXEOF_MASK      0x04000000 /* Last tx packet */
  86
  87 #define DMAALIGN        128
  88
  89 static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
  90
  91 /* Reflect dma offsets */
  92 struct axidma_reg {
  93         u32 control; /* DMACR */
  94         u32 status; /* DMASR */
  95         u32 current; /* CURDESC */
  96         u32 reserved;
  97         u32 tail; /* TAILDESC */
  98 };
  99
 100 /* Private driver structures */
 101 struct axidma_priv {
 102         struct axidma_reg *dmatx;
 103         struct axidma_reg *dmarx;
 104         int phyaddr;
 105
 106         struct phy_device *phydev;
 107         struct mii_dev *bus;
 108 };
 109
 110 /* BD descriptors */
 111 struct axidma_bd {
 112         u32 next;       /* Next descriptor pointer */
 113         u32 reserved1;
 114         u32 phys;       /* Buffer address */
 115         u32 reserved2;
 116         u32 reserved3;
 117         u32 reserved4;
 118         u32 cntrl;      /* Control */
 119         u32 status;     /* Status */
 120         u32 app0;
 121         u32 app1;       /* TX start << 16 | insert */
 122         u32 app2;       /* TX csum seed */
 123         u32 app3;
 124         u32 app4;
 125         u32 sw_id_offset;
 126         u32 reserved5;
 127         u32 reserved6;
 128 };
 129
 130 /* Static BDs - driver uses only one BD */
 131 static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN)));
 132 static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN)));
 133
 134 struct axi_regs {
 135         u32 reserved[3];
 136         u32 is; /* 0xC: Interrupt status */
 137         u32 reserved2;
 138         u32 ie; /* 0x14: Interrupt enable */
 139         u32 reserved3[251];
 140         u32 rcw1; /* 0x404: Rx Configuration Word 1 */
 141         u32 tc; /* 0x408: Tx Configuration */
 142         u32 reserved4;
 143         u32 emmc; /* 0x410: EMAC mode configuration */
 144         u32 reserved5[59];
 145         u32 mdio_mc; /* 0x500: MII Management Config */
 146         u32 mdio_mcr; /* 0x504: MII Management Control */
 147         u32 mdio_mwd; /* 0x508: MII Management Write Data */
 148         u32 mdio_mrd; /* 0x50C: MII Management Read Data */
 149         u32 reserved6[124];
 150         u32 uaw0; /* 0x700: Unicast address word 0 */
 151         u32 uaw1; /* 0x704: Unicast address word 1 */
 152 };
 153
 154 /* Use MII register 1 (MII status register) to detect PHY */
 155 #define PHY_DETECT_REG  1
 156
 157 /*
 158  * Mask used to verify certain PHY features (or register contents)
 159  * in the register above:
 160  *  0x1000: 10Mbps full duplex support
 161  *  0x0800: 10Mbps half duplex support
 162  *  0x0008: Auto-negotiation support
 163  */
 164 #define PHY_DETECT_MASK 0x1808
 165
 166 static inline int mdio_wait(struct eth_device *dev)
 167 {
 168         struct axi_regs *regs = (struct axi_regs *)dev->iobase;
 169         u32 timeout = 200;
 170
 171         /* Wait till MDIO interface is ready to accept a new transaction. */
 172         while (timeout && (!(in_be32(&regs->mdio_mcr)
 173                                                 & XAE_MDIO_MCR_READY_MASK))) {
 174                 timeout--;
 175                 udelay(1);
 176         }
 177         if (!timeout) {
 178                 printf("%s: Timeout\n", __func__);
 179                 return 1;
 180         }
 181         return 0;
 182 }
 183
 184 static u32 phyread(struct eth_device *dev, u32 phyaddress, u32 registernum,
 185                                                                 u16 *val)
 186 {
 187         struct axi_regs *regs = (struct axi_regs *)dev->iobase;
 188         u32 mdioctrlreg = 0;
 189
 190         if (mdio_wait(dev))
 191                 return 1;
 192
 193         mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
 194                         XAE_MDIO_MCR_PHYAD_MASK) |
 195                         ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
 196                         & XAE_MDIO_MCR_REGAD_MASK) |
 197                         XAE_MDIO_MCR_INITIATE_MASK |
 198                         XAE_MDIO_MCR_OP_READ_MASK;
 199
 200         out_be32(&regs->mdio_mcr, mdioctrlreg);
 201
 202         if (mdio_wait(dev))
 203                 return 1;
 204
 205         /* Read data */
 206         *val = in_be32(&regs->mdio_mrd);
 207         return 0;
 208 }
 209
 210 static u32 phywrite(struct eth_device *dev, u32 phyaddress, u32 registernum,
 211                                                                 u32 data)
 212 {
 213         struct axi_regs *regs = (struct axi_regs *)dev->iobase;
 214         u32 mdioctrlreg = 0;
 215
 216         if (mdio_wait(dev))
 217                 return 1;
 218
 219         mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
 220                         XAE_MDIO_MCR_PHYAD_MASK) |
 221                         ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
 222                         & XAE_MDIO_MCR_REGAD_MASK) |
 223                         XAE_MDIO_MCR_INITIATE_MASK |
 224                         XAE_MDIO_MCR_OP_WRITE_MASK;
 225
 226         /* Write data */
 227         out_be32(&regs->mdio_mwd, data);
 228
 229         out_be32(&regs->mdio_mcr, mdioctrlreg);
 230
 231         if (mdio_wait(dev))
 232                 return 1;
 233
 234         return 0;
 235 }
 236
 237 /* Setting axi emac and phy to proper setting */
 238 static int setup_phy(struct eth_device *dev)
 239 {
 240         u16 phyreg;
 241         u32 i, speed, emmc_reg, ret;
 242         struct axidma_priv *priv = dev->priv;
 243         struct axi_regs *regs = (struct axi_regs *)dev->iobase;
 244         struct phy_device *phydev;
 245
 246         u32 supported = SUPPORTED_10baseT_Half |
 247                         SUPPORTED_10baseT_Full |
 248                         SUPPORTED_100baseT_Half |
 249                         SUPPORTED_100baseT_Full |
 250                         SUPPORTED_1000baseT_Half |
 251                         SUPPORTED_1000baseT_Full;
 252
 253         if (priv->phyaddr == -1) {
 254                 /* Detect the PHY address */
 255                 for (i = 31; i >= 0; i--) {
 256                         ret = phyread(dev, i, PHY_DETECT_REG, &phyreg);
 257                         if (!ret && (phyreg != 0xFFFF) &&
 258                         ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
 259                                 /* Found a valid PHY address */
 260                                 priv->phyaddr = i;
 261                                 debug("axiemac: Found valid phy address, %x\n",
 262                                                                         phyreg);
 263                                 break;
 264                         }
 265                 }
 266         }
 267
 268         /* Interface - look at tsec */
 269         phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0);
 270
 271         phydev->supported &= supported;
 272         phydev->advertising = phydev->supported;
 273         priv->phydev = phydev;
 274         phy_config(phydev);
 275         if (phy_startup(phydev)) {
 276                 printf("axiemac: could not initialize PHY %s\n",
 277                        phydev->dev->name);
 278                 return 0;
 279         }
 280
 281         switch (phydev->speed) {
 282         case 1000:
 283                 speed = XAE_EMMC_LINKSPD_1000;
 284                 break;
 285         case 100:
 286                 speed = XAE_EMMC_LINKSPD_100;
 287                 break;
 288         case 10:
 289                 speed = XAE_EMMC_LINKSPD_10;
 290                 break;
 291         default:
 292                 return 0;
 293         }
 294
 295         /* Setup the emac for the phy speed */
 296         emmc_reg = in_be32(&regs->emmc);
 297         emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
 298         emmc_reg |= speed;
 299
 300         /* Write new speed setting out to Axi Ethernet */
 301         out_be32(&regs->emmc, emmc_reg);
 302
 303         /*
 304         * Setting the operating speed of the MAC needs a delay. There
 305         * doesn't seem to be register to poll, so please consider this
 306         * during your application design.
 307         */
 308         udelay(1);
 309
 310         return 1;
 311 }
 312
 313 /* STOP DMA transfers */
 314 static void axiemac_halt(struct eth_device *dev)
 315 {
 316         struct axidma_priv *priv = dev->priv;
 317         u32 temp;
 318
 319         /* Stop the hardware */
 320         temp = in_be32(&priv->dmatx->control);
 321         temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
 322         out_be32(&priv->dmatx->control, temp);
 323
 324         temp = in_be32(&priv->dmarx->control);
 325         temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
 326         out_be32(&priv->dmarx->control, temp);
 327
 328         debug("axiemac: Halted\n");
 329 }
 330
 331 static int axi_ethernet_init(struct eth_device *dev)
 332 {
 333         struct axi_regs *regs = (struct axi_regs *)dev->iobase;
 334         u32 timeout = 200;
 335
 336         /*
 337          * Check the status of the MgtRdy bit in the interrupt status
 338          * registers. This must be done to allow the MGT clock to become stable
 339          * for the Sgmii and 1000BaseX PHY interfaces. No other register reads
 340          * will be valid until this bit is valid.
 341          * The bit is always a 1 for all other PHY interfaces.
 342          */
 343         while (timeout && (!(in_be32(&regs->is) & XAE_INT_MGTRDY_MASK))) {
 344                 timeout--;
 345                 udelay(1);
 346         }
 347         if (!timeout) {
 348                 printf("%s: Timeout\n", __func__);
 349                 return 1;
 350         }
 351
 352         /* Stop the device and reset HW */
 353         /* Disable interrupts */
 354         out_be32(&regs->ie, 0);
 355
 356         /* Disable the receiver */
 357         out_be32(&regs->rcw1, in_be32(&regs->rcw1) & ~XAE_RCW1_RX_MASK);
 358
 359         /*
 360          * Stopping the receiver in mid-packet causes a dropped packet
 361          * indication from HW. Clear it.
 362          */
 363         /* Set the interrupt status register to clear the interrupt */
 364         out_be32(&regs->is, XAE_INT_RXRJECT_MASK);
 365
 366         /* Setup HW */
 367         /* Set default MDIO divisor */
 368         out_be32(&regs->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK);
 369
 370         debug("axiemac: InitHw done\n");
 371         return 0;
 372 }
 373
 374 static int axiemac_setup_mac(struct eth_device *dev)
 375 {
 376         struct axi_regs *regs = (struct axi_regs *)dev->iobase;
 377
 378         /* Set the MAC address */
 379         int val = ((dev->enetaddr[3] << 24) | (dev->enetaddr[2] << 16) |
 380                 (dev->enetaddr[1] << 8) | (dev->enetaddr[0]));
 381         out_be32(&regs->uaw0, val);
 382
 383         val = (dev->enetaddr[5] << 8) | dev->enetaddr[4] ;
 384         val |= in_be32(&regs->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
 385         out_be32(&regs->uaw1, val);
 386         return 0;
 387 }
 388
 389 /* Reset DMA engine */
 390 static void axi_dma_init(struct eth_device *dev)
 391 {
 392         struct axidma_priv *priv = dev->priv;
 393         u32 timeout = 500;
 394
 395         /* Reset the engine so the hardware starts from a known state */
 396         out_be32(&priv->dmatx->control, XAXIDMA_CR_RESET_MASK);
 397         out_be32(&priv->dmarx->control, XAXIDMA_CR_RESET_MASK);
 398
 399         /* At the initialization time, hardware should finish reset quickly */
 400         while (timeout--) {
 401                 /* Check transmit/receive channel */
 402                 /* Reset is done when the reset bit is low */
 403                 if (!(in_be32(&priv->dmatx->control) |
 404                                 in_be32(&priv->dmarx->control))
 405                                                 & XAXIDMA_CR_RESET_MASK) {
 406                         break;
 407                 }
 408         }
 409         if (!timeout)
 410                 printf("%s: Timeout\n", __func__);
 411 }
 412
 413 static int axiemac_init(struct eth_device *dev, bd_t * bis)
 414 {
 415         struct axidma_priv *priv = dev->priv;
 416         struct axi_regs *regs = (struct axi_regs *)dev->iobase;
 417         u32 temp;
 418
 419         debug("axiemac: Init started\n");
 420         /*
 421          * Initialize AXIDMA engine. AXIDMA engine must be initialized before
 422          * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
 423          * reset, and since AXIDMA reset line is connected to AxiEthernet, this
 424          * would ensure a reset of AxiEthernet.
 425          */
 426         axi_dma_init(dev);
 427
 428         /* Initialize AxiEthernet hardware. */
 429         if (axi_ethernet_init(dev))
 430                 return -1;
 431
 432         /* Disable all RX interrupts before RxBD space setup */
 433         temp = in_be32(&priv->dmarx->control);
 434         temp &= ~XAXIDMA_IRQ_ALL_MASK;
 435         out_be32(&priv->dmarx->control, temp);
 436
 437         /* Start DMA RX channel. Now it's ready to receive data.*/
 438         out_be32(&priv->dmarx->current, (u32)&rx_bd);
 439
 440         /* Setup the BD. */
 441         memset(&rx_bd, 0, sizeof(rx_bd));
 442         rx_bd.next = (u32)&rx_bd;
 443         rx_bd.phys = (u32)&rxframe;
 444         rx_bd.cntrl = sizeof(rxframe);
 445         /* Flush the last BD so DMA core could see the updates */
 446         flush_cache((u32)&rx_bd, sizeof(rx_bd));
 447
 448         /* It is necessary to flush rxframe because if you don't do it
 449          * then cache can contain uninitialized data */
 450         flush_cache((u32)&rxframe, sizeof(rxframe));
 451
 452         /* Start the hardware */
 453         temp = in_be32(&priv->dmarx->control);
 454         temp |= XAXIDMA_CR_RUNSTOP_MASK;
 455         out_be32(&priv->dmarx->control, temp);
 456
 457         /* Rx BD is ready - start */
 458         out_be32(&priv->dmarx->tail, (u32)&rx_bd);
 459
 460         /* Enable TX */
 461         out_be32(&regs->tc, XAE_TC_TX_MASK);
 462         /* Enable RX */
 463         out_be32(&regs->rcw1, XAE_RCW1_RX_MASK);
 464
 465         /* PHY setup */
 466         if (!setup_phy(dev)) {
 467                 axiemac_halt(dev);
 468                 return -1;
 469         }
 470
 471         debug("axiemac: Init complete\n");
 472         return 0;
 473 }
 474
 475 static int axiemac_send(struct eth_device *dev, void *ptr, int len)
 476 {
 477         struct axidma_priv *priv = dev->priv;
 478         u32 timeout;
 479
 480         if (len > PKTSIZE_ALIGN)
 481                 len = PKTSIZE_ALIGN;
 482
 483         /* Flush packet to main memory to be trasfered by DMA */
 484         flush_cache((u32)ptr, len);
 485
 486         /* Setup Tx BD */
 487         memset(&tx_bd, 0, sizeof(tx_bd));
 488         /* At the end of the ring, link the last BD back to the top */
 489         tx_bd.next = (u32)&tx_bd;
 490         tx_bd.phys = (u32)ptr;
 491         /* Save len */
 492         tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK |
 493                                                 XAXIDMA_BD_CTRL_TXEOF_MASK;
 494
 495         /* Flush the last BD so DMA core could see the updates */
 496         flush_cache((u32)&tx_bd, sizeof(tx_bd));
 497
 498         if (in_be32(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
 499                 u32 temp;
 500                 out_be32(&priv->dmatx->current, (u32)&tx_bd);
 501                 /* Start the hardware */
 502                 temp = in_be32(&priv->dmatx->control);
 503                 temp |= XAXIDMA_CR_RUNSTOP_MASK;
 504                 out_be32(&priv->dmatx->control, temp);
 505         }
 506
 507         /* Start transfer */
 508         out_be32(&priv->dmatx->tail, (u32)&tx_bd);
 509
 510         /* Wait for transmission to complete */
 511         debug("axiemac: Waiting for tx to be done\n");
 512         timeout = 200;
 513         while (timeout && (!in_be32(&priv->dmatx->status) &
 514                         (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK))) {
 515                 timeout--;
 516                 udelay(1);
 517         }
 518         if (!timeout) {
 519                 printf("%s: Timeout\n", __func__);
 520                 return 1;
 521         }
 522
 523         debug("axiemac: Sending complete\n");
 524         return 0;
 525 }
 526
 527 static int isrxready(struct eth_device *dev)
 528 {
 529         u32 status;
 530         struct axidma_priv *priv = dev->priv;
 531
 532         /* Read pending interrupts */
 533         status = in_be32(&priv->dmarx->status);
 534
 535         /* Acknowledge pending interrupts */
 536         out_be32(&priv->dmarx->status, status & XAXIDMA_IRQ_ALL_MASK);
 537
 538         /*
 539          * If Reception done interrupt is asserted, call RX call back function
 540          * to handle the processed BDs and then raise the according flag.
 541          */
 542         if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))
 543                 return 1;
 544
 545         return 0;
 546 }
 547
 548 static int axiemac_recv(struct eth_device *dev)
 549 {
 550         u32 length;
 551         struct axidma_priv *priv = dev->priv;
 552         u32 temp;
 553
 554         /* Wait for an incoming packet */
 555         if (!isrxready(dev))
 556                 return 0;
 557
 558         debug("axiemac: RX data ready\n");
 559
 560         /* Disable IRQ for a moment till packet is handled */
 561         temp = in_be32(&priv->dmarx->control);
 562         temp &= ~XAXIDMA_IRQ_ALL_MASK;
 563         out_be32(&priv->dmarx->control, temp);
 564
 565         length = rx_bd.app4 & 0xFFFF; /* max length mask */
 566 #ifdef DEBUG
 567         print_buffer(&rxframe, &rxframe[0], 1, length, 16);
 568 #endif
 569         /* Pass the received frame up for processing */
 570         if (length)
 571                 NetReceive(rxframe, length);
 572
 573 #ifdef DEBUG
 574         /* It is useful to clear buffer to be sure that it is consistent */
 575         memset(rxframe, 0, sizeof(rxframe));
 576 #endif
 577         /* Setup RxBD */
 578         /* Clear the whole buffer and setup it again - all flags are cleared */
 579         memset(&rx_bd, 0, sizeof(rx_bd));
 580         rx_bd.next = (u32)&rx_bd;
 581         rx_bd.phys = (u32)&rxframe;
 582         rx_bd.cntrl = sizeof(rxframe);
 583
 584         /* Write bd to HW */
 585         flush_cache((u32)&rx_bd, sizeof(rx_bd));
 586
 587         /* It is necessary to flush rxframe because if you don't do it
 588          * then cache will contain previous packet */
 589         flush_cache((u32)&rxframe, sizeof(rxframe));
 590
 591         /* Rx BD is ready - start again */
 592         out_be32(&priv->dmarx->tail, (u32)&rx_bd);
 593
 594         debug("axiemac: RX completed, framelength = %d\n", length);
 595
 596         return length;
 597 }
 598
 599 static int axiemac_miiphy_read(const char *devname, uchar addr,
 600                                                         uchar reg, ushort *val)
 601 {
 602         struct eth_device *dev = eth_get_dev();
 603         u32 ret;
 604
 605         ret = phyread(dev, addr, reg, val);
 606         debug("axiemac: Read MII 0x%x, 0x%x, 0x%x\n", addr, reg, *val);
 607         return ret;
 608 }
 609
 610 static int axiemac_miiphy_write(const char *devname, uchar addr,
 611                                                         uchar reg, ushort val)
 612 {
 613         struct eth_device *dev = eth_get_dev();
 614
 615         debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val);
 616         return phywrite(dev, addr, reg, val);
 617 }
 618
 619 static int axiemac_bus_reset(struct mii_dev *bus)
 620 {
 621         debug("axiemac: Bus reset\n");
 622         return 0;
 623 }
 624
 625 int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr,
 626                                                         unsigned long dma_addr)
 627 {
 628         struct eth_device *dev;
 629         struct axidma_priv *priv;
 630
 631         dev = calloc(1, sizeof(struct eth_device));
 632         if (dev == NULL)
 633                 return -1;
 634
 635         dev->priv = calloc(1, sizeof(struct axidma_priv));
 636         if (dev->priv == NULL) {
 637                 free(dev);
 638                 return -1;
 639         }
 640         priv = dev->priv;
 641
 642         sprintf(dev->name, "aximac.%lx", base_addr);
 643
 644         dev->iobase = base_addr;
 645         priv->dmatx = (struct axidma_reg *)dma_addr;
 646         /* RX channel offset is 0x30 */
 647         priv->dmarx = (struct axidma_reg *)(dma_addr + 0x30);
 648         dev->init = axiemac_init;
 649         dev->halt = axiemac_halt;
 650         dev->send = axiemac_send;
 651         dev->recv = axiemac_recv;
 652         dev->write_hwaddr = axiemac_setup_mac;
 653
 654 #ifdef CONFIG_PHY_ADDR
 655         priv->phyaddr = CONFIG_PHY_ADDR;
 656 #else
 657         priv->phyaddr = -1;
 658 #endif
 659
 660         eth_register(dev);
 661
 662 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
 663         miiphy_register(dev->name, axiemac_miiphy_read, axiemac_miiphy_write);
 664         priv->bus = miiphy_get_dev_by_name(dev->name);
 665         priv->bus->reset = axiemac_bus_reset;
 666 #endif
 667         return 1;
 668 }