2 * (C) Copyright 2007-2009 Michal Simek
3 * (C) Copyright 2003 Xilinx Inc.
5 * Michal SIMEK <monstr@monstr.eu>
7 * SPDX-License-Identifier: GPL-2.0+
20 #include <linux/errno.h>
21 #include <linux/kernel.h>
24 DECLARE_GLOBAL_DATA_PTR
;
26 #define ENET_ADDR_LENGTH 6
27 #define ETH_FCS_LEN 4 /* Octets in the FCS */
30 #define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
31 /* Xmit interrupt enable bit */
32 #define XEL_TSR_XMIT_IE_MASK 0x00000008UL
33 /* Program the MAC address */
34 #define XEL_TSR_PROGRAM_MASK 0x00000002UL
35 /* define for programming the MAC address into the EMAC Lite */
36 #define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
38 /* Transmit packet length upper byte */
39 #define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
40 /* Transmit packet length lower byte */
41 #define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
44 #define XEL_RSR_RECV_DONE_MASK 0x00000001UL
45 /* Recv interrupt enable bit */
46 #define XEL_RSR_RECV_IE_MASK 0x00000008UL
48 /* MDIO Address Register Bit Masks */
49 #define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */
50 #define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */
51 #define XEL_MDIOADDR_PHYADR_SHIFT 5
52 #define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */
54 /* MDIO Write Data Register Bit Masks */
55 #define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */
57 /* MDIO Read Data Register Bit Masks */
58 #define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */
60 /* MDIO Control Register Bit Masks */
61 #define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */
62 #define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */
64 struct emaclite_regs
{
65 u32 tx_ping
; /* 0x0 - TX Ping buffer */
67 u32 mdioaddr
; /* 0x7e4 - MDIO Address Register */
68 u32 mdiowr
; /* 0x7e8 - MDIO Write Data Register */
69 u32 mdiord
;/* 0x7ec - MDIO Read Data Register */
70 u32 mdioctrl
; /* 0x7f0 - MDIO Control Register */
71 u32 tx_ping_tplr
; /* 0x7f4 - Tx packet length */
72 u32 global_interrupt
; /* 0x7f8 - Global interrupt enable */
73 u32 tx_ping_tsr
; /* 0x7fc - Tx status */
74 u32 tx_pong
; /* 0x800 - TX Pong buffer */
76 u32 tx_pong_tplr
; /* 0xff4 - Tx packet length */
77 u32 reserved3
; /* 0xff8 */
78 u32 tx_pong_tsr
; /* 0xffc - Tx status */
79 u32 rx_ping
; /* 0x1000 - Receive Buffer */
81 u32 rx_ping_rsr
; /* 0x17fc - Rx status */
82 u32 rx_pong
; /* 0x1800 - Receive Buffer */
84 u32 rx_pong_rsr
; /* 0x1ffc - Rx status */
88 bool use_rx_pong_buffer_next
; /* Next RX buffer to read from */
89 u32 txpp
; /* TX ping pong buffer */
90 u32 rxpp
; /* RX ping pong buffer */
92 struct emaclite_regs
*regs
;
93 struct phy_device
*phydev
;
97 static uchar etherrxbuff
[PKTSIZE_ALIGN
]; /* Receive buffer */
99 static void xemaclite_alignedread(u32
*srcptr
, void *destptr
, u32 bytecount
)
108 from32ptr
= (u32
*) srcptr
;
110 /* Word aligned buffer, no correction needed. */
111 to32ptr
= (u32
*) destptr
;
112 while (bytecount
> 3) {
113 *to32ptr
++ = *from32ptr
++;
116 to8ptr
= (u8
*) to32ptr
;
118 alignbuffer
= *from32ptr
++;
119 from8ptr
= (u8
*) &alignbuffer
;
121 for (i
= 0; i
< bytecount
; i
++)
122 *to8ptr
++ = *from8ptr
++;
125 static void xemaclite_alignedwrite(void *srcptr
, u32
*destptr
, u32 bytecount
)
129 u32
*to32ptr
= (u32
*) destptr
;
134 from32ptr
= (u32
*) srcptr
;
135 while (bytecount
> 3) {
137 *to32ptr
++ = *from32ptr
++;
142 to8ptr
= (u8
*) &alignbuffer
;
143 from8ptr
= (u8
*) from32ptr
;
145 for (i
= 0; i
< bytecount
; i
++)
146 *to8ptr
++ = *from8ptr
++;
148 *to32ptr
++ = alignbuffer
;
151 static int wait_for_bit(const char *func
, u32
*reg
, const u32 mask
,
152 bool set
, unsigned int timeout
)
155 unsigned long start
= get_timer(0);
158 val
= __raw_readl(reg
);
163 if ((val
& mask
) == mask
)
166 if (get_timer(start
) > timeout
)
177 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
178 func
, reg
, mask
, set
);
183 static int mdio_wait(struct emaclite_regs
*regs
)
185 return wait_for_bit(__func__
, ®s
->mdioctrl
,
186 XEL_MDIOCTRL_MDIOSTS_MASK
, false, 2000);
189 static u32
phyread(struct xemaclite
*emaclite
, u32 phyaddress
, u32 registernum
,
192 struct emaclite_regs
*regs
= emaclite
->regs
;
197 u32 ctrl_reg
= __raw_readl(®s
->mdioctrl
);
198 __raw_writel(XEL_MDIOADDR_OP_MASK
199 | ((phyaddress
<< XEL_MDIOADDR_PHYADR_SHIFT
)
200 | registernum
), ®s
->mdioaddr
);
201 __raw_writel(ctrl_reg
| XEL_MDIOCTRL_MDIOSTS_MASK
, ®s
->mdioctrl
);
207 *data
= __raw_readl(®s
->mdiord
);
211 static u32
phywrite(struct xemaclite
*emaclite
, u32 phyaddress
, u32 registernum
,
214 struct emaclite_regs
*regs
= emaclite
->regs
;
220 * Write the PHY address, register number and clear the OP bit in the
221 * MDIO Address register and then write the value into the MDIO Write
222 * Data register. Finally, set the Status bit in the MDIO Control
223 * register to start a MDIO write transaction.
225 u32 ctrl_reg
= __raw_readl(®s
->mdioctrl
);
226 __raw_writel(~XEL_MDIOADDR_OP_MASK
227 & ((phyaddress
<< XEL_MDIOADDR_PHYADR_SHIFT
)
228 | registernum
), ®s
->mdioaddr
);
229 __raw_writel(data
, ®s
->mdiowr
);
230 __raw_writel(ctrl_reg
| XEL_MDIOCTRL_MDIOSTS_MASK
, ®s
->mdioctrl
);
238 static void emaclite_stop(struct udevice
*dev
)
243 /* Use MII register 1 (MII status register) to detect PHY */
244 #define PHY_DETECT_REG 1
246 /* Mask used to verify certain PHY features (or register contents)
247 * in the register above:
248 * 0x1000: 10Mbps full duplex support
249 * 0x0800: 10Mbps half duplex support
250 * 0x0008: Auto-negotiation support
252 #define PHY_DETECT_MASK 0x1808
254 static int setup_phy(struct udevice
*dev
)
258 struct xemaclite
*emaclite
= dev_get_priv(dev
);
259 struct phy_device
*phydev
;
261 u32 supported
= SUPPORTED_10baseT_Half
|
262 SUPPORTED_10baseT_Full
|
263 SUPPORTED_100baseT_Half
|
264 SUPPORTED_100baseT_Full
;
266 if (emaclite
->phyaddr
!= -1) {
267 phyread(emaclite
, emaclite
->phyaddr
, PHY_DETECT_REG
, &phyreg
);
268 if ((phyreg
!= 0xFFFF) &&
269 ((phyreg
& PHY_DETECT_MASK
) == PHY_DETECT_MASK
)) {
270 /* Found a valid PHY address */
271 debug("Default phy address %d is valid\n",
274 debug("PHY address is not setup correctly %d\n",
276 emaclite
->phyaddr
= -1;
280 if (emaclite
->phyaddr
== -1) {
281 /* detect the PHY address */
282 for (i
= 31; i
>= 0; i
--) {
283 phyread(emaclite
, i
, PHY_DETECT_REG
, &phyreg
);
284 if ((phyreg
!= 0xFFFF) &&
285 ((phyreg
& PHY_DETECT_MASK
) == PHY_DETECT_MASK
)) {
286 /* Found a valid PHY address */
287 emaclite
->phyaddr
= i
;
288 debug("emaclite: Found valid phy address, %d\n",
295 /* interface - look at tsec */
296 phydev
= phy_connect(emaclite
->bus
, emaclite
->phyaddr
, dev
,
297 PHY_INTERFACE_MODE_MII
);
299 * Phy can support 1000baseT but device NOT that's why phydev->supported
300 * must be setup for 1000baseT. phydev->advertising setups what speeds
301 * will be used for autonegotiation where 1000baseT must be disabled.
303 phydev
->supported
= supported
| SUPPORTED_1000baseT_Half
|
304 SUPPORTED_1000baseT_Full
;
305 phydev
->advertising
= supported
;
306 emaclite
->phydev
= phydev
;
308 ret
= phy_startup(phydev
);
313 printf("%s: No link.\n", phydev
->dev
->name
);
317 /* Do not setup anything */
321 static int emaclite_start(struct udevice
*dev
)
323 struct xemaclite
*emaclite
= dev_get_priv(dev
);
324 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
325 struct emaclite_regs
*regs
= emaclite
->regs
;
327 debug("EmacLite Initialization Started\n");
330 * TX - TX_PING & TX_PONG initialization
332 /* Restart PING TX */
333 __raw_writel(0, ®s
->tx_ping_tsr
);
334 /* Copy MAC address */
335 xemaclite_alignedwrite(pdata
->enetaddr
, ®s
->tx_ping
,
338 __raw_writel(ENET_ADDR_LENGTH
, ®s
->tx_ping_tplr
);
339 /* Update the MAC address in the EMAC Lite */
340 __raw_writel(XEL_TSR_PROG_MAC_ADDR
, ®s
->tx_ping_tsr
);
341 /* Wait for EMAC Lite to finish with the MAC address update */
342 while ((__raw_readl(®s
->tx_ping_tsr
) &
343 XEL_TSR_PROG_MAC_ADDR
) != 0)
346 if (emaclite
->txpp
) {
347 /* The same operation with PONG TX */
348 __raw_writel(0, ®s
->tx_pong_tsr
);
349 xemaclite_alignedwrite(pdata
->enetaddr
, ®s
->tx_pong
,
351 __raw_writel(ENET_ADDR_LENGTH
, ®s
->tx_pong_tplr
);
352 __raw_writel(XEL_TSR_PROG_MAC_ADDR
, ®s
->tx_pong_tsr
);
353 while ((__raw_readl(®s
->tx_pong_tsr
) &
354 XEL_TSR_PROG_MAC_ADDR
) != 0)
359 * RX - RX_PING & RX_PONG initialization
361 /* Write out the value to flush the RX buffer */
362 __raw_writel(XEL_RSR_RECV_IE_MASK
, ®s
->rx_ping_rsr
);
365 __raw_writel(XEL_RSR_RECV_IE_MASK
, ®s
->rx_pong_rsr
);
367 __raw_writel(XEL_MDIOCTRL_MDIOEN_MASK
, ®s
->mdioctrl
);
368 if (__raw_readl(®s
->mdioctrl
) & XEL_MDIOCTRL_MDIOEN_MASK
)
372 debug("EmacLite Initialization complete\n");
376 static int xemaclite_txbufferavailable(struct xemaclite
*emaclite
)
379 struct emaclite_regs
*regs
= emaclite
->regs
;
382 * Read the other buffer register
383 * and determine if the other buffer is available
385 tmp
= ~__raw_readl(®s
->tx_ping_tsr
);
387 tmp
|= ~__raw_readl(®s
->tx_pong_tsr
);
389 return !(tmp
& XEL_TSR_XMIT_BUSY_MASK
);
392 static int emaclite_send(struct udevice
*dev
, void *ptr
, int len
)
395 struct xemaclite
*emaclite
= dev_get_priv(dev
);
396 struct emaclite_regs
*regs
= emaclite
->regs
;
403 while (xemaclite_txbufferavailable(emaclite
) && maxtry
) {
409 printf("Error: Timeout waiting for ethernet TX buffer\n");
410 /* Restart PING TX */
411 __raw_writel(0, ®s
->tx_ping_tsr
);
412 if (emaclite
->txpp
) {
413 __raw_writel(0, ®s
->tx_pong_tsr
);
418 /* Determine if the expected buffer address is empty */
419 reg
= __raw_readl(®s
->tx_ping_tsr
);
420 if ((reg
& XEL_TSR_XMIT_BUSY_MASK
) == 0) {
421 debug("Send packet from tx_ping buffer\n");
422 /* Write the frame to the buffer */
423 xemaclite_alignedwrite(ptr
, ®s
->tx_ping
, len
);
425 & (XEL_TPLR_LENGTH_MASK_HI
| XEL_TPLR_LENGTH_MASK_LO
),
426 ®s
->tx_ping_tplr
);
427 reg
= __raw_readl(®s
->tx_ping_tsr
);
428 reg
|= XEL_TSR_XMIT_BUSY_MASK
;
429 __raw_writel(reg
, ®s
->tx_ping_tsr
);
433 if (emaclite
->txpp
) {
434 /* Determine if the expected buffer address is empty */
435 reg
= __raw_readl(®s
->tx_pong_tsr
);
436 if ((reg
& XEL_TSR_XMIT_BUSY_MASK
) == 0) {
437 debug("Send packet from tx_pong buffer\n");
438 /* Write the frame to the buffer */
439 xemaclite_alignedwrite(ptr
, ®s
->tx_pong
, len
);
441 (XEL_TPLR_LENGTH_MASK_HI
|
442 XEL_TPLR_LENGTH_MASK_LO
),
443 ®s
->tx_pong_tplr
);
444 reg
= __raw_readl(®s
->tx_pong_tsr
);
445 reg
|= XEL_TSR_XMIT_BUSY_MASK
;
446 __raw_writel(reg
, ®s
->tx_pong_tsr
);
451 puts("Error while sending frame\n");
455 static int emaclite_recv(struct udevice
*dev
, int flags
, uchar
**packetp
)
457 u32 length
, first_read
, reg
, attempt
= 0;
459 struct xemaclite
*emaclite
= dev
->priv
;
460 struct emaclite_regs
*regs
= emaclite
->regs
;
461 struct ethernet_hdr
*eth
;
462 struct ip_udp_hdr
*ip
;
465 if (!emaclite
->use_rx_pong_buffer_next
) {
466 reg
= __raw_readl(®s
->rx_ping_rsr
);
467 debug("Testing data at rx_ping\n");
468 if ((reg
& XEL_RSR_RECV_DONE_MASK
) == XEL_RSR_RECV_DONE_MASK
) {
469 debug("Data found in rx_ping buffer\n");
470 addr
= ®s
->rx_ping
;
471 ack
= ®s
->rx_ping_rsr
;
473 debug("Data not found in rx_ping buffer\n");
474 /* Pong buffer is not available - return immediately */
478 /* Try pong buffer if this is first attempt */
481 emaclite
->use_rx_pong_buffer_next
=
482 !emaclite
->use_rx_pong_buffer_next
;
486 reg
= __raw_readl(®s
->rx_pong_rsr
);
487 debug("Testing data at rx_pong\n");
488 if ((reg
& XEL_RSR_RECV_DONE_MASK
) == XEL_RSR_RECV_DONE_MASK
) {
489 debug("Data found in rx_pong buffer\n");
490 addr
= ®s
->rx_pong
;
491 ack
= ®s
->rx_pong_rsr
;
493 debug("Data not found in rx_pong buffer\n");
494 /* Try ping buffer if this is first attempt */
497 emaclite
->use_rx_pong_buffer_next
=
498 !emaclite
->use_rx_pong_buffer_next
;
503 /* Read all bytes for ARP packet with 32bit alignment - 48bytes */
504 first_read
= ALIGN(ETHER_HDR_SIZE
+ ARP_HDR_SIZE
+ ETH_FCS_LEN
, 4);
505 xemaclite_alignedread(addr
, etherrxbuff
, first_read
);
507 /* Detect real packet size */
508 eth
= (struct ethernet_hdr
*)etherrxbuff
;
509 switch (ntohs(eth
->et_protlen
)) {
512 debug("ARP Packet %x\n", length
);
515 ip
= (struct ip_udp_hdr
*)(etherrxbuff
+ ETHER_HDR_SIZE
);
516 length
= ntohs(ip
->ip_len
);
517 length
+= ETHER_HDR_SIZE
+ ETH_FCS_LEN
;
518 debug("IP Packet %x\n", length
);
521 debug("Other Packet\n");
526 /* Read the rest of the packet which is longer then first read */
527 if (length
!= first_read
)
528 xemaclite_alignedread(addr
+ first_read
,
529 etherrxbuff
+ first_read
,
530 length
- first_read
);
532 /* Acknowledge the frame */
533 reg
= __raw_readl(ack
);
534 reg
&= ~XEL_RSR_RECV_DONE_MASK
;
535 __raw_writel(reg
, ack
);
537 debug("Packet receive from 0x%p, length %dB\n", addr
, length
);
538 *packetp
= etherrxbuff
;
542 static int emaclite_miiphy_read(struct mii_dev
*bus
, int addr
,
548 ret
= phyread(bus
->priv
, addr
, reg
, &val
);
549 debug("emaclite: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr
, reg
, val
, ret
);
553 static int emaclite_miiphy_write(struct mii_dev
*bus
, int addr
, int devad
,
556 debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr
, reg
, value
);
557 return phywrite(bus
->priv
, addr
, reg
, value
);
560 static int emaclite_probe(struct udevice
*dev
)
562 struct xemaclite
*emaclite
= dev_get_priv(dev
);
565 emaclite
->bus
= mdio_alloc();
566 emaclite
->bus
->read
= emaclite_miiphy_read
;
567 emaclite
->bus
->write
= emaclite_miiphy_write
;
568 emaclite
->bus
->priv
= emaclite
;
570 ret
= mdio_register_seq(emaclite
->bus
, dev
->seq
);
577 static int emaclite_remove(struct udevice
*dev
)
579 struct xemaclite
*emaclite
= dev_get_priv(dev
);
581 free(emaclite
->phydev
);
582 mdio_unregister(emaclite
->bus
);
583 mdio_free(emaclite
->bus
);
588 static const struct eth_ops emaclite_ops
= {
589 .start
= emaclite_start
,
590 .send
= emaclite_send
,
591 .recv
= emaclite_recv
,
592 .stop
= emaclite_stop
,
595 static int emaclite_ofdata_to_platdata(struct udevice
*dev
)
597 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
598 struct xemaclite
*emaclite
= dev_get_priv(dev
);
601 pdata
->iobase
= (phys_addr_t
)devfdt_get_addr(dev
);
602 emaclite
->regs
= (struct emaclite_regs
*)ioremap_nocache(pdata
->iobase
,
605 emaclite
->phyaddr
= -1;
607 offset
= fdtdec_lookup_phandle(gd
->fdt_blob
, dev_of_offset(dev
),
610 emaclite
->phyaddr
= fdtdec_get_int(gd
->fdt_blob
, offset
,
613 emaclite
->txpp
= fdtdec_get_int(gd
->fdt_blob
, dev_of_offset(dev
),
614 "xlnx,tx-ping-pong", 0);
615 emaclite
->rxpp
= fdtdec_get_int(gd
->fdt_blob
, dev_of_offset(dev
),
616 "xlnx,rx-ping-pong", 0);
618 printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong
)emaclite
->regs
,
619 emaclite
->phyaddr
, emaclite
->txpp
, emaclite
->rxpp
);
624 static const struct udevice_id emaclite_ids
[] = {
625 { .compatible
= "xlnx,xps-ethernetlite-1.00.a" },
629 U_BOOT_DRIVER(emaclite
) = {
632 .of_match
= emaclite_ids
,
633 .ofdata_to_platdata
= emaclite_ofdata_to_platdata
,
634 .probe
= emaclite_probe
,
635 .remove
= emaclite_remove
,
636 .ops
= &emaclite_ops
,
637 .priv_auto_alloc_size
= sizeof(struct xemaclite
),
638 .platdata_auto_alloc_size
= sizeof(struct eth_pdata
),