drivers/net/xilinx_ll_temac_fifo.h

   1 /*
   2  * Xilinx xps_ll_temac ethernet driver for u-boot
   3  *
   4  * FIFO sub-controller interface
   5  *
   6  * Copyright (C) 2011 - 2012 Stephan Linz <linz@li-pro.net>
   7  * Copyright (C) 2008 - 2011 Michal Simek <monstr@monstr.eu>
   8  * Copyright (C) 2008 - 2011 PetaLogix
   9  *
  10  * Based on Yoshio Kashiwagi kashiwagi@co-nss.co.jp driver
  11  * Copyright (C) 2008 Nissin Systems Co.,Ltd.
  12  * March 2008 created
  13  *
  14  * This program is free software; you can redistribute it and/or modify it
  15  * under the terms of the GNU General Public License as published by the
  16  * Free Software Foundation; either version 2 of the License, or (at your
  17  * option) any later version.
  18  *
  19  * [0]: http://www.xilinx.com/support/documentation
  20  *
  21  * [S]: [0]/ip_documentation/xps_ll_temac.pdf
  22  * [A]: [0]/application_notes/xapp1041.pdf
  23  */
  24 #ifndef _XILINX_LL_TEMAC_FIFO_
  25 #define _XILINX_LL_TEMAC_FIFO_
  26
  27 #include <net.h>
  28
  29 #include <asm/types.h>
  30 #include <asm/byteorder.h>
  31
  32 #if !defined(__BIG_ENDIAN)
  33 # error LL_TEMAC requires big endianess
  34 #endif
  35
  36 /*
  37  * FIFO Register Definition
  38  *
  39  * Used for memory mapped access from and to (Rd/Td) the LocalLink (LL)
  40  * Tri-Mode Ether MAC (TEMAC) via the 2 kb full duplex FIFO Controller,
  41  * one for each.
  42  *
  43  * [1]: [0]/ip_documentation/xps_ll_fifo.pdf
  44  *      page 10, Registers Definition
  45  */
  46 struct fifo_ctrl {
  47         u32 isr;        /* Interrupt Status Register (RW) */
  48         u32 ier;        /* Interrupt Enable Register (RW) */
  49         u32 tdfr;       /* Transmit Data FIFO Reset (WO) */
  50         u32 tdfv;       /* Transmit Data FIFO Vacancy (RO) */
  51         u32 tdfd;       /* Transmit Data FIFO 32bit wide Data write port (WO) */
  52         u32 tlf;        /* Transmit Length FIFO (WO) */
  53         u32 rdfr;       /* Receive Data FIFO Reset (WO) */
  54         u32 rdfo;       /* Receive Data FIFO Occupancy (RO) */
  55         u32 rdfd;       /* Receive Data FIFO 32bit wide Data read port (RO) */
  56         u32 rlf;        /* Receive Length FIFO (RO) */
  57         u32 llr;        /* LocalLink Reset (WO) */
  58 };
  59
  60 /* Interrupt Status Register (ISR), [1] p11 */
  61 #define LL_FIFO_ISR_RPURE       (1 << 31) /* Receive Packet Underrun Read Err */
  62 #define LL_FIFO_ISR_RPORE       (1 << 30) /* Receive Packet Overrun Read Err */
  63 #define LL_FIFO_ISR_RPUE        (1 << 29) /* Receive Packet Underrun Error */
  64 #define LL_FIFO_ISR_TPOE        (1 << 28) /* Transmit Packet Overrun Error */
  65 #define LL_FIFO_ISR_TC          (1 << 27) /* Transmit Complete */
  66 #define LL_FIFO_ISR_RC          (1 << 26) /* Receive Complete */
  67 #define LL_FIFO_ISR_TSE         (1 << 25) /* Transmit Size Error */
  68 #define LL_FIFO_ISR_TRC         (1 << 24) /* Transmit Reset Complete */
  69 #define LL_FIFO_ISR_RRC         (1 << 23) /* Receive Reset Complete */
  70
  71 /* Interrupt Enable Register (IER), [1] p12/p13 */
  72 #define LL_FIFO_IER_RPURE       (1 << 31) /* Receive Packet Underrun Read Err */
  73 #define LL_FIFO_IER_RPORE       (1 << 30) /* Receive Packet Overrun Read Err */
  74 #define LL_FIFO_IER_RPUE        (1 << 29) /* Receive Packet Underrun Error */
  75 #define LL_FIFO_IER_TPOE        (1 << 28) /* Transmit Packet Overrun Error */
  76 #define LL_FIFO_IER_TC          (1 << 27) /* Transmit Complete */
  77 #define LL_FIFO_IER_RC          (1 << 26) /* Receive Complete */
  78 #define LL_FIFO_IER_TSE         (1 << 25) /* Transmit Size Error */
  79 #define LL_FIFO_IER_TRC         (1 << 24) /* Transmit Reset Complete */
  80 #define LL_FIFO_IER_RRC         (1 << 23) /* Receive Reset Complete */
  81
  82 /* Transmit Data FIFO Reset (TDFR), [1] p13/p14 */
  83 #define LL_FIFO_TDFR_KEY        0x000000A5UL
  84
  85 /* Transmit Data FIFO Vacancy (TDFV), [1] p14 */
  86 #define LL_FIFO_TDFV_POS        0
  87 #define LL_FIFO_TDFV_MASK       (0x000001FFUL << LL_FIFO_TDFV_POS)
  88
  89 /* Transmit Length FIFO (TLF), [1] p16/p17 */
  90 #define LL_FIFO_TLF_POS         0
  91 #define LL_FIFO_TLF_MASK        (0x000007FFUL << LL_FIFO_TLF_POS)
  92 #define LL_FIFO_TLF_MIN         ((4 * sizeof(u32)) & LL_FIFO_TLF_MASK)
  93 #define LL_FIFO_TLF_MAX         ((510 * sizeof(u32)) & LL_FIFO_TLF_MASK)
  94
  95 /* Receive Data FIFO Reset (RDFR), [1] p15 */
  96 #define LL_FIFO_RDFR_KEY        0x000000A5UL
  97
  98 /* Receive Data FIFO Occupancy (RDFO), [1] p16 */
  99 #define LL_FIFO_RDFO_POS        0
 100 #define LL_FIFO_RDFO_MASK       (0x000001FFUL << LL_FIFO_RDFO_POS)
 101
 102 /* Receive Length FIFO (RLF), [1] p17/p18 */
 103 #define LL_FIFO_RLF_POS         0
 104 #define LL_FIFO_RLF_MASK        (0x000007FFUL << LL_FIFO_RLF_POS)
 105 #define LL_FIFO_RLF_MIN         ((4 * sizeof(uint32)) & LL_FIFO_RLF_MASK)
 106 #define LL_FIFO_RLF_MAX         ((510 * sizeof(uint32)) & LL_FIFO_RLF_MASK)
 107
 108 /* LocalLink Reset (LLR), [1] p18 */
 109 #define LL_FIFO_LLR_KEY         0x000000A5UL
 110
 111
 112 /* reset FIFO and IRQ, disable interrupts */
 113 int ll_temac_reset_fifo(struct eth_device *dev);
 114
 115 /* receive buffered data from FIFO (polling ISR) */
 116 int ll_temac_recv_fifo(struct eth_device *dev);
 117
 118 /* send buffered data to FIFO */
 119 int ll_temac_send_fifo(struct eth_device *dev, void *packet, int length);
 120
 121 #endif /* _XILINX_LL_TEMAC_FIFO_ */