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[thirdparty/u-boot.git] / drivers / net / zynq_gem.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2011 Michal Simek
4 *
5 * Michal SIMEK <monstr@monstr.eu>
6 *
7 * Based on Xilinx gmac driver:
8 * (C) Copyright 2011 Xilinx
9 */
10
11 #include <clk.h>
12 #include <common.h>
13 #include <cpu_func.h>
14 #include <dm.h>
15 #include <net.h>
16 #include <netdev.h>
17 #include <config.h>
18 #include <console.h>
19 #include <malloc.h>
20 #include <asm/cache.h>
21 #include <asm/io.h>
22 #include <phy.h>
23 #include <miiphy.h>
24 #include <wait_bit.h>
25 #include <watchdog.h>
26 #include <asm/system.h>
27 #include <asm/arch/hardware.h>
28 #include <asm/arch/sys_proto.h>
29 #include <dm/device_compat.h>
30 #include <linux/err.h>
31 #include <linux/errno.h>
32
33 /* Bit/mask specification */
34 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
35 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
36 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
37 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
38 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
39
40 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
41 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
42 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
43
44 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
45 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
46 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
47
48 /* Wrap bit, last descriptor */
49 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
50 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
51 #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */
52
53 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
54 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
55 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
56 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
57
58 #define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */
59 #define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */
60 #define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */
61 #define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */
62 #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */
63 #define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */
64 #ifdef CONFIG_ARM64
65 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */
66 #else
67 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */
68 #endif
69
70 #ifdef CONFIG_ARM64
71 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
72 #else
73 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
74 #endif
75
76 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
77 ZYNQ_GEM_NWCFG_FDEN | \
78 ZYNQ_GEM_NWCFG_FSREM | \
79 ZYNQ_GEM_NWCFG_MDCCLKDIV)
80
81 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
82
83 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
84 /* Use full configured addressable space (8 Kb) */
85 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
86 /* Use full configured addressable space (4 Kb) */
87 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
88 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
89 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000
90
91 #if defined(CONFIG_PHYS_64BIT)
92 # define ZYNQ_GEM_DMA_BUS_WIDTH BIT(30) /* 64 bit bus */
93 #else
94 # define ZYNQ_GEM_DMA_BUS_WIDTH (0 << 30) /* 32 bit bus */
95 #endif
96
97 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
98 ZYNQ_GEM_DMACR_RXSIZE | \
99 ZYNQ_GEM_DMACR_TXSIZE | \
100 ZYNQ_GEM_DMACR_RXBUF | \
101 ZYNQ_GEM_DMA_BUS_WIDTH)
102
103 #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */
104
105 #define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000
106
107 #define ZYNQ_GEM_DCFG_DBG6_DMA_64B BIT(23)
108
109 /* Use MII register 1 (MII status register) to detect PHY */
110 #define PHY_DETECT_REG 1
111
112 /* Mask used to verify certain PHY features (or register contents)
113 * in the register above:
114 * 0x1000: 10Mbps full duplex support
115 * 0x0800: 10Mbps half duplex support
116 * 0x0008: Auto-negotiation support
117 */
118 #define PHY_DETECT_MASK 0x1808
119
120 /* TX BD status masks */
121 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
122 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
123 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
124
125 /* Clock frequencies for different speeds */
126 #define ZYNQ_GEM_FREQUENCY_10 2500000UL
127 #define ZYNQ_GEM_FREQUENCY_100 25000000UL
128 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL
129
130 /* Device registers */
131 struct zynq_gem_regs {
132 u32 nwctrl; /* 0x0 - Network Control reg */
133 u32 nwcfg; /* 0x4 - Network Config reg */
134 u32 nwsr; /* 0x8 - Network Status reg */
135 u32 reserved1;
136 u32 dmacr; /* 0x10 - DMA Control reg */
137 u32 txsr; /* 0x14 - TX Status reg */
138 u32 rxqbase; /* 0x18 - RX Q Base address reg */
139 u32 txqbase; /* 0x1c - TX Q Base address reg */
140 u32 rxsr; /* 0x20 - RX Status reg */
141 u32 reserved2[2];
142 u32 idr; /* 0x2c - Interrupt Disable reg */
143 u32 reserved3;
144 u32 phymntnc; /* 0x34 - Phy Maintaince reg */
145 u32 reserved4[18];
146 u32 hashl; /* 0x80 - Hash Low address reg */
147 u32 hashh; /* 0x84 - Hash High address reg */
148 #define LADDR_LOW 0
149 #define LADDR_HIGH 1
150 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
151 u32 match[4]; /* 0xa8 - Type ID1 Match reg */
152 u32 reserved6[18];
153 #define STAT_SIZE 44
154 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
155 u32 reserved9[20];
156 u32 pcscntrl;
157 u32 rserved12[36];
158 u32 dcfg6; /* 0x294 Design config reg6 */
159 u32 reserved7[106];
160 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
161 u32 reserved8[15];
162 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
163 u32 reserved10[17];
164 u32 upper_txqbase; /* 0x4C8 - Upper tx_q base addr */
165 u32 reserved11[2];
166 u32 upper_rxqbase; /* 0x4D4 - Upper rx_q base addr */
167 };
168
169 /* BD descriptors */
170 struct emac_bd {
171 u32 addr; /* Next descriptor pointer */
172 u32 status;
173 #if defined(CONFIG_PHYS_64BIT)
174 u32 addr_hi;
175 u32 reserved;
176 #endif
177 };
178
179 /* Reduce amount of BUFs if you have limited amount of memory */
180 #define RX_BUF 32
181 /* Page table entries are set to 1MB, or multiples of 1MB
182 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
183 */
184 #define BD_SPACE 0x100000
185 /* BD separation space */
186 #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd))
187
188 /* Setup the first free TX descriptor */
189 #define TX_FREE_DESC 2
190
191 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
192 struct zynq_gem_priv {
193 struct emac_bd *tx_bd;
194 struct emac_bd *rx_bd;
195 char *rxbuffers;
196 u32 rxbd_current;
197 u32 rx_first_buf;
198 int phyaddr;
199 int init;
200 struct zynq_gem_regs *iobase;
201 struct zynq_gem_regs *mdiobase;
202 phy_interface_t interface;
203 struct phy_device *phydev;
204 ofnode phy_of_node;
205 struct mii_dev *bus;
206 struct clk clk;
207 u32 max_speed;
208 bool int_pcs;
209 bool dma_64bit;
210 };
211
212 static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
213 u32 op, u16 *data)
214 {
215 u32 mgtcr;
216 struct zynq_gem_regs *regs = priv->mdiobase;
217 int err;
218
219 err = wait_for_bit_le32(&regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
220 true, 20000, false);
221 if (err)
222 return err;
223
224 /* Construct mgtcr mask for the operation */
225 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
226 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
227 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
228
229 /* Write mgtcr and wait for completion */
230 writel(mgtcr, &regs->phymntnc);
231
232 err = wait_for_bit_le32(&regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
233 true, 20000, false);
234 if (err)
235 return err;
236
237 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
238 *data = readl(&regs->phymntnc);
239
240 return 0;
241 }
242
243 static int phyread(struct zynq_gem_priv *priv, u32 phy_addr,
244 u32 regnum, u16 *val)
245 {
246 int ret;
247
248 ret = phy_setup_op(priv, phy_addr, regnum,
249 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
250
251 if (!ret)
252 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
253 phy_addr, regnum, *val);
254
255 return ret;
256 }
257
258 static int phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
259 u32 regnum, u16 data)
260 {
261 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
262 regnum, data);
263
264 return phy_setup_op(priv, phy_addr, regnum,
265 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
266 }
267
268 static int zynq_gem_setup_mac(struct udevice *dev)
269 {
270 u32 i, macaddrlow, macaddrhigh;
271 struct eth_pdata *pdata = dev_get_platdata(dev);
272 struct zynq_gem_priv *priv = dev_get_priv(dev);
273 struct zynq_gem_regs *regs = priv->iobase;
274
275 /* Set the MAC bits [31:0] in BOT */
276 macaddrlow = pdata->enetaddr[0];
277 macaddrlow |= pdata->enetaddr[1] << 8;
278 macaddrlow |= pdata->enetaddr[2] << 16;
279 macaddrlow |= pdata->enetaddr[3] << 24;
280
281 /* Set MAC bits [47:32] in TOP */
282 macaddrhigh = pdata->enetaddr[4];
283 macaddrhigh |= pdata->enetaddr[5] << 8;
284
285 for (i = 0; i < 4; i++) {
286 writel(0, &regs->laddr[i][LADDR_LOW]);
287 writel(0, &regs->laddr[i][LADDR_HIGH]);
288 /* Do not use MATCHx register */
289 writel(0, &regs->match[i]);
290 }
291
292 writel(macaddrlow, &regs->laddr[0][LADDR_LOW]);
293 writel(macaddrhigh, &regs->laddr[0][LADDR_HIGH]);
294
295 return 0;
296 }
297
298 static int zynq_phy_init(struct udevice *dev)
299 {
300 int ret;
301 struct zynq_gem_priv *priv = dev_get_priv(dev);
302 struct zynq_gem_regs *regs_mdio = priv->mdiobase;
303 const u32 supported = SUPPORTED_10baseT_Half |
304 SUPPORTED_10baseT_Full |
305 SUPPORTED_100baseT_Half |
306 SUPPORTED_100baseT_Full |
307 SUPPORTED_1000baseT_Half |
308 SUPPORTED_1000baseT_Full;
309
310 /* Enable only MDIO bus */
311 writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, &regs_mdio->nwctrl);
312
313 priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
314 priv->interface);
315 if (!priv->phydev)
316 return -ENODEV;
317
318 if (priv->max_speed) {
319 ret = phy_set_supported(priv->phydev, priv->max_speed);
320 if (ret)
321 return ret;
322 }
323
324 priv->phydev->supported &= supported | ADVERTISED_Pause |
325 ADVERTISED_Asym_Pause;
326
327 priv->phydev->advertising = priv->phydev->supported;
328 priv->phydev->node = priv->phy_of_node;
329
330 return phy_config(priv->phydev);
331 }
332
333 static int zynq_gem_init(struct udevice *dev)
334 {
335 u32 i, nwconfig;
336 int ret;
337 unsigned long clk_rate = 0;
338 struct zynq_gem_priv *priv = dev_get_priv(dev);
339 struct zynq_gem_regs *regs = priv->iobase;
340 struct zynq_gem_regs *regs_mdio = priv->mdiobase;
341 struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
342 struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
343
344 if (readl(&regs->dcfg6) & ZYNQ_GEM_DCFG_DBG6_DMA_64B)
345 priv->dma_64bit = true;
346 else
347 priv->dma_64bit = false;
348
349 #if defined(CONFIG_PHYS_64BIT)
350 if (!priv->dma_64bit) {
351 printf("ERR: %s: Using 64-bit DMA but HW doesn't support it\n",
352 __func__);
353 return -EINVAL;
354 }
355 #else
356 if (priv->dma_64bit)
357 debug("WARN: %s: Not using 64-bit dma even HW supports it\n",
358 __func__);
359 #endif
360
361 if (!priv->init) {
362 /* Disable all interrupts */
363 writel(0xFFFFFFFF, &regs->idr);
364
365 /* Disable the receiver & transmitter */
366 writel(0, &regs->nwctrl);
367 writel(0, &regs->txsr);
368 writel(0, &regs->rxsr);
369 writel(0, &regs->phymntnc);
370
371 /* Clear the Hash registers for the mac address
372 * pointed by AddressPtr
373 */
374 writel(0x0, &regs->hashl);
375 /* Write bits [63:32] in TOP */
376 writel(0x0, &regs->hashh);
377
378 /* Clear all counters */
379 for (i = 0; i < STAT_SIZE; i++)
380 readl(&regs->stat[i]);
381
382 /* Setup RxBD space */
383 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
384
385 for (i = 0; i < RX_BUF; i++) {
386 priv->rx_bd[i].status = 0xF0000000;
387 priv->rx_bd[i].addr =
388 (lower_32_bits((ulong)(priv->rxbuffers)
389 + (i * PKTSIZE_ALIGN)));
390 #if defined(CONFIG_PHYS_64BIT)
391 priv->rx_bd[i].addr_hi =
392 (upper_32_bits((ulong)(priv->rxbuffers)
393 + (i * PKTSIZE_ALIGN)));
394 #endif
395 }
396 /* WRAP bit to last BD */
397 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
398 /* Write RxBDs to IP */
399 writel(lower_32_bits((ulong)priv->rx_bd), &regs->rxqbase);
400 #if defined(CONFIG_PHYS_64BIT)
401 writel(upper_32_bits((ulong)priv->rx_bd), &regs->upper_rxqbase);
402 #endif
403
404 /* Setup for DMA Configuration register */
405 writel(ZYNQ_GEM_DMACR_INIT, &regs->dmacr);
406
407 /* Setup for Network Control register, MDIO, Rx and Tx enable */
408 setbits_le32(&regs_mdio->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
409
410 /* Disable the second priority queue */
411 dummy_tx_bd->addr = 0;
412 #if defined(CONFIG_PHYS_64BIT)
413 dummy_tx_bd->addr_hi = 0;
414 #endif
415 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
416 ZYNQ_GEM_TXBUF_LAST_MASK|
417 ZYNQ_GEM_TXBUF_USED_MASK;
418
419 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
420 ZYNQ_GEM_RXBUF_NEW_MASK;
421 #if defined(CONFIG_PHYS_64BIT)
422 dummy_rx_bd->addr_hi = 0;
423 #endif
424 dummy_rx_bd->status = 0;
425
426 writel((ulong)dummy_tx_bd, &regs->transmit_q1_ptr);
427 writel((ulong)dummy_rx_bd, &regs->receive_q1_ptr);
428
429 priv->init++;
430 }
431
432 ret = phy_startup(priv->phydev);
433 if (ret)
434 return ret;
435
436 if (!priv->phydev->link) {
437 printf("%s: No link.\n", priv->phydev->dev->name);
438 return -1;
439 }
440
441 nwconfig = ZYNQ_GEM_NWCFG_INIT;
442
443 /*
444 * Set SGMII enable PCS selection only if internal PCS/PMA
445 * core is used and interface is SGMII.
446 */
447 if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
448 priv->int_pcs) {
449 nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
450 ZYNQ_GEM_NWCFG_PCS_SEL;
451 #ifdef CONFIG_ARM64
452 writel(readl(&regs->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
453 &regs->pcscntrl);
454 #endif
455 }
456
457 switch (priv->phydev->speed) {
458 case SPEED_1000:
459 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000,
460 &regs->nwcfg);
461 clk_rate = ZYNQ_GEM_FREQUENCY_1000;
462 break;
463 case SPEED_100:
464 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100,
465 &regs->nwcfg);
466 clk_rate = ZYNQ_GEM_FREQUENCY_100;
467 break;
468 case SPEED_10:
469 clk_rate = ZYNQ_GEM_FREQUENCY_10;
470 break;
471 }
472
473 ret = clk_set_rate(&priv->clk, clk_rate);
474 if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
475 dev_err(dev, "failed to set tx clock rate\n");
476 return ret;
477 }
478
479 ret = clk_enable(&priv->clk);
480 if (ret && ret != -ENOSYS) {
481 dev_err(dev, "failed to enable tx clock\n");
482 return ret;
483 }
484
485 setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
486 ZYNQ_GEM_NWCTRL_TXEN_MASK);
487
488 return 0;
489 }
490
491 static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
492 {
493 dma_addr_t addr;
494 u32 size;
495 struct zynq_gem_priv *priv = dev_get_priv(dev);
496 struct zynq_gem_regs *regs = priv->iobase;
497 struct emac_bd *current_bd = &priv->tx_bd[1];
498
499 /* Setup Tx BD */
500 memset(priv->tx_bd, 0, sizeof(struct emac_bd));
501
502 priv->tx_bd->addr = lower_32_bits((ulong)ptr);
503 #if defined(CONFIG_PHYS_64BIT)
504 priv->tx_bd->addr_hi = upper_32_bits((ulong)ptr);
505 #endif
506 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
507 ZYNQ_GEM_TXBUF_LAST_MASK;
508 /* Dummy descriptor to mark it as the last in descriptor chain */
509 current_bd->addr = 0x0;
510 #if defined(CONFIG_PHYS_64BIT)
511 current_bd->addr_hi = 0x0;
512 #endif
513 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
514 ZYNQ_GEM_TXBUF_LAST_MASK|
515 ZYNQ_GEM_TXBUF_USED_MASK;
516
517 /* setup BD */
518 writel(lower_32_bits((ulong)priv->tx_bd), &regs->txqbase);
519 #if defined(CONFIG_PHYS_64BIT)
520 writel(upper_32_bits((ulong)priv->tx_bd), &regs->upper_txqbase);
521 #endif
522
523 addr = (ulong) ptr;
524 addr &= ~(ARCH_DMA_MINALIGN - 1);
525 size = roundup(len, ARCH_DMA_MINALIGN);
526 flush_dcache_range(addr, addr + size);
527 barrier();
528
529 /* Start transmit */
530 setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
531
532 /* Read TX BD status */
533 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
534 printf("TX buffers exhausted in mid frame\n");
535
536 return wait_for_bit_le32(&regs->txsr, ZYNQ_GEM_TSR_DONE,
537 true, 20000, true);
538 }
539
540 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
541 static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
542 {
543 int frame_len;
544 dma_addr_t addr;
545 struct zynq_gem_priv *priv = dev_get_priv(dev);
546 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
547
548 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
549 return -1;
550
551 if (!(current_bd->status &
552 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
553 printf("GEM: SOF or EOF not set for last buffer received!\n");
554 return -1;
555 }
556
557 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
558 if (!frame_len) {
559 printf("%s: Zero size packet?\n", __func__);
560 return -1;
561 }
562
563 #if defined(CONFIG_PHYS_64BIT)
564 addr = (dma_addr_t)((current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK)
565 | ((dma_addr_t)current_bd->addr_hi << 32));
566 #else
567 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
568 #endif
569 addr &= ~(ARCH_DMA_MINALIGN - 1);
570
571 *packetp = (uchar *)(uintptr_t)addr;
572
573 invalidate_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
574 barrier();
575
576 return frame_len;
577 }
578
579 static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length)
580 {
581 struct zynq_gem_priv *priv = dev_get_priv(dev);
582 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
583 struct emac_bd *first_bd;
584 dma_addr_t addr;
585
586 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) {
587 priv->rx_first_buf = priv->rxbd_current;
588 } else {
589 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
590 current_bd->status = 0xF0000000; /* FIXME */
591 }
592
593 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
594 first_bd = &priv->rx_bd[priv->rx_first_buf];
595 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
596 first_bd->status = 0xF0000000;
597 }
598
599 /* Flush the cache for the packet as well */
600 #if defined(CONFIG_PHYS_64BIT)
601 addr = (dma_addr_t)((current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK)
602 | ((dma_addr_t)current_bd->addr_hi << 32));
603 #else
604 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
605 #endif
606 flush_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN,
607 ARCH_DMA_MINALIGN));
608 barrier();
609
610 if ((++priv->rxbd_current) >= RX_BUF)
611 priv->rxbd_current = 0;
612
613 return 0;
614 }
615
616 static void zynq_gem_halt(struct udevice *dev)
617 {
618 struct zynq_gem_priv *priv = dev_get_priv(dev);
619 struct zynq_gem_regs *regs = priv->iobase;
620
621 clrsetbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
622 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
623 }
624
625 __weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
626 {
627 return -ENOSYS;
628 }
629
630 static int zynq_gem_read_rom_mac(struct udevice *dev)
631 {
632 struct eth_pdata *pdata = dev_get_platdata(dev);
633
634 if (!pdata)
635 return -ENOSYS;
636
637 return zynq_board_read_rom_ethaddr(pdata->enetaddr);
638 }
639
640 static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr,
641 int devad, int reg)
642 {
643 struct zynq_gem_priv *priv = bus->priv;
644 int ret;
645 u16 val = 0;
646
647 ret = phyread(priv, addr, reg, &val);
648 debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret);
649 return val;
650 }
651
652 static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad,
653 int reg, u16 value)
654 {
655 struct zynq_gem_priv *priv = bus->priv;
656
657 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value);
658 return phywrite(priv, addr, reg, value);
659 }
660
661 static int zynq_gem_probe(struct udevice *dev)
662 {
663 void *bd_space;
664 struct zynq_gem_priv *priv = dev_get_priv(dev);
665 int ret;
666
667 /* Align rxbuffers to ARCH_DMA_MINALIGN */
668 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
669 if (!priv->rxbuffers)
670 return -ENOMEM;
671
672 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
673 ulong addr = (ulong)priv->rxbuffers;
674 flush_dcache_range(addr, addr + roundup(RX_BUF * PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
675 barrier();
676
677 /* Align bd_space to MMU_SECTION_SHIFT */
678 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
679 if (!bd_space) {
680 ret = -ENOMEM;
681 goto err1;
682 }
683
684 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
685 BD_SPACE, DCACHE_OFF);
686
687 /* Initialize the bd spaces for tx and rx bd's */
688 priv->tx_bd = (struct emac_bd *)bd_space;
689 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
690
691 ret = clk_get_by_name(dev, "tx_clk", &priv->clk);
692 if (ret < 0) {
693 dev_err(dev, "failed to get clock\n");
694 goto err1;
695 }
696
697 priv->bus = mdio_alloc();
698 priv->bus->read = zynq_gem_miiphy_read;
699 priv->bus->write = zynq_gem_miiphy_write;
700 priv->bus->priv = priv;
701
702 ret = mdio_register_seq(priv->bus, dev->seq);
703 if (ret)
704 goto err2;
705
706 ret = zynq_phy_init(dev);
707 if (ret)
708 goto err2;
709
710 return ret;
711
712 err2:
713 free(priv->rxbuffers);
714 err1:
715 free(priv->tx_bd);
716 return ret;
717 }
718
719 static int zynq_gem_remove(struct udevice *dev)
720 {
721 struct zynq_gem_priv *priv = dev_get_priv(dev);
722
723 free(priv->phydev);
724 mdio_unregister(priv->bus);
725 mdio_free(priv->bus);
726
727 return 0;
728 }
729
730 static const struct eth_ops zynq_gem_ops = {
731 .start = zynq_gem_init,
732 .send = zynq_gem_send,
733 .recv = zynq_gem_recv,
734 .free_pkt = zynq_gem_free_pkt,
735 .stop = zynq_gem_halt,
736 .write_hwaddr = zynq_gem_setup_mac,
737 .read_rom_hwaddr = zynq_gem_read_rom_mac,
738 };
739
740 static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
741 {
742 struct eth_pdata *pdata = dev_get_platdata(dev);
743 struct zynq_gem_priv *priv = dev_get_priv(dev);
744 struct ofnode_phandle_args phandle_args;
745 const char *phy_mode;
746
747 pdata->iobase = (phys_addr_t)dev_read_addr(dev);
748 priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
749 priv->mdiobase = priv->iobase;
750 /* Hardcode for now */
751 priv->phyaddr = -1;
752
753 if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
754 &phandle_args)) {
755 debug("phy-handle does exist %s\n", dev->name);
756 priv->phyaddr = ofnode_read_u32_default(phandle_args.node,
757 "reg", -1);
758 priv->phy_of_node = phandle_args.node;
759 priv->max_speed = ofnode_read_u32_default(phandle_args.node,
760 "max-speed",
761 SPEED_1000);
762 }
763
764 phy_mode = dev_read_prop(dev, "phy-mode", NULL);
765 if (phy_mode)
766 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
767 if (pdata->phy_interface == -1) {
768 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
769 return -EINVAL;
770 }
771 priv->interface = pdata->phy_interface;
772
773 priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma");
774
775 printf("\nZYNQ GEM: %lx, mdio bus %lx, phyaddr %d, interface %s\n",
776 (ulong)priv->iobase, (ulong)priv->mdiobase, priv->phyaddr,
777 phy_string_for_interface(priv->interface));
778
779 return 0;
780 }
781
782 static const struct udevice_id zynq_gem_ids[] = {
783 { .compatible = "cdns,versal-gem" },
784 { .compatible = "cdns,zynqmp-gem" },
785 { .compatible = "cdns,zynq-gem" },
786 { .compatible = "cdns,gem" },
787 { }
788 };
789
790 U_BOOT_DRIVER(zynq_gem) = {
791 .name = "zynq_gem",
792 .id = UCLASS_ETH,
793 .of_match = zynq_gem_ids,
794 .ofdata_to_platdata = zynq_gem_ofdata_to_platdata,
795 .probe = zynq_gem_probe,
796 .remove = zynq_gem_remove,
797 .ops = &zynq_gem_ops,
798 .priv_auto_alloc_size = sizeof(struct zynq_gem_priv),
799 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
800 };
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