2 * (C) Copyright 2011 Michal Simek
4 * Michal SIMEK <monstr@monstr.eu>
6 * Based on Xilinx gmac driver:
7 * (C) Copyright 2011 Xilinx
9 * SPDX-License-Identifier: GPL-2.0+
20 #include <asm/arch/hardware.h>
21 #include <asm/arch/sys_proto.h>
23 #if !defined(CONFIG_PHYLIB)
24 # error XILINX_GEM_ETHERNET requires PHYLIB
27 /* Bit/mask specification */
28 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
29 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
30 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
31 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
32 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
34 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
35 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
36 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
38 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
39 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
40 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
42 /* Wrap bit, last descriptor */
43 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
44 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
46 #define ZYNQ_GEM_TXSR_HRESPNOK_MASK 0x00000100 /* Transmit hresp not OK */
47 #define ZYNQ_GEM_TXSR_URUN_MASK 0x00000040 /* Transmit underrun */
48 /* Transmit buffs exhausted mid frame */
49 #define ZYNQ_GEM_TXSR_BUFEXH_MASK 0x00000010
51 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
52 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
53 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
54 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
56 #define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */
57 #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */
58 #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */
59 #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */
60 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */
61 #define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */
63 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_NWCFG_FDEN | \
64 ZYNQ_GEM_NWCFG_FSREM | \
65 ZYNQ_GEM_NWCFG_MDCCLKDIV)
67 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
69 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
70 /* Use full configured addressable space (8 Kb) */
71 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
72 /* Use full configured addressable space (4 Kb) */
73 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
74 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
75 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000
77 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
78 ZYNQ_GEM_DMACR_RXSIZE | \
79 ZYNQ_GEM_DMACR_TXSIZE | \
82 /* Use MII register 1 (MII status register) to detect PHY */
83 #define PHY_DETECT_REG 1
85 /* Mask used to verify certain PHY features (or register contents)
86 * in the register above:
87 * 0x1000: 10Mbps full duplex support
88 * 0x0800: 10Mbps half duplex support
89 * 0x0008: Auto-negotiation support
91 #define PHY_DETECT_MASK 0x1808
93 /* Device registers */
94 struct zynq_gem_regs
{
95 u32 nwctrl
; /* Network Control reg */
96 u32 nwcfg
; /* Network Config reg */
97 u32 nwsr
; /* Network Status reg */
99 u32 dmacr
; /* DMA Control reg */
100 u32 txsr
; /* TX Status reg */
101 u32 rxqbase
; /* RX Q Base address reg */
102 u32 txqbase
; /* TX Q Base address reg */
103 u32 rxsr
; /* RX Status reg */
105 u32 idr
; /* Interrupt Disable reg */
107 u32 phymntnc
; /* Phy Maintaince reg */
109 u32 hashl
; /* Hash Low address reg */
110 u32 hashh
; /* Hash High address reg */
113 u32 laddr
[4][LADDR_HIGH
+ 1]; /* Specific1 addr low/high reg */
114 u32 match
[4]; /* Type ID1 Match reg */
116 u32 stat
[44]; /* Octects transmitted Low reg - stat start */
121 u32 addr
; /* Next descriptor pointer */
127 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
128 struct zynq_gem_priv
{
129 struct emac_bd tx_bd
;
130 struct emac_bd rx_bd
[RX_BUF
];
131 char rxbuffers
[RX_BUF
* PKTSIZE_ALIGN
];
137 struct phy_device
*phydev
;
141 static inline int mdio_wait(struct eth_device
*dev
)
143 struct zynq_gem_regs
*regs
= (struct zynq_gem_regs
*)dev
->iobase
;
146 /* Wait till MDIO interface is ready to accept a new transaction. */
148 if (readl(®s
->nwsr
) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK
)
154 printf("%s: Timeout\n", __func__
);
161 static u32
phy_setup_op(struct eth_device
*dev
, u32 phy_addr
, u32 regnum
,
165 struct zynq_gem_regs
*regs
= (struct zynq_gem_regs
*)dev
->iobase
;
170 /* Construct mgtcr mask for the operation */
171 mgtcr
= ZYNQ_GEM_PHYMNTNC_OP_MASK
| op
|
172 (phy_addr
<< ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK
) |
173 (regnum
<< ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK
) | *data
;
175 /* Write mgtcr and wait for completion */
176 writel(mgtcr
, ®s
->phymntnc
);
181 if (op
== ZYNQ_GEM_PHYMNTNC_OP_R_MASK
)
182 *data
= readl(®s
->phymntnc
);
187 static u32
phyread(struct eth_device
*dev
, u32 phy_addr
, u32 regnum
, u16
*val
)
189 return phy_setup_op(dev
, phy_addr
, regnum
,
190 ZYNQ_GEM_PHYMNTNC_OP_R_MASK
, val
);
193 static u32
phywrite(struct eth_device
*dev
, u32 phy_addr
, u32 regnum
, u16 data
)
195 return phy_setup_op(dev
, phy_addr
, regnum
,
196 ZYNQ_GEM_PHYMNTNC_OP_W_MASK
, &data
);
199 static void phy_detection(struct eth_device
*dev
)
203 struct zynq_gem_priv
*priv
= dev
->priv
;
205 if (priv
->phyaddr
!= -1) {
206 phyread(dev
, priv
->phyaddr
, PHY_DETECT_REG
, &phyreg
);
207 if ((phyreg
!= 0xFFFF) &&
208 ((phyreg
& PHY_DETECT_MASK
) == PHY_DETECT_MASK
)) {
209 /* Found a valid PHY address */
210 debug("Default phy address %d is valid\n",
214 debug("PHY address is not setup correctly %d\n",
220 debug("detecting phy address\n");
221 if (priv
->phyaddr
== -1) {
222 /* detect the PHY address */
223 for (i
= 31; i
>= 0; i
--) {
224 phyread(dev
, i
, PHY_DETECT_REG
, &phyreg
);
225 if ((phyreg
!= 0xFFFF) &&
226 ((phyreg
& PHY_DETECT_MASK
) == PHY_DETECT_MASK
)) {
227 /* Found a valid PHY address */
229 debug("Found valid phy address, %d\n", i
);
234 printf("PHY is not detected\n");
237 static int zynq_gem_setup_mac(struct eth_device
*dev
)
239 u32 i
, macaddrlow
, macaddrhigh
;
240 struct zynq_gem_regs
*regs
= (struct zynq_gem_regs
*)dev
->iobase
;
242 /* Set the MAC bits [31:0] in BOT */
243 macaddrlow
= dev
->enetaddr
[0];
244 macaddrlow
|= dev
->enetaddr
[1] << 8;
245 macaddrlow
|= dev
->enetaddr
[2] << 16;
246 macaddrlow
|= dev
->enetaddr
[3] << 24;
248 /* Set MAC bits [47:32] in TOP */
249 macaddrhigh
= dev
->enetaddr
[4];
250 macaddrhigh
|= dev
->enetaddr
[5] << 8;
252 for (i
= 0; i
< 4; i
++) {
253 writel(0, ®s
->laddr
[i
][LADDR_LOW
]);
254 writel(0, ®s
->laddr
[i
][LADDR_HIGH
]);
255 /* Do not use MATCHx register */
256 writel(0, ®s
->match
[i
]);
259 writel(macaddrlow
, ®s
->laddr
[0][LADDR_LOW
]);
260 writel(macaddrhigh
, ®s
->laddr
[0][LADDR_HIGH
]);
265 static int zynq_gem_init(struct eth_device
*dev
, bd_t
* bis
)
267 u32 i
, rclk
, clk
= 0;
268 struct phy_device
*phydev
;
269 const u32 stat_size
= (sizeof(struct zynq_gem_regs
) -
270 offsetof(struct zynq_gem_regs
, stat
)) / 4;
271 struct zynq_gem_regs
*regs
= (struct zynq_gem_regs
*)dev
->iobase
;
272 struct zynq_gem_priv
*priv
= dev
->priv
;
273 const u32 supported
= SUPPORTED_10baseT_Half
|
274 SUPPORTED_10baseT_Full
|
275 SUPPORTED_100baseT_Half
|
276 SUPPORTED_100baseT_Full
|
277 SUPPORTED_1000baseT_Half
|
278 SUPPORTED_1000baseT_Full
;
281 /* Disable all interrupts */
282 writel(0xFFFFFFFF, ®s
->idr
);
284 /* Disable the receiver & transmitter */
285 writel(0, ®s
->nwctrl
);
286 writel(0, ®s
->txsr
);
287 writel(0, ®s
->rxsr
);
288 writel(0, ®s
->phymntnc
);
290 /* Clear the Hash registers for the mac address
291 * pointed by AddressPtr
293 writel(0x0, ®s
->hashl
);
294 /* Write bits [63:32] in TOP */
295 writel(0x0, ®s
->hashh
);
297 /* Clear all counters */
298 for (i
= 0; i
<= stat_size
; i
++)
299 readl(®s
->stat
[i
]);
301 /* Setup RxBD space */
302 memset(&(priv
->rx_bd
), 0, sizeof(priv
->rx_bd
));
303 /* Create the RxBD ring */
304 memset(&(priv
->rxbuffers
), 0, sizeof(priv
->rxbuffers
));
306 for (i
= 0; i
< RX_BUF
; i
++) {
307 priv
->rx_bd
[i
].status
= 0xF0000000;
308 priv
->rx_bd
[i
].addr
=
309 (u32
)((char *)&(priv
->rxbuffers
) +
310 (i
* PKTSIZE_ALIGN
));
312 /* WRAP bit to last BD */
313 priv
->rx_bd
[--i
].addr
|= ZYNQ_GEM_RXBUF_WRAP_MASK
;
314 /* Write RxBDs to IP */
315 writel((u32
)&(priv
->rx_bd
), ®s
->rxqbase
);
317 /* Setup for DMA Configuration register */
318 writel(ZYNQ_GEM_DMACR_INIT
, ®s
->dmacr
);
320 /* Setup for Network Control register, MDIO, Rx and Tx enable */
321 setbits_le32(®s
->nwctrl
, ZYNQ_GEM_NWCTRL_MDEN_MASK
);
328 /* interface - look at tsec */
329 phydev
= phy_connect(priv
->bus
, priv
->phyaddr
, dev
, 0);
331 phydev
->supported
= supported
| ADVERTISED_Pause
|
332 ADVERTISED_Asym_Pause
;
333 phydev
->advertising
= phydev
->supported
;
334 priv
->phydev
= phydev
;
338 switch (phydev
->speed
) {
340 writel(ZYNQ_GEM_NWCFG_INIT
| ZYNQ_GEM_NWCFG_SPEED1000
,
342 rclk
= (0 << 4) | (1 << 0);
343 clk
= (1 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
346 clrsetbits_le32(®s
->nwcfg
, ZYNQ_GEM_NWCFG_SPEED1000
,
347 ZYNQ_GEM_NWCFG_INIT
| ZYNQ_GEM_NWCFG_SPEED100
);
349 clk
= (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
354 clk
= (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
358 /* Change the rclk and clk only not using EMIO interface */
360 zynq_slcr_gem_clk_setup(dev
->iobase
!=
361 ZYNQ_GEM_BASEADDR0
, rclk
, clk
);
363 setbits_le32(®s
->nwctrl
, ZYNQ_GEM_NWCTRL_RXEN_MASK
|
364 ZYNQ_GEM_NWCTRL_TXEN_MASK
);
369 static int zynq_gem_send(struct eth_device
*dev
, void *ptr
, int len
)
372 struct zynq_gem_priv
*priv
= dev
->priv
;
373 struct zynq_gem_regs
*regs
= (struct zynq_gem_regs
*)dev
->iobase
;
374 const u32 mask
= ZYNQ_GEM_TXSR_HRESPNOK_MASK
| \
375 ZYNQ_GEM_TXSR_URUN_MASK
| ZYNQ_GEM_TXSR_BUFEXH_MASK
;
378 writel((u32
)&(priv
->tx_bd
), ®s
->txqbase
);
381 memset((void *)&(priv
->tx_bd
), 0, sizeof(struct emac_bd
));
383 priv
->tx_bd
.addr
= (u32
)ptr
;
384 priv
->tx_bd
.status
= len
| ZYNQ_GEM_TXBUF_LAST_MASK
;
387 setbits_le32(®s
->nwctrl
, ZYNQ_GEM_NWCTRL_STARTTX_MASK
);
389 /* Read the stat register to know if the packet has been transmitted */
390 status
= readl(®s
->txsr
);
392 printf("Something has gone wrong here!? Status is 0x%x.\n",
395 /* Clear Tx status register before leaving . */
396 writel(status
, ®s
->txsr
);
400 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
401 static int zynq_gem_recv(struct eth_device
*dev
)
404 struct zynq_gem_priv
*priv
= dev
->priv
;
405 struct emac_bd
*current_bd
= &priv
->rx_bd
[priv
->rxbd_current
];
406 struct emac_bd
*first_bd
;
408 if (!(current_bd
->addr
& ZYNQ_GEM_RXBUF_NEW_MASK
))
411 if (!(current_bd
->status
&
412 (ZYNQ_GEM_RXBUF_SOF_MASK
| ZYNQ_GEM_RXBUF_EOF_MASK
))) {
413 printf("GEM: SOF or EOF not set for last buffer received!\n");
417 frame_len
= current_bd
->status
& ZYNQ_GEM_RXBUF_LEN_MASK
;
419 NetReceive((u8
*) (current_bd
->addr
&
420 ZYNQ_GEM_RXBUF_ADD_MASK
), frame_len
);
422 if (current_bd
->status
& ZYNQ_GEM_RXBUF_SOF_MASK
)
423 priv
->rx_first_buf
= priv
->rxbd_current
;
425 current_bd
->addr
&= ~ZYNQ_GEM_RXBUF_NEW_MASK
;
426 current_bd
->status
= 0xF0000000; /* FIXME */
429 if (current_bd
->status
& ZYNQ_GEM_RXBUF_EOF_MASK
) {
430 first_bd
= &priv
->rx_bd
[priv
->rx_first_buf
];
431 first_bd
->addr
&= ~ZYNQ_GEM_RXBUF_NEW_MASK
;
432 first_bd
->status
= 0xF0000000;
435 if ((++priv
->rxbd_current
) >= RX_BUF
)
436 priv
->rxbd_current
= 0;
442 static void zynq_gem_halt(struct eth_device
*dev
)
444 struct zynq_gem_regs
*regs
= (struct zynq_gem_regs
*)dev
->iobase
;
446 clrsetbits_le32(®s
->nwctrl
, ZYNQ_GEM_NWCTRL_RXEN_MASK
|
447 ZYNQ_GEM_NWCTRL_TXEN_MASK
, 0);
450 static int zynq_gem_miiphyread(const char *devname
, uchar addr
,
451 uchar reg
, ushort
*val
)
453 struct eth_device
*dev
= eth_get_dev();
456 ret
= phyread(dev
, addr
, reg
, val
);
457 debug("%s 0x%x, 0x%x, 0x%x\n", __func__
, addr
, reg
, *val
);
461 static int zynq_gem_miiphy_write(const char *devname
, uchar addr
,
462 uchar reg
, ushort val
)
464 struct eth_device
*dev
= eth_get_dev();
466 debug("%s 0x%x, 0x%x, 0x%x\n", __func__
, addr
, reg
, val
);
467 return phywrite(dev
, addr
, reg
, val
);
470 int zynq_gem_initialize(bd_t
*bis
, int base_addr
, int phy_addr
, u32 emio
)
472 struct eth_device
*dev
;
473 struct zynq_gem_priv
*priv
;
475 dev
= calloc(1, sizeof(*dev
));
479 dev
->priv
= calloc(1, sizeof(struct zynq_gem_priv
));
480 if (dev
->priv
== NULL
) {
486 priv
->phyaddr
= phy_addr
;
489 sprintf(dev
->name
, "Gem.%x", base_addr
);
491 dev
->iobase
= base_addr
;
493 dev
->init
= zynq_gem_init
;
494 dev
->halt
= zynq_gem_halt
;
495 dev
->send
= zynq_gem_send
;
496 dev
->recv
= zynq_gem_recv
;
497 dev
->write_hwaddr
= zynq_gem_setup_mac
;
501 miiphy_register(dev
->name
, zynq_gem_miiphyread
, zynq_gem_miiphy_write
);
502 priv
->bus
= miiphy_get_dev_by_name(dev
->name
);