drivers/net/zynq_gem.c

   1 /*
   2  * (C) Copyright 2011 Michal Simek
   3  *
   4  * Michal SIMEK <monstr@monstr.eu>
   5  *
   6  * Based on Xilinx gmac driver:
   7  * (C) Copyright 2011 Xilinx
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <dm.h>
  14 #include <net.h>
  15 #include <netdev.h>
  16 #include <config.h>
  17 #include <console.h>
  18 #include <malloc.h>
  19 #include <asm/io.h>
  20 #include <phy.h>
  21 #include <miiphy.h>
  22 #include <watchdog.h>
  23 #include <asm/system.h>
  24 #include <asm/arch/hardware.h>
  25 #include <asm/arch/sys_proto.h>
  26 #include <asm-generic/errno.h>
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 #if !defined(CONFIG_PHYLIB)
  31 # error XILINX_GEM_ETHERNET requires PHYLIB
  32 #endif
  33
  34 /* Bit/mask specification */
  35 #define ZYNQ_GEM_PHYMNTNC_OP_MASK       0x40020000 /* operation mask bits */
  36 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK     0x20000000 /* read operation */
  37 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK     0x10000000 /* write operation */
  38 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK      23 /* Shift bits for PHYAD */
  39 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK      18 /* Shift bits for PHREG */
  40
  41 #define ZYNQ_GEM_RXBUF_EOF_MASK         0x00008000 /* End of frame. */
  42 #define ZYNQ_GEM_RXBUF_SOF_MASK         0x00004000 /* Start of frame. */
  43 #define ZYNQ_GEM_RXBUF_LEN_MASK         0x00003FFF /* Mask for length field */
  44
  45 #define ZYNQ_GEM_RXBUF_WRAP_MASK        0x00000002 /* Wrap bit, last BD */
  46 #define ZYNQ_GEM_RXBUF_NEW_MASK         0x00000001 /* Used bit.. */
  47 #define ZYNQ_GEM_RXBUF_ADD_MASK         0xFFFFFFFC /* Mask for address */
  48
  49 /* Wrap bit, last descriptor */
  50 #define ZYNQ_GEM_TXBUF_WRAP_MASK        0x40000000
  51 #define ZYNQ_GEM_TXBUF_LAST_MASK        0x00008000 /* Last buffer */
  52 #define ZYNQ_GEM_TXBUF_USED_MASK        0x80000000 /* Used by Hw */
  53
  54 #define ZYNQ_GEM_NWCTRL_TXEN_MASK       0x00000008 /* Enable transmit */
  55 #define ZYNQ_GEM_NWCTRL_RXEN_MASK       0x00000004 /* Enable receive */
  56 #define ZYNQ_GEM_NWCTRL_MDEN_MASK       0x00000010 /* Enable MDIO port */
  57 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK    0x00000200 /* Start tx (tx_go) */
  58
  59 #define ZYNQ_GEM_NWCFG_SPEED100         0x000000001 /* 100 Mbps operation */
  60 #define ZYNQ_GEM_NWCFG_SPEED1000        0x000000400 /* 1Gbps operation */
  61 #define ZYNQ_GEM_NWCFG_FDEN             0x000000002 /* Full Duplex mode */
  62 #define ZYNQ_GEM_NWCFG_FSREM            0x000020000 /* FCS removal */
  63 #define ZYNQ_GEM_NWCFG_MDCCLKDIV        0x0000c0000 /* Div pclk by 48, max 120MHz */
  64
  65 #ifdef CONFIG_ARM64
  66 # define ZYNQ_GEM_DBUS_WIDTH    (1 << 21) /* 64 bit bus */
  67 #else
  68 # define ZYNQ_GEM_DBUS_WIDTH    (0 << 21) /* 32 bit bus */
  69 #endif
  70
  71 #define ZYNQ_GEM_NWCFG_INIT             (ZYNQ_GEM_DBUS_WIDTH | \
  72                                         ZYNQ_GEM_NWCFG_FDEN | \
  73                                         ZYNQ_GEM_NWCFG_FSREM | \
  74                                         ZYNQ_GEM_NWCFG_MDCCLKDIV)
  75
  76 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK     0x00000004 /* PHY management idle */
  77
  78 #define ZYNQ_GEM_DMACR_BLENGTH          0x00000004 /* INCR4 AHB bursts */
  79 /* Use full configured addressable space (8 Kb) */
  80 #define ZYNQ_GEM_DMACR_RXSIZE           0x00000300
  81 /* Use full configured addressable space (4 Kb) */
  82 #define ZYNQ_GEM_DMACR_TXSIZE           0x00000400
  83 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
  84 #define ZYNQ_GEM_DMACR_RXBUF            0x00180000
  85
  86 #define ZYNQ_GEM_DMACR_INIT             (ZYNQ_GEM_DMACR_BLENGTH | \
  87                                         ZYNQ_GEM_DMACR_RXSIZE | \
  88                                         ZYNQ_GEM_DMACR_TXSIZE | \
  89                                         ZYNQ_GEM_DMACR_RXBUF)
  90
  91 #define ZYNQ_GEM_TSR_DONE               0x00000020 /* Tx done mask */
  92
  93 /* Use MII register 1 (MII status register) to detect PHY */
  94 #define PHY_DETECT_REG  1
  95
  96 /* Mask used to verify certain PHY features (or register contents)
  97  * in the register above:
  98  *  0x1000: 10Mbps full duplex support
  99  *  0x0800: 10Mbps half duplex support
 100  *  0x0008: Auto-negotiation support
 101  */
 102 #define PHY_DETECT_MASK 0x1808
 103
 104 /* TX BD status masks */
 105 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK      0x000007ff
 106 #define ZYNQ_GEM_TXBUF_EXHAUSTED        0x08000000
 107 #define ZYNQ_GEM_TXBUF_UNDERRUN         0x10000000
 108
 109 /* Clock frequencies for different speeds */
 110 #define ZYNQ_GEM_FREQUENCY_10   2500000UL
 111 #define ZYNQ_GEM_FREQUENCY_100  25000000UL
 112 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL
 113
 114 /* Device registers */
 115 struct zynq_gem_regs {
 116         u32 nwctrl; /* 0x0 - Network Control reg */
 117         u32 nwcfg; /* 0x4 - Network Config reg */
 118         u32 nwsr; /* 0x8 - Network Status reg */
 119         u32 reserved1;
 120         u32 dmacr; /* 0x10 - DMA Control reg */
 121         u32 txsr; /* 0x14 - TX Status reg */
 122         u32 rxqbase; /* 0x18 - RX Q Base address reg */
 123         u32 txqbase; /* 0x1c - TX Q Base address reg */
 124         u32 rxsr; /* 0x20 - RX Status reg */
 125         u32 reserved2[2];
 126         u32 idr; /* 0x2c - Interrupt Disable reg */
 127         u32 reserved3;
 128         u32 phymntnc; /* 0x34 - Phy Maintaince reg */
 129         u32 reserved4[18];
 130         u32 hashl; /* 0x80 - Hash Low address reg */
 131         u32 hashh; /* 0x84 - Hash High address reg */
 132 #define LADDR_LOW       0
 133 #define LADDR_HIGH      1
 134         u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
 135         u32 match[4]; /* 0xa8 - Type ID1 Match reg */
 136         u32 reserved6[18];
 137 #define STAT_SIZE       44
 138         u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
 139         u32 reserved7[164];
 140         u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
 141         u32 reserved8[15];
 142         u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
 143 };
 144
 145 /* BD descriptors */
 146 struct emac_bd {
 147         u32 addr; /* Next descriptor pointer */
 148         u32 status;
 149 };
 150
 151 #define RX_BUF 32
 152 /* Page table entries are set to 1MB, or multiples of 1MB
 153  * (not < 1MB). driver uses less bd's so use 1MB bdspace.
 154  */
 155 #define BD_SPACE        0x100000
 156 /* BD separation space */
 157 #define BD_SEPRN_SPACE  (RX_BUF * sizeof(struct emac_bd))
 158
 159 /* Setup the first free TX descriptor */
 160 #define TX_FREE_DESC    2
 161
 162 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
 163 struct zynq_gem_priv {
 164         struct emac_bd *tx_bd;
 165         struct emac_bd *rx_bd;
 166         char *rxbuffers;
 167         u32 rxbd_current;
 168         u32 rx_first_buf;
 169         int phyaddr;
 170         u32 emio;
 171         int init;
 172         struct zynq_gem_regs *iobase;
 173         phy_interface_t interface;
 174         struct phy_device *phydev;
 175         struct mii_dev *bus;
 176 };
 177
 178 static inline int mdio_wait(struct zynq_gem_regs *regs)
 179 {
 180         u32 timeout = 20000;
 181
 182         /* Wait till MDIO interface is ready to accept a new transaction. */
 183         while (--timeout) {
 184                 if (readl(&regs->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)
 185                         break;
 186                 WATCHDOG_RESET();
 187         }
 188
 189         if (!timeout) {
 190                 printf("%s: Timeout\n", __func__);
 191                 return 1;
 192         }
 193
 194         return 0;
 195 }
 196
 197 static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
 198                         u32 op, u16 *data)
 199 {
 200         u32 mgtcr;
 201         struct zynq_gem_regs *regs = priv->iobase;
 202
 203         if (mdio_wait(regs))
 204                 return 1;
 205
 206         /* Construct mgtcr mask for the operation */
 207         mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
 208                 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
 209                 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
 210
 211         /* Write mgtcr and wait for completion */
 212         writel(mgtcr, &regs->phymntnc);
 213
 214         if (mdio_wait(regs))
 215                 return 1;
 216
 217         if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
 218                 *data = readl(&regs->phymntnc);
 219
 220         return 0;
 221 }
 222
 223 static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr,
 224                    u32 regnum, u16 *val)
 225 {
 226         u32 ret;
 227
 228         ret = phy_setup_op(priv, phy_addr, regnum,
 229                            ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
 230
 231         if (!ret)
 232                 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
 233                       phy_addr, regnum, *val);
 234
 235         return ret;
 236 }
 237
 238 static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
 239                     u32 regnum, u16 data)
 240 {
 241         debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
 242               regnum, data);
 243
 244         return phy_setup_op(priv, phy_addr, regnum,
 245                             ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
 246 }
 247
 248 static int phy_detection(struct udevice *dev)
 249 {
 250         int i;
 251         u16 phyreg;
 252         struct zynq_gem_priv *priv = dev->priv;
 253
 254         if (priv->phyaddr != -1) {
 255                 phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg);
 256                 if ((phyreg != 0xFFFF) &&
 257                     ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
 258                         /* Found a valid PHY address */
 259                         debug("Default phy address %d is valid\n",
 260                               priv->phyaddr);
 261                         return 0;
 262                 } else {
 263                         debug("PHY address is not setup correctly %d\n",
 264                               priv->phyaddr);
 265                         priv->phyaddr = -1;
 266                 }
 267         }
 268
 269         debug("detecting phy address\n");
 270         if (priv->phyaddr == -1) {
 271                 /* detect the PHY address */
 272                 for (i = 31; i >= 0; i--) {
 273                         phyread(priv, i, PHY_DETECT_REG, &phyreg);
 274                         if ((phyreg != 0xFFFF) &&
 275                             ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
 276                                 /* Found a valid PHY address */
 277                                 priv->phyaddr = i;
 278                                 debug("Found valid phy address, %d\n", i);
 279                                 return 0;
 280                         }
 281                 }
 282         }
 283         printf("PHY is not detected\n");
 284         return -1;
 285 }
 286
 287 static int zynq_gem_setup_mac(struct udevice *dev)
 288 {
 289         u32 i, macaddrlow, macaddrhigh;
 290         struct eth_pdata *pdata = dev_get_platdata(dev);
 291         struct zynq_gem_priv *priv = dev_get_priv(dev);
 292         struct zynq_gem_regs *regs = priv->iobase;
 293
 294         /* Set the MAC bits [31:0] in BOT */
 295         macaddrlow = pdata->enetaddr[0];
 296         macaddrlow |= pdata->enetaddr[1] << 8;
 297         macaddrlow |= pdata->enetaddr[2] << 16;
 298         macaddrlow |= pdata->enetaddr[3] << 24;
 299
 300         /* Set MAC bits [47:32] in TOP */
 301         macaddrhigh = pdata->enetaddr[4];
 302         macaddrhigh |= pdata->enetaddr[5] << 8;
 303
 304         for (i = 0; i < 4; i++) {
 305                 writel(0, &regs->laddr[i][LADDR_LOW]);
 306                 writel(0, &regs->laddr[i][LADDR_HIGH]);
 307                 /* Do not use MATCHx register */
 308                 writel(0, &regs->match[i]);
 309         }
 310
 311         writel(macaddrlow, &regs->laddr[0][LADDR_LOW]);
 312         writel(macaddrhigh, &regs->laddr[0][LADDR_HIGH]);
 313
 314         return 0;
 315 }
 316
 317 static int zynq_phy_init(struct udevice *dev)
 318 {
 319         int ret;
 320         struct zynq_gem_priv *priv = dev_get_priv(dev);
 321         struct zynq_gem_regs *regs = priv->iobase;
 322         const u32 supported = SUPPORTED_10baseT_Half |
 323                         SUPPORTED_10baseT_Full |
 324                         SUPPORTED_100baseT_Half |
 325                         SUPPORTED_100baseT_Full |
 326                         SUPPORTED_1000baseT_Half |
 327                         SUPPORTED_1000baseT_Full;
 328
 329         /* Enable only MDIO bus */
 330         writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, &regs->nwctrl);
 331
 332         ret = phy_detection(dev);
 333         if (ret) {
 334                 printf("GEM PHY init failed\n");
 335                 return ret;
 336         }
 337
 338         priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
 339                                    priv->interface);
 340         if (!priv->phydev)
 341                 return -ENODEV;
 342
 343         priv->phydev->supported = supported | ADVERTISED_Pause |
 344                                   ADVERTISED_Asym_Pause;
 345         priv->phydev->advertising = priv->phydev->supported;
 346         phy_config(priv->phydev);
 347
 348         return 0;
 349 }
 350
 351 static int zynq_gem_init(struct udevice *dev)
 352 {
 353         u32 i;
 354         unsigned long clk_rate = 0;
 355         struct zynq_gem_priv *priv = dev_get_priv(dev);
 356         struct zynq_gem_regs *regs = priv->iobase;
 357         struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
 358         struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
 359
 360         if (!priv->init) {
 361                 /* Disable all interrupts */
 362                 writel(0xFFFFFFFF, &regs->idr);
 363
 364                 /* Disable the receiver & transmitter */
 365                 writel(0, &regs->nwctrl);
 366                 writel(0, &regs->txsr);
 367                 writel(0, &regs->rxsr);
 368                 writel(0, &regs->phymntnc);
 369
 370                 /* Clear the Hash registers for the mac address
 371                  * pointed by AddressPtr
 372                  */
 373                 writel(0x0, &regs->hashl);
 374                 /* Write bits [63:32] in TOP */
 375                 writel(0x0, &regs->hashh);
 376
 377                 /* Clear all counters */
 378                 for (i = 0; i < STAT_SIZE; i++)
 379                         readl(&regs->stat[i]);
 380
 381                 /* Setup RxBD space */
 382                 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
 383
 384                 for (i = 0; i < RX_BUF; i++) {
 385                         priv->rx_bd[i].status = 0xF0000000;
 386                         priv->rx_bd[i].addr =
 387                                         ((ulong)(priv->rxbuffers) +
 388                                                         (i * PKTSIZE_ALIGN));
 389                 }
 390                 /* WRAP bit to last BD */
 391                 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
 392                 /* Write RxBDs to IP */
 393                 writel((ulong)priv->rx_bd, &regs->rxqbase);
 394
 395                 /* Setup for DMA Configuration register */
 396                 writel(ZYNQ_GEM_DMACR_INIT, &regs->dmacr);
 397
 398                 /* Setup for Network Control register, MDIO, Rx and Tx enable */
 399                 setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
 400
 401                 /* Disable the second priority queue */
 402                 dummy_tx_bd->addr = 0;
 403                 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
 404                                 ZYNQ_GEM_TXBUF_LAST_MASK|
 405                                 ZYNQ_GEM_TXBUF_USED_MASK;
 406
 407                 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
 408                                 ZYNQ_GEM_RXBUF_NEW_MASK;
 409                 dummy_rx_bd->status = 0;
 410                 flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd +
 411                                    sizeof(dummy_tx_bd));
 412                 flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd +
 413                                    sizeof(dummy_rx_bd));
 414
 415                 writel((ulong)dummy_tx_bd, &regs->transmit_q1_ptr);
 416                 writel((ulong)dummy_rx_bd, &regs->receive_q1_ptr);
 417
 418                 priv->init++;
 419         }
 420
 421         phy_startup(priv->phydev);
 422
 423         if (!priv->phydev->link) {
 424                 printf("%s: No link.\n", priv->phydev->dev->name);
 425                 return -1;
 426         }
 427
 428         switch (priv->phydev->speed) {
 429         case SPEED_1000:
 430                 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
 431                        &regs->nwcfg);
 432                 clk_rate = ZYNQ_GEM_FREQUENCY_1000;
 433                 break;
 434         case SPEED_100:
 435                 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100,
 436                        &regs->nwcfg);
 437                 clk_rate = ZYNQ_GEM_FREQUENCY_100;
 438                 break;
 439         case SPEED_10:
 440                 clk_rate = ZYNQ_GEM_FREQUENCY_10;
 441                 break;
 442         }
 443
 444         /* Change the rclk and clk only not using EMIO interface */
 445         if (!priv->emio)
 446                 zynq_slcr_gem_clk_setup((ulong)priv->iobase !=
 447                                         ZYNQ_GEM_BASEADDR0, clk_rate);
 448
 449         setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
 450                                         ZYNQ_GEM_NWCTRL_TXEN_MASK);
 451
 452         return 0;
 453 }
 454
 455 static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
 456                         bool set, unsigned int timeout)
 457 {
 458         u32 val;
 459         unsigned long start = get_timer(0);
 460
 461         while (1) {
 462                 val = readl(reg);
 463
 464                 if (!set)
 465                         val = ~val;
 466
 467                 if ((val & mask) == mask)
 468                         return 0;
 469
 470                 if (get_timer(start) > timeout)
 471                         break;
 472
 473                 if (ctrlc()) {
 474                         puts("Abort\n");
 475                         return -EINTR;
 476                 }
 477
 478                 udelay(1);
 479         }
 480
 481         debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
 482               func, reg, mask, set);
 483
 484         return -ETIMEDOUT;
 485 }
 486
 487 static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
 488 {
 489         u32 addr, size;
 490         struct zynq_gem_priv *priv = dev_get_priv(dev);
 491         struct zynq_gem_regs *regs = priv->iobase;
 492         struct emac_bd *current_bd = &priv->tx_bd[1];
 493
 494         /* Setup Tx BD */
 495         memset(priv->tx_bd, 0, sizeof(struct emac_bd));
 496
 497         priv->tx_bd->addr = (ulong)ptr;
 498         priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
 499                                ZYNQ_GEM_TXBUF_LAST_MASK;
 500         /* Dummy descriptor to mark it as the last in descriptor chain */
 501         current_bd->addr = 0x0;
 502         current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
 503                              ZYNQ_GEM_TXBUF_LAST_MASK|
 504                              ZYNQ_GEM_TXBUF_USED_MASK;
 505
 506         /* setup BD */
 507         writel((ulong)priv->tx_bd, &regs->txqbase);
 508
 509         addr = (ulong) ptr;
 510         addr &= ~(ARCH_DMA_MINALIGN - 1);
 511         size = roundup(len, ARCH_DMA_MINALIGN);
 512         flush_dcache_range(addr, addr + size);
 513
 514         addr = (ulong)priv->rxbuffers;
 515         addr &= ~(ARCH_DMA_MINALIGN - 1);
 516         size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN);
 517         flush_dcache_range(addr, addr + size);
 518         barrier();
 519
 520         /* Start transmit */
 521         setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
 522
 523         /* Read TX BD status */
 524         if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
 525                 printf("TX buffers exhausted in mid frame\n");
 526
 527         return wait_for_bit(__func__, &regs->txsr, ZYNQ_GEM_TSR_DONE,
 528                             true, 20000);
 529 }
 530
 531 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
 532 static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
 533 {
 534         int frame_len;
 535         u32 addr;
 536         struct zynq_gem_priv *priv = dev_get_priv(dev);
 537         struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
 538
 539         if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
 540                 return -1;
 541
 542         if (!(current_bd->status &
 543                         (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
 544                 printf("GEM: SOF or EOF not set for last buffer received!\n");
 545                 return -1;
 546         }
 547
 548         frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
 549         if (!frame_len) {
 550                 printf("%s: Zero size packet?\n", __func__);
 551                 return -1;
 552         }
 553
 554         addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
 555         addr &= ~(ARCH_DMA_MINALIGN - 1);
 556         *packetp = (uchar *)(uintptr_t)addr;
 557
 558         return frame_len;
 559 }
 560
 561 static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length)
 562 {
 563         struct zynq_gem_priv *priv = dev_get_priv(dev);
 564         struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
 565         struct emac_bd *first_bd;
 566
 567         if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) {
 568                 priv->rx_first_buf = priv->rxbd_current;
 569         } else {
 570                 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
 571                 current_bd->status = 0xF0000000; /* FIXME */
 572         }
 573
 574         if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
 575                 first_bd = &priv->rx_bd[priv->rx_first_buf];
 576                 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
 577                 first_bd->status = 0xF0000000;
 578         }
 579
 580         if ((++priv->rxbd_current) >= RX_BUF)
 581                 priv->rxbd_current = 0;
 582
 583         return 0;
 584 }
 585
 586 static void zynq_gem_halt(struct udevice *dev)
 587 {
 588         struct zynq_gem_priv *priv = dev_get_priv(dev);
 589         struct zynq_gem_regs *regs = priv->iobase;
 590
 591         clrsetbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
 592                                                 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
 593 }
 594
 595 static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr,
 596                                 int devad, int reg)
 597 {
 598         struct zynq_gem_priv *priv = bus->priv;
 599         int ret;
 600         u16 val;
 601
 602         ret = phyread(priv, addr, reg, &val);
 603         debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret);
 604         return val;
 605 }
 606
 607 static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad,
 608                                  int reg, u16 value)
 609 {
 610         struct zynq_gem_priv *priv = bus->priv;
 611
 612         debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value);
 613         return phywrite(priv, addr, reg, value);
 614 }
 615
 616 static int zynq_gem_probe(struct udevice *dev)
 617 {
 618         void *bd_space;
 619         struct zynq_gem_priv *priv = dev_get_priv(dev);
 620         int ret;
 621
 622         /* Align rxbuffers to ARCH_DMA_MINALIGN */
 623         priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
 624         memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
 625
 626         /* Align bd_space to MMU_SECTION_SHIFT */
 627         bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
 628         mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
 629                                         BD_SPACE, DCACHE_OFF);
 630
 631         /* Initialize the bd spaces for tx and rx bd's */
 632         priv->tx_bd = (struct emac_bd *)bd_space;
 633         priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
 634
 635         priv->bus = mdio_alloc();
 636         priv->bus->read = zynq_gem_miiphy_read;
 637         priv->bus->write = zynq_gem_miiphy_write;
 638         priv->bus->priv = priv;
 639         strcpy(priv->bus->name, "gem");
 640
 641         ret = mdio_register(priv->bus);
 642         if (ret)
 643                 return ret;
 644
 645         zynq_phy_init(dev);
 646
 647         return 0;
 648 }
 649
 650 static int zynq_gem_remove(struct udevice *dev)
 651 {
 652         struct zynq_gem_priv *priv = dev_get_priv(dev);
 653
 654         free(priv->phydev);
 655         mdio_unregister(priv->bus);
 656         mdio_free(priv->bus);
 657
 658         return 0;
 659 }
 660
 661 static const struct eth_ops zynq_gem_ops = {
 662         .start                  = zynq_gem_init,
 663         .send                   = zynq_gem_send,
 664         .recv                   = zynq_gem_recv,
 665         .free_pkt               = zynq_gem_free_pkt,
 666         .stop                   = zynq_gem_halt,
 667         .write_hwaddr           = zynq_gem_setup_mac,
 668 };
 669
 670 static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
 671 {
 672         struct eth_pdata *pdata = dev_get_platdata(dev);
 673         struct zynq_gem_priv *priv = dev_get_priv(dev);
 674         int offset = 0;
 675         const char *phy_mode;
 676
 677         pdata->iobase = (phys_addr_t)dev_get_addr(dev);
 678         priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
 679         /* Hardcode for now */
 680         priv->emio = 0;
 681         priv->phyaddr = -1;
 682
 683         offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
 684                                        "phy-handle");
 685         if (offset > 0)
 686                 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
 687
 688         phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
 689         if (phy_mode)
 690                 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
 691         if (pdata->phy_interface == -1) {
 692                 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
 693                 return -EINVAL;
 694         }
 695         priv->interface = pdata->phy_interface;
 696
 697         printf("ZYNQ GEM: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
 698                priv->phyaddr, phy_string_for_interface(priv->interface));
 699
 700         return 0;
 701 }
 702
 703 static const struct udevice_id zynq_gem_ids[] = {
 704         { .compatible = "cdns,zynqmp-gem" },
 705         { .compatible = "cdns,zynq-gem" },
 706         { .compatible = "cdns,gem" },
 707         { }
 708 };
 709
 710 U_BOOT_DRIVER(zynq_gem) = {
 711         .name   = "zynq_gem",
 712         .id     = UCLASS_ETH,
 713         .of_match = zynq_gem_ids,
 714         .ofdata_to_platdata = zynq_gem_ofdata_to_platdata,
 715         .probe  = zynq_gem_probe,
 716         .remove = zynq_gem_remove,
 717         .ops    = &zynq_gem_ops,
 718         .priv_auto_alloc_size = sizeof(struct zynq_gem_priv),
 719         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
 720 };