2 * (C) Copyright 2011 Michal Simek
4 * Michal SIMEK <monstr@monstr.eu>
6 * Based on Xilinx gmac driver:
7 * (C) Copyright 2011 Xilinx
9 * SPDX-License-Identifier: GPL-2.0+
23 #include <asm/arch/hardware.h>
24 #include <asm/arch/sys_proto.h>
26 #if !defined(CONFIG_PHYLIB)
27 # error XILINX_GEM_ETHERNET requires PHYLIB
30 /* Bit/mask specification */
31 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
32 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
33 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
34 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
35 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
37 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
38 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
39 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
41 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
42 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
43 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
45 /* Wrap bit, last descriptor */
46 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
47 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
49 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
50 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
51 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
52 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
54 #define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */
55 #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */
56 #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */
57 #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */
58 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */
59 #define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */
61 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_NWCFG_FDEN | \
62 ZYNQ_GEM_NWCFG_FSREM | \
63 ZYNQ_GEM_NWCFG_MDCCLKDIV)
65 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
67 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
68 /* Use full configured addressable space (8 Kb) */
69 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
70 /* Use full configured addressable space (4 Kb) */
71 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
72 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
73 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000
75 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
76 ZYNQ_GEM_DMACR_RXSIZE | \
77 ZYNQ_GEM_DMACR_TXSIZE | \
80 /* Use MII register 1 (MII status register) to detect PHY */
81 #define PHY_DETECT_REG 1
83 /* Mask used to verify certain PHY features (or register contents)
84 * in the register above:
85 * 0x1000: 10Mbps full duplex support
86 * 0x0800: 10Mbps half duplex support
87 * 0x0008: Auto-negotiation support
89 #define PHY_DETECT_MASK 0x1808
91 /* TX BD status masks */
92 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
93 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
94 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
96 /* Clock frequencies for different speeds */
97 #define ZYNQ_GEM_FREQUENCY_10 2500000UL
98 #define ZYNQ_GEM_FREQUENCY_100 25000000UL
99 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL
101 /* Device registers */
102 struct zynq_gem_regs
{
103 u32 nwctrl
; /* Network Control reg */
104 u32 nwcfg
; /* Network Config reg */
105 u32 nwsr
; /* Network Status reg */
107 u32 dmacr
; /* DMA Control reg */
108 u32 txsr
; /* TX Status reg */
109 u32 rxqbase
; /* RX Q Base address reg */
110 u32 txqbase
; /* TX Q Base address reg */
111 u32 rxsr
; /* RX Status reg */
113 u32 idr
; /* Interrupt Disable reg */
115 u32 phymntnc
; /* Phy Maintaince reg */
117 u32 hashl
; /* Hash Low address reg */
118 u32 hashh
; /* Hash High address reg */
121 u32 laddr
[4][LADDR_HIGH
+ 1]; /* Specific1 addr low/high reg */
122 u32 match
[4]; /* Type ID1 Match reg */
124 u32 stat
[44]; /* Octects transmitted Low reg - stat start */
129 u32 addr
; /* Next descriptor pointer */
134 /* Page table entries are set to 1MB, or multiples of 1MB
135 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
137 #define BD_SPACE 0x100000
138 /* BD separation space */
139 #define BD_SEPRN_SPACE 64
141 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
142 struct zynq_gem_priv
{
143 struct emac_bd
*tx_bd
;
144 struct emac_bd
*rx_bd
;
151 struct phy_device
*phydev
;
155 static inline int mdio_wait(struct eth_device
*dev
)
157 struct zynq_gem_regs
*regs
= (struct zynq_gem_regs
*)dev
->iobase
;
160 /* Wait till MDIO interface is ready to accept a new transaction. */
162 if (readl(®s
->nwsr
) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK
)
168 printf("%s: Timeout\n", __func__
);
175 static u32
phy_setup_op(struct eth_device
*dev
, u32 phy_addr
, u32 regnum
,
179 struct zynq_gem_regs
*regs
= (struct zynq_gem_regs
*)dev
->iobase
;
184 /* Construct mgtcr mask for the operation */
185 mgtcr
= ZYNQ_GEM_PHYMNTNC_OP_MASK
| op
|
186 (phy_addr
<< ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK
) |
187 (regnum
<< ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK
) | *data
;
189 /* Write mgtcr and wait for completion */
190 writel(mgtcr
, ®s
->phymntnc
);
195 if (op
== ZYNQ_GEM_PHYMNTNC_OP_R_MASK
)
196 *data
= readl(®s
->phymntnc
);
201 static u32
phyread(struct eth_device
*dev
, u32 phy_addr
, u32 regnum
, u16
*val
)
203 return phy_setup_op(dev
, phy_addr
, regnum
,
204 ZYNQ_GEM_PHYMNTNC_OP_R_MASK
, val
);
207 static u32
phywrite(struct eth_device
*dev
, u32 phy_addr
, u32 regnum
, u16 data
)
209 return phy_setup_op(dev
, phy_addr
, regnum
,
210 ZYNQ_GEM_PHYMNTNC_OP_W_MASK
, &data
);
213 static void phy_detection(struct eth_device
*dev
)
217 struct zynq_gem_priv
*priv
= dev
->priv
;
219 if (priv
->phyaddr
!= -1) {
220 phyread(dev
, priv
->phyaddr
, PHY_DETECT_REG
, &phyreg
);
221 if ((phyreg
!= 0xFFFF) &&
222 ((phyreg
& PHY_DETECT_MASK
) == PHY_DETECT_MASK
)) {
223 /* Found a valid PHY address */
224 debug("Default phy address %d is valid\n",
228 debug("PHY address is not setup correctly %d\n",
234 debug("detecting phy address\n");
235 if (priv
->phyaddr
== -1) {
236 /* detect the PHY address */
237 for (i
= 31; i
>= 0; i
--) {
238 phyread(dev
, i
, PHY_DETECT_REG
, &phyreg
);
239 if ((phyreg
!= 0xFFFF) &&
240 ((phyreg
& PHY_DETECT_MASK
) == PHY_DETECT_MASK
)) {
241 /* Found a valid PHY address */
243 debug("Found valid phy address, %d\n", i
);
248 printf("PHY is not detected\n");
251 static int zynq_gem_setup_mac(struct eth_device
*dev
)
253 u32 i
, macaddrlow
, macaddrhigh
;
254 struct zynq_gem_regs
*regs
= (struct zynq_gem_regs
*)dev
->iobase
;
256 /* Set the MAC bits [31:0] in BOT */
257 macaddrlow
= dev
->enetaddr
[0];
258 macaddrlow
|= dev
->enetaddr
[1] << 8;
259 macaddrlow
|= dev
->enetaddr
[2] << 16;
260 macaddrlow
|= dev
->enetaddr
[3] << 24;
262 /* Set MAC bits [47:32] in TOP */
263 macaddrhigh
= dev
->enetaddr
[4];
264 macaddrhigh
|= dev
->enetaddr
[5] << 8;
266 for (i
= 0; i
< 4; i
++) {
267 writel(0, ®s
->laddr
[i
][LADDR_LOW
]);
268 writel(0, ®s
->laddr
[i
][LADDR_HIGH
]);
269 /* Do not use MATCHx register */
270 writel(0, ®s
->match
[i
]);
273 writel(macaddrlow
, ®s
->laddr
[0][LADDR_LOW
]);
274 writel(macaddrhigh
, ®s
->laddr
[0][LADDR_HIGH
]);
279 static int zynq_gem_init(struct eth_device
*dev
, bd_t
* bis
)
282 unsigned long clk_rate
= 0;
283 struct phy_device
*phydev
;
284 const u32 stat_size
= (sizeof(struct zynq_gem_regs
) -
285 offsetof(struct zynq_gem_regs
, stat
)) / 4;
286 struct zynq_gem_regs
*regs
= (struct zynq_gem_regs
*)dev
->iobase
;
287 struct zynq_gem_priv
*priv
= dev
->priv
;
288 const u32 supported
= SUPPORTED_10baseT_Half
|
289 SUPPORTED_10baseT_Full
|
290 SUPPORTED_100baseT_Half
|
291 SUPPORTED_100baseT_Full
|
292 SUPPORTED_1000baseT_Half
|
293 SUPPORTED_1000baseT_Full
;
296 /* Disable all interrupts */
297 writel(0xFFFFFFFF, ®s
->idr
);
299 /* Disable the receiver & transmitter */
300 writel(0, ®s
->nwctrl
);
301 writel(0, ®s
->txsr
);
302 writel(0, ®s
->rxsr
);
303 writel(0, ®s
->phymntnc
);
305 /* Clear the Hash registers for the mac address
306 * pointed by AddressPtr
308 writel(0x0, ®s
->hashl
);
309 /* Write bits [63:32] in TOP */
310 writel(0x0, ®s
->hashh
);
312 /* Clear all counters */
313 for (i
= 0; i
<= stat_size
; i
++)
314 readl(®s
->stat
[i
]);
316 /* Setup RxBD space */
317 memset(priv
->rx_bd
, 0, RX_BUF
* sizeof(struct emac_bd
));
319 for (i
= 0; i
< RX_BUF
; i
++) {
320 priv
->rx_bd
[i
].status
= 0xF0000000;
321 priv
->rx_bd
[i
].addr
=
322 ((u32
)(priv
->rxbuffers
) +
323 (i
* PKTSIZE_ALIGN
));
325 /* WRAP bit to last BD */
326 priv
->rx_bd
[--i
].addr
|= ZYNQ_GEM_RXBUF_WRAP_MASK
;
327 /* Write RxBDs to IP */
328 writel((u32
)priv
->rx_bd
, ®s
->rxqbase
);
330 /* Setup for DMA Configuration register */
331 writel(ZYNQ_GEM_DMACR_INIT
, ®s
->dmacr
);
333 /* Setup for Network Control register, MDIO, Rx and Tx enable */
334 setbits_le32(®s
->nwctrl
, ZYNQ_GEM_NWCTRL_MDEN_MASK
);
341 /* interface - look at tsec */
342 phydev
= phy_connect(priv
->bus
, priv
->phyaddr
, dev
,
343 PHY_INTERFACE_MODE_MII
);
345 phydev
->supported
= supported
| ADVERTISED_Pause
|
346 ADVERTISED_Asym_Pause
;
347 phydev
->advertising
= phydev
->supported
;
348 priv
->phydev
= phydev
;
353 printf("%s: No link.\n", phydev
->dev
->name
);
357 switch (phydev
->speed
) {
359 writel(ZYNQ_GEM_NWCFG_INIT
| ZYNQ_GEM_NWCFG_SPEED1000
,
361 clk_rate
= ZYNQ_GEM_FREQUENCY_1000
;
364 clrsetbits_le32(®s
->nwcfg
, ZYNQ_GEM_NWCFG_SPEED1000
,
365 ZYNQ_GEM_NWCFG_INIT
| ZYNQ_GEM_NWCFG_SPEED100
);
366 clk_rate
= ZYNQ_GEM_FREQUENCY_100
;
369 clk_rate
= ZYNQ_GEM_FREQUENCY_10
;
373 /* Change the rclk and clk only not using EMIO interface */
375 zynq_slcr_gem_clk_setup(dev
->iobase
!=
376 ZYNQ_GEM_BASEADDR0
, clk_rate
);
378 setbits_le32(®s
->nwctrl
, ZYNQ_GEM_NWCTRL_RXEN_MASK
|
379 ZYNQ_GEM_NWCTRL_TXEN_MASK
);
384 static int zynq_gem_send(struct eth_device
*dev
, void *ptr
, int len
)
387 struct zynq_gem_priv
*priv
= dev
->priv
;
388 struct zynq_gem_regs
*regs
= (struct zynq_gem_regs
*)dev
->iobase
;
391 writel((u32
)priv
->tx_bd
, ®s
->txqbase
);
394 memset(priv
->tx_bd
, 0, sizeof(struct emac_bd
));
396 priv
->tx_bd
->addr
= (u32
)ptr
;
397 priv
->tx_bd
->status
= (len
& ZYNQ_GEM_TXBUF_FRMLEN_MASK
) |
398 ZYNQ_GEM_TXBUF_LAST_MASK
;
401 addr
&= ~(ARCH_DMA_MINALIGN
- 1);
402 size
= roundup(len
, ARCH_DMA_MINALIGN
);
403 flush_dcache_range(addr
, addr
+ size
);
407 setbits_le32(®s
->nwctrl
, ZYNQ_GEM_NWCTRL_STARTTX_MASK
);
409 /* Read TX BD status */
410 if (priv
->tx_bd
->status
& ZYNQ_GEM_TXBUF_UNDERRUN
)
411 printf("TX underrun\n");
412 if (priv
->tx_bd
->status
& ZYNQ_GEM_TXBUF_EXHAUSTED
)
413 printf("TX buffers exhausted in mid frame\n");
418 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
419 static int zynq_gem_recv(struct eth_device
*dev
)
422 struct zynq_gem_priv
*priv
= dev
->priv
;
423 struct emac_bd
*current_bd
= &priv
->rx_bd
[priv
->rxbd_current
];
424 struct emac_bd
*first_bd
;
426 if (!(current_bd
->addr
& ZYNQ_GEM_RXBUF_NEW_MASK
))
429 if (!(current_bd
->status
&
430 (ZYNQ_GEM_RXBUF_SOF_MASK
| ZYNQ_GEM_RXBUF_EOF_MASK
))) {
431 printf("GEM: SOF or EOF not set for last buffer received!\n");
435 frame_len
= current_bd
->status
& ZYNQ_GEM_RXBUF_LEN_MASK
;
437 u32 addr
= current_bd
->addr
& ZYNQ_GEM_RXBUF_ADD_MASK
;
438 addr
&= ~(ARCH_DMA_MINALIGN
- 1);
439 u32 size
= roundup(frame_len
, ARCH_DMA_MINALIGN
);
440 invalidate_dcache_range(addr
, addr
+ size
);
442 net_process_received_packet((u8
*)addr
, frame_len
);
444 if (current_bd
->status
& ZYNQ_GEM_RXBUF_SOF_MASK
)
445 priv
->rx_first_buf
= priv
->rxbd_current
;
447 current_bd
->addr
&= ~ZYNQ_GEM_RXBUF_NEW_MASK
;
448 current_bd
->status
= 0xF0000000; /* FIXME */
451 if (current_bd
->status
& ZYNQ_GEM_RXBUF_EOF_MASK
) {
452 first_bd
= &priv
->rx_bd
[priv
->rx_first_buf
];
453 first_bd
->addr
&= ~ZYNQ_GEM_RXBUF_NEW_MASK
;
454 first_bd
->status
= 0xF0000000;
457 if ((++priv
->rxbd_current
) >= RX_BUF
)
458 priv
->rxbd_current
= 0;
464 static void zynq_gem_halt(struct eth_device
*dev
)
466 struct zynq_gem_regs
*regs
= (struct zynq_gem_regs
*)dev
->iobase
;
468 clrsetbits_le32(®s
->nwctrl
, ZYNQ_GEM_NWCTRL_RXEN_MASK
|
469 ZYNQ_GEM_NWCTRL_TXEN_MASK
, 0);
472 static int zynq_gem_miiphyread(const char *devname
, uchar addr
,
473 uchar reg
, ushort
*val
)
475 struct eth_device
*dev
= eth_get_dev();
478 ret
= phyread(dev
, addr
, reg
, val
);
479 debug("%s 0x%x, 0x%x, 0x%x\n", __func__
, addr
, reg
, *val
);
483 static int zynq_gem_miiphy_write(const char *devname
, uchar addr
,
484 uchar reg
, ushort val
)
486 struct eth_device
*dev
= eth_get_dev();
488 debug("%s 0x%x, 0x%x, 0x%x\n", __func__
, addr
, reg
, val
);
489 return phywrite(dev
, addr
, reg
, val
);
492 int zynq_gem_initialize(bd_t
*bis
, phys_addr_t base_addr
,
493 int phy_addr
, u32 emio
)
495 struct eth_device
*dev
;
496 struct zynq_gem_priv
*priv
;
499 dev
= calloc(1, sizeof(*dev
));
503 dev
->priv
= calloc(1, sizeof(struct zynq_gem_priv
));
504 if (dev
->priv
== NULL
) {
510 /* Align rxbuffers to ARCH_DMA_MINALIGN */
511 priv
->rxbuffers
= memalign(ARCH_DMA_MINALIGN
, RX_BUF
* PKTSIZE_ALIGN
);
512 memset(priv
->rxbuffers
, 0, RX_BUF
* PKTSIZE_ALIGN
);
514 /* Align bd_space to 1MB */
515 bd_space
= memalign(1 << MMU_SECTION_SHIFT
, BD_SPACE
);
516 mmu_set_region_dcache_behaviour((phys_addr_t
)bd_space
,
517 BD_SPACE
, DCACHE_OFF
);
519 /* Initialize the bd spaces for tx and rx bd's */
520 priv
->tx_bd
= (struct emac_bd
*)bd_space
;
521 priv
->rx_bd
= (struct emac_bd
*)((u32
)bd_space
+ BD_SEPRN_SPACE
);
523 priv
->phyaddr
= phy_addr
;
526 sprintf(dev
->name
, "Gem.%lx", base_addr
);
528 dev
->iobase
= base_addr
;
530 dev
->init
= zynq_gem_init
;
531 dev
->halt
= zynq_gem_halt
;
532 dev
->send
= zynq_gem_send
;
533 dev
->recv
= zynq_gem_recv
;
534 dev
->write_hwaddr
= zynq_gem_setup_mac
;
538 miiphy_register(dev
->name
, zynq_gem_miiphyread
, zynq_gem_miiphy_write
);
539 priv
->bus
= miiphy_get_dev_by_name(dev
->name
);
544 #ifdef CONFIG_OF_CONTROL
545 int zynq_gem_of_init(const void *blob
)
551 debug("ZYNQ GEM: Initialization\n");
554 offset
= fdt_node_offset_by_compatible(blob
, offset
,
555 "xlnx,ps7-ethernet-1.00.a");
557 reg
= fdtdec_get_addr(blob
, offset
, "reg");
558 if (reg
!= FDT_ADDR_T_NONE
) {
559 offset
= fdtdec_lookup_phandle(blob
, offset
,
562 phy_reg
= fdtdec_get_addr(blob
, offset
,
567 debug("ZYNQ GEM: addr %x, phyaddr %x\n",
570 ret
|= zynq_gem_initialize(NULL
, reg
,
574 debug("ZYNQ GEM: Can't get base address\n");
578 } while (offset
!= -1);