drivers/net/zynq_gem.c

   1 /*
   2  * (C) Copyright 2011 Michal Simek
   3  *
   4  * Michal SIMEK <monstr@monstr.eu>
   5  *
   6  * Based on Xilinx gmac driver:
   7  * (C) Copyright 2011 Xilinx
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <net.h>
  14 #include <netdev.h>
  15 #include <config.h>
  16 #include <fdtdec.h>
  17 #include <libfdt.h>
  18 #include <malloc.h>
  19 #include <asm/io.h>
  20 #include <phy.h>
  21 #include <miiphy.h>
  22 #include <watchdog.h>
  23 #include <asm/arch/hardware.h>
  24 #include <asm/arch/sys_proto.h>
  25
  26 #if !defined(CONFIG_PHYLIB)
  27 # error XILINX_GEM_ETHERNET requires PHYLIB
  28 #endif
  29
  30 /* Bit/mask specification */
  31 #define ZYNQ_GEM_PHYMNTNC_OP_MASK       0x40020000 /* operation mask bits */
  32 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK     0x20000000 /* read operation */
  33 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK     0x10000000 /* write operation */
  34 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK      23 /* Shift bits for PHYAD */
  35 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK      18 /* Shift bits for PHREG */
  36
  37 #define ZYNQ_GEM_RXBUF_EOF_MASK         0x00008000 /* End of frame. */
  38 #define ZYNQ_GEM_RXBUF_SOF_MASK         0x00004000 /* Start of frame. */
  39 #define ZYNQ_GEM_RXBUF_LEN_MASK         0x00003FFF /* Mask for length field */
  40
  41 #define ZYNQ_GEM_RXBUF_WRAP_MASK        0x00000002 /* Wrap bit, last BD */
  42 #define ZYNQ_GEM_RXBUF_NEW_MASK         0x00000001 /* Used bit.. */
  43 #define ZYNQ_GEM_RXBUF_ADD_MASK         0xFFFFFFFC /* Mask for address */
  44
  45 /* Wrap bit, last descriptor */
  46 #define ZYNQ_GEM_TXBUF_WRAP_MASK        0x40000000
  47 #define ZYNQ_GEM_TXBUF_LAST_MASK        0x00008000 /* Last buffer */
  48
  49 #define ZYNQ_GEM_NWCTRL_TXEN_MASK       0x00000008 /* Enable transmit */
  50 #define ZYNQ_GEM_NWCTRL_RXEN_MASK       0x00000004 /* Enable receive */
  51 #define ZYNQ_GEM_NWCTRL_MDEN_MASK       0x00000010 /* Enable MDIO port */
  52 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK    0x00000200 /* Start tx (tx_go) */
  53
  54 #define ZYNQ_GEM_NWCFG_SPEED100         0x000000001 /* 100 Mbps operation */
  55 #define ZYNQ_GEM_NWCFG_SPEED1000        0x000000400 /* 1Gbps operation */
  56 #define ZYNQ_GEM_NWCFG_FDEN             0x000000002 /* Full Duplex mode */
  57 #define ZYNQ_GEM_NWCFG_FSREM            0x000020000 /* FCS removal */
  58 #define ZYNQ_GEM_NWCFG_MDCCLKDIV        0x000080000 /* Div pclk by 32, 80MHz */
  59 #define ZYNQ_GEM_NWCFG_MDCCLKDIV2       0x0000c0000 /* Div pclk by 48, 120MHz */
  60
  61 #define ZYNQ_GEM_NWCFG_INIT             (ZYNQ_GEM_NWCFG_FDEN | \
  62                                         ZYNQ_GEM_NWCFG_FSREM | \
  63                                         ZYNQ_GEM_NWCFG_MDCCLKDIV)
  64
  65 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK     0x00000004 /* PHY management idle */
  66
  67 #define ZYNQ_GEM_DMACR_BLENGTH          0x00000004 /* INCR4 AHB bursts */
  68 /* Use full configured addressable space (8 Kb) */
  69 #define ZYNQ_GEM_DMACR_RXSIZE           0x00000300
  70 /* Use full configured addressable space (4 Kb) */
  71 #define ZYNQ_GEM_DMACR_TXSIZE           0x00000400
  72 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
  73 #define ZYNQ_GEM_DMACR_RXBUF            0x00180000
  74
  75 #define ZYNQ_GEM_DMACR_INIT             (ZYNQ_GEM_DMACR_BLENGTH | \
  76                                         ZYNQ_GEM_DMACR_RXSIZE | \
  77                                         ZYNQ_GEM_DMACR_TXSIZE | \
  78                                         ZYNQ_GEM_DMACR_RXBUF)
  79
  80 /* Use MII register 1 (MII status register) to detect PHY */
  81 #define PHY_DETECT_REG  1
  82
  83 /* Mask used to verify certain PHY features (or register contents)
  84  * in the register above:
  85  *  0x1000: 10Mbps full duplex support
  86  *  0x0800: 10Mbps half duplex support
  87  *  0x0008: Auto-negotiation support
  88  */
  89 #define PHY_DETECT_MASK 0x1808
  90
  91 /* TX BD status masks */
  92 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK      0x000007ff
  93 #define ZYNQ_GEM_TXBUF_EXHAUSTED        0x08000000
  94 #define ZYNQ_GEM_TXBUF_UNDERRUN         0x10000000
  95
  96 /* Clock frequencies for different speeds */
  97 #define ZYNQ_GEM_FREQUENCY_10   2500000UL
  98 #define ZYNQ_GEM_FREQUENCY_100  25000000UL
  99 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL
 100
 101 /* Device registers */
 102 struct zynq_gem_regs {
 103         u32 nwctrl; /* Network Control reg */
 104         u32 nwcfg; /* Network Config reg */
 105         u32 nwsr; /* Network Status reg */
 106         u32 reserved1;
 107         u32 dmacr; /* DMA Control reg */
 108         u32 txsr; /* TX Status reg */
 109         u32 rxqbase; /* RX Q Base address reg */
 110         u32 txqbase; /* TX Q Base address reg */
 111         u32 rxsr; /* RX Status reg */
 112         u32 reserved2[2];
 113         u32 idr; /* Interrupt Disable reg */
 114         u32 reserved3;
 115         u32 phymntnc; /* Phy Maintaince reg */
 116         u32 reserved4[18];
 117         u32 hashl; /* Hash Low address reg */
 118         u32 hashh; /* Hash High address reg */
 119 #define LADDR_LOW       0
 120 #define LADDR_HIGH      1
 121         u32 laddr[4][LADDR_HIGH + 1]; /* Specific1 addr low/high reg */
 122         u32 match[4]; /* Type ID1 Match reg */
 123         u32 reserved6[18];
 124         u32 stat[44]; /* Octects transmitted Low reg - stat start */
 125 };
 126
 127 /* BD descriptors */
 128 struct emac_bd {
 129         u32 addr; /* Next descriptor pointer */
 130         u32 status;
 131 };
 132
 133 #define RX_BUF 3
 134 /* Page table entries are set to 1MB, or multiples of 1MB
 135  * (not < 1MB). driver uses less bd's so use 1MB bdspace.
 136  */
 137 #define BD_SPACE        0x100000
 138 /* BD separation space */
 139 #define BD_SEPRN_SPACE  64
 140
 141 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
 142 struct zynq_gem_priv {
 143         struct emac_bd *tx_bd;
 144         struct emac_bd *rx_bd;
 145         char *rxbuffers;
 146         u32 rxbd_current;
 147         u32 rx_first_buf;
 148         int phyaddr;
 149         u32 emio;
 150         int init;
 151         struct phy_device *phydev;
 152         struct mii_dev *bus;
 153 };
 154
 155 static inline int mdio_wait(struct eth_device *dev)
 156 {
 157         struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
 158         u32 timeout = 200;
 159
 160         /* Wait till MDIO interface is ready to accept a new transaction. */
 161         while (--timeout) {
 162                 if (readl(&regs->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)
 163                         break;
 164                 WATCHDOG_RESET();
 165         }
 166
 167         if (!timeout) {
 168                 printf("%s: Timeout\n", __func__);
 169                 return 1;
 170         }
 171
 172         return 0;
 173 }
 174
 175 static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum,
 176                                                         u32 op, u16 *data)
 177 {
 178         u32 mgtcr;
 179         struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
 180
 181         if (mdio_wait(dev))
 182                 return 1;
 183
 184         /* Construct mgtcr mask for the operation */
 185         mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
 186                 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
 187                 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
 188
 189         /* Write mgtcr and wait for completion */
 190         writel(mgtcr, &regs->phymntnc);
 191
 192         if (mdio_wait(dev))
 193                 return 1;
 194
 195         if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
 196                 *data = readl(&regs->phymntnc);
 197
 198         return 0;
 199 }
 200
 201 static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val)
 202 {
 203         return phy_setup_op(dev, phy_addr, regnum,
 204                                 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
 205 }
 206
 207 static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data)
 208 {
 209         return phy_setup_op(dev, phy_addr, regnum,
 210                                 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
 211 }
 212
 213 static void phy_detection(struct eth_device *dev)
 214 {
 215         int i;
 216         u16 phyreg;
 217         struct zynq_gem_priv *priv = dev->priv;
 218
 219         if (priv->phyaddr != -1) {
 220                 phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg);
 221                 if ((phyreg != 0xFFFF) &&
 222                     ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
 223                         /* Found a valid PHY address */
 224                         debug("Default phy address %d is valid\n",
 225                               priv->phyaddr);
 226                         return;
 227                 } else {
 228                         debug("PHY address is not setup correctly %d\n",
 229                               priv->phyaddr);
 230                         priv->phyaddr = -1;
 231                 }
 232         }
 233
 234         debug("detecting phy address\n");
 235         if (priv->phyaddr == -1) {
 236                 /* detect the PHY address */
 237                 for (i = 31; i >= 0; i--) {
 238                         phyread(dev, i, PHY_DETECT_REG, &phyreg);
 239                         if ((phyreg != 0xFFFF) &&
 240                             ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
 241                                 /* Found a valid PHY address */
 242                                 priv->phyaddr = i;
 243                                 debug("Found valid phy address, %d\n", i);
 244                                 return;
 245                         }
 246                 }
 247         }
 248         printf("PHY is not detected\n");
 249 }
 250
 251 static int zynq_gem_setup_mac(struct eth_device *dev)
 252 {
 253         u32 i, macaddrlow, macaddrhigh;
 254         struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
 255
 256         /* Set the MAC bits [31:0] in BOT */
 257         macaddrlow = dev->enetaddr[0];
 258         macaddrlow |= dev->enetaddr[1] << 8;
 259         macaddrlow |= dev->enetaddr[2] << 16;
 260         macaddrlow |= dev->enetaddr[3] << 24;
 261
 262         /* Set MAC bits [47:32] in TOP */
 263         macaddrhigh = dev->enetaddr[4];
 264         macaddrhigh |= dev->enetaddr[5] << 8;
 265
 266         for (i = 0; i < 4; i++) {
 267                 writel(0, &regs->laddr[i][LADDR_LOW]);
 268                 writel(0, &regs->laddr[i][LADDR_HIGH]);
 269                 /* Do not use MATCHx register */
 270                 writel(0, &regs->match[i]);
 271         }
 272
 273         writel(macaddrlow, &regs->laddr[0][LADDR_LOW]);
 274         writel(macaddrhigh, &regs->laddr[0][LADDR_HIGH]);
 275
 276         return 0;
 277 }
 278
 279 static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
 280 {
 281         u32 i;
 282         unsigned long clk_rate = 0;
 283         struct phy_device *phydev;
 284         const u32 stat_size = (sizeof(struct zynq_gem_regs) -
 285                                 offsetof(struct zynq_gem_regs, stat)) / 4;
 286         struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
 287         struct zynq_gem_priv *priv = dev->priv;
 288         const u32 supported = SUPPORTED_10baseT_Half |
 289                         SUPPORTED_10baseT_Full |
 290                         SUPPORTED_100baseT_Half |
 291                         SUPPORTED_100baseT_Full |
 292                         SUPPORTED_1000baseT_Half |
 293                         SUPPORTED_1000baseT_Full;
 294
 295         if (!priv->init) {
 296                 /* Disable all interrupts */
 297                 writel(0xFFFFFFFF, &regs->idr);
 298
 299                 /* Disable the receiver & transmitter */
 300                 writel(0, &regs->nwctrl);
 301                 writel(0, &regs->txsr);
 302                 writel(0, &regs->rxsr);
 303                 writel(0, &regs->phymntnc);
 304
 305                 /* Clear the Hash registers for the mac address
 306                  * pointed by AddressPtr
 307                  */
 308                 writel(0x0, &regs->hashl);
 309                 /* Write bits [63:32] in TOP */
 310                 writel(0x0, &regs->hashh);
 311
 312                 /* Clear all counters */
 313                 for (i = 0; i <= stat_size; i++)
 314                         readl(&regs->stat[i]);
 315
 316                 /* Setup RxBD space */
 317                 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
 318
 319                 for (i = 0; i < RX_BUF; i++) {
 320                         priv->rx_bd[i].status = 0xF0000000;
 321                         priv->rx_bd[i].addr =
 322                                         ((u32)(priv->rxbuffers) +
 323                                                         (i * PKTSIZE_ALIGN));
 324                 }
 325                 /* WRAP bit to last BD */
 326                 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
 327                 /* Write RxBDs to IP */
 328                 writel((u32)priv->rx_bd, &regs->rxqbase);
 329
 330                 /* Setup for DMA Configuration register */
 331                 writel(ZYNQ_GEM_DMACR_INIT, &regs->dmacr);
 332
 333                 /* Setup for Network Control register, MDIO, Rx and Tx enable */
 334                 setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
 335
 336                 priv->init++;
 337         }
 338
 339         phy_detection(dev);
 340
 341         /* interface - look at tsec */
 342         phydev = phy_connect(priv->bus, priv->phyaddr, dev,
 343                              PHY_INTERFACE_MODE_MII);
 344
 345         phydev->supported = supported | ADVERTISED_Pause |
 346                             ADVERTISED_Asym_Pause;
 347         phydev->advertising = phydev->supported;
 348         priv->phydev = phydev;
 349         phy_config(phydev);
 350         phy_startup(phydev);
 351
 352         if (!phydev->link) {
 353                 printf("%s: No link.\n", phydev->dev->name);
 354                 return -1;
 355         }
 356
 357         switch (phydev->speed) {
 358         case SPEED_1000:
 359                 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
 360                        &regs->nwcfg);
 361                 clk_rate = ZYNQ_GEM_FREQUENCY_1000;
 362                 break;
 363         case SPEED_100:
 364                 clrsetbits_le32(&regs->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000,
 365                                 ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100);
 366                 clk_rate = ZYNQ_GEM_FREQUENCY_100;
 367                 break;
 368         case SPEED_10:
 369                 clk_rate = ZYNQ_GEM_FREQUENCY_10;
 370                 break;
 371         }
 372
 373         /* Change the rclk and clk only not using EMIO interface */
 374         if (!priv->emio)
 375                 zynq_slcr_gem_clk_setup(dev->iobase !=
 376                                         ZYNQ_GEM_BASEADDR0, clk_rate);
 377
 378         setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
 379                                         ZYNQ_GEM_NWCTRL_TXEN_MASK);
 380
 381         return 0;
 382 }
 383
 384 static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
 385 {
 386         u32 addr, size;
 387         struct zynq_gem_priv *priv = dev->priv;
 388         struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
 389
 390         /* setup BD */
 391         writel((u32)priv->tx_bd, &regs->txqbase);
 392
 393         /* Setup Tx BD */
 394         memset(priv->tx_bd, 0, sizeof(struct emac_bd));
 395
 396         priv->tx_bd->addr = (u32)ptr;
 397         priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
 398                                 ZYNQ_GEM_TXBUF_LAST_MASK;
 399
 400         addr = (u32) ptr;
 401         addr &= ~(ARCH_DMA_MINALIGN - 1);
 402         size = roundup(len, ARCH_DMA_MINALIGN);
 403         flush_dcache_range(addr, addr + size);
 404         barrier();
 405
 406         /* Start transmit */
 407         setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
 408
 409         /* Read TX BD status */
 410         if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_UNDERRUN)
 411                 printf("TX underrun\n");
 412         if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
 413                 printf("TX buffers exhausted in mid frame\n");
 414
 415         return 0;
 416 }
 417
 418 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
 419 static int zynq_gem_recv(struct eth_device *dev)
 420 {
 421         int frame_len;
 422         struct zynq_gem_priv *priv = dev->priv;
 423         struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
 424         struct emac_bd *first_bd;
 425
 426         if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
 427                 return 0;
 428
 429         if (!(current_bd->status &
 430                         (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
 431                 printf("GEM: SOF or EOF not set for last buffer received!\n");
 432                 return 0;
 433         }
 434
 435         frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
 436         if (frame_len) {
 437                 u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
 438                 addr &= ~(ARCH_DMA_MINALIGN - 1);
 439                 u32 size = roundup(frame_len, ARCH_DMA_MINALIGN);
 440                 invalidate_dcache_range(addr, addr + size);
 441
 442                 NetReceive((u8 *)addr, frame_len);
 443
 444                 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK)
 445                         priv->rx_first_buf = priv->rxbd_current;
 446                 else {
 447                         current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
 448                         current_bd->status = 0xF0000000; /* FIXME */
 449                 }
 450
 451                 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
 452                         first_bd = &priv->rx_bd[priv->rx_first_buf];
 453                         first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
 454                         first_bd->status = 0xF0000000;
 455                 }
 456
 457                 if ((++priv->rxbd_current) >= RX_BUF)
 458                         priv->rxbd_current = 0;
 459         }
 460
 461         return frame_len;
 462 }
 463
 464 static void zynq_gem_halt(struct eth_device *dev)
 465 {
 466         struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
 467
 468         clrsetbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
 469                                                 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
 470 }
 471
 472 static int zynq_gem_miiphyread(const char *devname, uchar addr,
 473                                                         uchar reg, ushort *val)
 474 {
 475         struct eth_device *dev = eth_get_dev();
 476         int ret;
 477
 478         ret = phyread(dev, addr, reg, val);
 479         debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val);
 480         return ret;
 481 }
 482
 483 static int zynq_gem_miiphy_write(const char *devname, uchar addr,
 484                                                         uchar reg, ushort val)
 485 {
 486         struct eth_device *dev = eth_get_dev();
 487
 488         debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val);
 489         return phywrite(dev, addr, reg, val);
 490 }
 491
 492 int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio)
 493 {
 494         struct eth_device *dev;
 495         struct zynq_gem_priv *priv;
 496         void *bd_space;
 497
 498         dev = calloc(1, sizeof(*dev));
 499         if (dev == NULL)
 500                 return -1;
 501
 502         dev->priv = calloc(1, sizeof(struct zynq_gem_priv));
 503         if (dev->priv == NULL) {
 504                 free(dev);
 505                 return -1;
 506         }
 507         priv = dev->priv;
 508
 509         /* Align rxbuffers to ARCH_DMA_MINALIGN */
 510         priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
 511         memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
 512
 513         /* Align bd_space to 1MB */
 514         bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
 515         mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, DCACHE_OFF);
 516
 517         /* Initialize the bd spaces for tx and rx bd's */
 518         priv->tx_bd = (struct emac_bd *)bd_space;
 519         priv->rx_bd = (struct emac_bd *)((u32)bd_space + BD_SEPRN_SPACE);
 520
 521         priv->phyaddr = phy_addr;
 522         priv->emio = emio;
 523
 524         sprintf(dev->name, "Gem.%x", base_addr);
 525
 526         dev->iobase = base_addr;
 527
 528         dev->init = zynq_gem_init;
 529         dev->halt = zynq_gem_halt;
 530         dev->send = zynq_gem_send;
 531         dev->recv = zynq_gem_recv;
 532         dev->write_hwaddr = zynq_gem_setup_mac;
 533
 534         eth_register(dev);
 535
 536         miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write);
 537         priv->bus = miiphy_get_dev_by_name(dev->name);
 538
 539         return 1;
 540 }
 541
 542 #ifdef CONFIG_OF_CONTROL
 543 int zynq_gem_of_init(const void *blob)
 544 {
 545         int offset = 0;
 546         u32 ret = 0;
 547         u32 reg, phy_reg;
 548
 549         debug("ZYNQ GEM: Initialization\n");
 550
 551         do {
 552                 offset = fdt_node_offset_by_compatible(blob, offset,
 553                                         "xlnx,ps7-ethernet-1.00.a");
 554                 if (offset != -1) {
 555                         reg = fdtdec_get_addr(blob, offset, "reg");
 556                         if (reg != FDT_ADDR_T_NONE) {
 557                                 offset = fdtdec_lookup_phandle(blob, offset,
 558                                                                "phy-handle");
 559                                 if (offset != -1)
 560                                         phy_reg = fdtdec_get_addr(blob, offset,
 561                                                                   "reg");
 562                                 else
 563                                         phy_reg = 0;
 564
 565                                 debug("ZYNQ GEM: addr %x, phyaddr %x\n",
 566                                       reg, phy_reg);
 567
 568                                 ret |= zynq_gem_initialize(NULL, reg,
 569                                                            phy_reg, 0);
 570
 571                         } else {
 572                                 debug("ZYNQ GEM: Can't get base address\n");
 573                                 return -1;
 574                         }
 575                 }
 576         } while (offset != -1);
 577
 578         return ret;
 579 }
 580 #endif