drivers/net/zynq_gem.c

   1 /*
   2  * (C) Copyright 2011 Michal Simek
   3  *
   4  * Michal SIMEK <monstr@monstr.eu>
   5  *
   6  * Based on Xilinx gmac driver:
   7  * (C) Copyright 2011 Xilinx
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <dm.h>
  14 #include <net.h>
  15 #include <netdev.h>
  16 #include <config.h>
  17 #include <console.h>
  18 #include <malloc.h>
  19 #include <asm/io.h>
  20 #include <phy.h>
  21 #include <miiphy.h>
  22 #include <wait_bit.h>
  23 #include <watchdog.h>
  24 #include <asm/system.h>
  25 #include <asm/arch/hardware.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <asm-generic/errno.h>
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 /* Bit/mask specification */
  32 #define ZYNQ_GEM_PHYMNTNC_OP_MASK       0x40020000 /* operation mask bits */
  33 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK     0x20000000 /* read operation */
  34 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK     0x10000000 /* write operation */
  35 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK      23 /* Shift bits for PHYAD */
  36 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK      18 /* Shift bits for PHREG */
  37
  38 #define ZYNQ_GEM_RXBUF_EOF_MASK         0x00008000 /* End of frame. */
  39 #define ZYNQ_GEM_RXBUF_SOF_MASK         0x00004000 /* Start of frame. */
  40 #define ZYNQ_GEM_RXBUF_LEN_MASK         0x00003FFF /* Mask for length field */
  41
  42 #define ZYNQ_GEM_RXBUF_WRAP_MASK        0x00000002 /* Wrap bit, last BD */
  43 #define ZYNQ_GEM_RXBUF_NEW_MASK         0x00000001 /* Used bit.. */
  44 #define ZYNQ_GEM_RXBUF_ADD_MASK         0xFFFFFFFC /* Mask for address */
  45
  46 /* Wrap bit, last descriptor */
  47 #define ZYNQ_GEM_TXBUF_WRAP_MASK        0x40000000
  48 #define ZYNQ_GEM_TXBUF_LAST_MASK        0x00008000 /* Last buffer */
  49 #define ZYNQ_GEM_TXBUF_USED_MASK        0x80000000 /* Used by Hw */
  50
  51 #define ZYNQ_GEM_NWCTRL_TXEN_MASK       0x00000008 /* Enable transmit */
  52 #define ZYNQ_GEM_NWCTRL_RXEN_MASK       0x00000004 /* Enable receive */
  53 #define ZYNQ_GEM_NWCTRL_MDEN_MASK       0x00000010 /* Enable MDIO port */
  54 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK    0x00000200 /* Start tx (tx_go) */
  55
  56 #define ZYNQ_GEM_NWCFG_SPEED100         0x000000001 /* 100 Mbps operation */
  57 #define ZYNQ_GEM_NWCFG_SPEED1000        0x000000400 /* 1Gbps operation */
  58 #define ZYNQ_GEM_NWCFG_FDEN             0x000000002 /* Full Duplex mode */
  59 #define ZYNQ_GEM_NWCFG_FSREM            0x000020000 /* FCS removal */
  60 #define ZYNQ_GEM_NWCFG_MDCCLKDIV        0x0000c0000 /* Div pclk by 48, max 120MHz */
  61
  62 #ifdef CONFIG_ARM64
  63 # define ZYNQ_GEM_DBUS_WIDTH    (1 << 21) /* 64 bit bus */
  64 #else
  65 # define ZYNQ_GEM_DBUS_WIDTH    (0 << 21) /* 32 bit bus */
  66 #endif
  67
  68 #define ZYNQ_GEM_NWCFG_INIT             (ZYNQ_GEM_DBUS_WIDTH | \
  69                                         ZYNQ_GEM_NWCFG_FDEN | \
  70                                         ZYNQ_GEM_NWCFG_FSREM | \
  71                                         ZYNQ_GEM_NWCFG_MDCCLKDIV)
  72
  73 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK     0x00000004 /* PHY management idle */
  74
  75 #define ZYNQ_GEM_DMACR_BLENGTH          0x00000004 /* INCR4 AHB bursts */
  76 /* Use full configured addressable space (8 Kb) */
  77 #define ZYNQ_GEM_DMACR_RXSIZE           0x00000300
  78 /* Use full configured addressable space (4 Kb) */
  79 #define ZYNQ_GEM_DMACR_TXSIZE           0x00000400
  80 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
  81 #define ZYNQ_GEM_DMACR_RXBUF            0x00180000
  82
  83 #define ZYNQ_GEM_DMACR_INIT             (ZYNQ_GEM_DMACR_BLENGTH | \
  84                                         ZYNQ_GEM_DMACR_RXSIZE | \
  85                                         ZYNQ_GEM_DMACR_TXSIZE | \
  86                                         ZYNQ_GEM_DMACR_RXBUF)
  87
  88 #define ZYNQ_GEM_TSR_DONE               0x00000020 /* Tx done mask */
  89
  90 /* Use MII register 1 (MII status register) to detect PHY */
  91 #define PHY_DETECT_REG  1
  92
  93 /* Mask used to verify certain PHY features (or register contents)
  94  * in the register above:
  95  *  0x1000: 10Mbps full duplex support
  96  *  0x0800: 10Mbps half duplex support
  97  *  0x0008: Auto-negotiation support
  98  */
  99 #define PHY_DETECT_MASK 0x1808
 100
 101 /* TX BD status masks */
 102 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK      0x000007ff
 103 #define ZYNQ_GEM_TXBUF_EXHAUSTED        0x08000000
 104 #define ZYNQ_GEM_TXBUF_UNDERRUN         0x10000000
 105
 106 /* Clock frequencies for different speeds */
 107 #define ZYNQ_GEM_FREQUENCY_10   2500000UL
 108 #define ZYNQ_GEM_FREQUENCY_100  25000000UL
 109 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL
 110
 111 /* Device registers */
 112 struct zynq_gem_regs {
 113         u32 nwctrl; /* 0x0 - Network Control reg */
 114         u32 nwcfg; /* 0x4 - Network Config reg */
 115         u32 nwsr; /* 0x8 - Network Status reg */
 116         u32 reserved1;
 117         u32 dmacr; /* 0x10 - DMA Control reg */
 118         u32 txsr; /* 0x14 - TX Status reg */
 119         u32 rxqbase; /* 0x18 - RX Q Base address reg */
 120         u32 txqbase; /* 0x1c - TX Q Base address reg */
 121         u32 rxsr; /* 0x20 - RX Status reg */
 122         u32 reserved2[2];
 123         u32 idr; /* 0x2c - Interrupt Disable reg */
 124         u32 reserved3;
 125         u32 phymntnc; /* 0x34 - Phy Maintaince reg */
 126         u32 reserved4[18];
 127         u32 hashl; /* 0x80 - Hash Low address reg */
 128         u32 hashh; /* 0x84 - Hash High address reg */
 129 #define LADDR_LOW       0
 130 #define LADDR_HIGH      1
 131         u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
 132         u32 match[4]; /* 0xa8 - Type ID1 Match reg */
 133         u32 reserved6[18];
 134 #define STAT_SIZE       44
 135         u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
 136         u32 reserved7[164];
 137         u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
 138         u32 reserved8[15];
 139         u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
 140 };
 141
 142 /* BD descriptors */
 143 struct emac_bd {
 144         u32 addr; /* Next descriptor pointer */
 145         u32 status;
 146 };
 147
 148 #define RX_BUF 32
 149 /* Page table entries are set to 1MB, or multiples of 1MB
 150  * (not < 1MB). driver uses less bd's so use 1MB bdspace.
 151  */
 152 #define BD_SPACE        0x100000
 153 /* BD separation space */
 154 #define BD_SEPRN_SPACE  (RX_BUF * sizeof(struct emac_bd))
 155
 156 /* Setup the first free TX descriptor */
 157 #define TX_FREE_DESC    2
 158
 159 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
 160 struct zynq_gem_priv {
 161         struct emac_bd *tx_bd;
 162         struct emac_bd *rx_bd;
 163         char *rxbuffers;
 164         u32 rxbd_current;
 165         u32 rx_first_buf;
 166         int phyaddr;
 167         u32 emio;
 168         int init;
 169         struct zynq_gem_regs *iobase;
 170         phy_interface_t interface;
 171         struct phy_device *phydev;
 172         struct mii_dev *bus;
 173 };
 174
 175 static inline int mdio_wait(struct zynq_gem_regs *regs)
 176 {
 177         u32 timeout = 20000;
 178
 179         /* Wait till MDIO interface is ready to accept a new transaction. */
 180         while (--timeout) {
 181                 if (readl(&regs->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)
 182                         break;
 183                 WATCHDOG_RESET();
 184         }
 185
 186         if (!timeout) {
 187                 printf("%s: Timeout\n", __func__);
 188                 return 1;
 189         }
 190
 191         return 0;
 192 }
 193
 194 static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
 195                         u32 op, u16 *data)
 196 {
 197         u32 mgtcr;
 198         struct zynq_gem_regs *regs = priv->iobase;
 199
 200         if (mdio_wait(regs))
 201                 return 1;
 202
 203         /* Construct mgtcr mask for the operation */
 204         mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
 205                 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
 206                 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
 207
 208         /* Write mgtcr and wait for completion */
 209         writel(mgtcr, &regs->phymntnc);
 210
 211         if (mdio_wait(regs))
 212                 return 1;
 213
 214         if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
 215                 *data = readl(&regs->phymntnc);
 216
 217         return 0;
 218 }
 219
 220 static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr,
 221                    u32 regnum, u16 *val)
 222 {
 223         u32 ret;
 224
 225         ret = phy_setup_op(priv, phy_addr, regnum,
 226                            ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
 227
 228         if (!ret)
 229                 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
 230                       phy_addr, regnum, *val);
 231
 232         return ret;
 233 }
 234
 235 static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
 236                     u32 regnum, u16 data)
 237 {
 238         debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
 239               regnum, data);
 240
 241         return phy_setup_op(priv, phy_addr, regnum,
 242                             ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
 243 }
 244
 245 static int phy_detection(struct udevice *dev)
 246 {
 247         int i;
 248         u16 phyreg;
 249         struct zynq_gem_priv *priv = dev->priv;
 250
 251         if (priv->phyaddr != -1) {
 252                 phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg);
 253                 if ((phyreg != 0xFFFF) &&
 254                     ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
 255                         /* Found a valid PHY address */
 256                         debug("Default phy address %d is valid\n",
 257                               priv->phyaddr);
 258                         return 0;
 259                 } else {
 260                         debug("PHY address is not setup correctly %d\n",
 261                               priv->phyaddr);
 262                         priv->phyaddr = -1;
 263                 }
 264         }
 265
 266         debug("detecting phy address\n");
 267         if (priv->phyaddr == -1) {
 268                 /* detect the PHY address */
 269                 for (i = 31; i >= 0; i--) {
 270                         phyread(priv, i, PHY_DETECT_REG, &phyreg);
 271                         if ((phyreg != 0xFFFF) &&
 272                             ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
 273                                 /* Found a valid PHY address */
 274                                 priv->phyaddr = i;
 275                                 debug("Found valid phy address, %d\n", i);
 276                                 return 0;
 277                         }
 278                 }
 279         }
 280         printf("PHY is not detected\n");
 281         return -1;
 282 }
 283
 284 static int zynq_gem_setup_mac(struct udevice *dev)
 285 {
 286         u32 i, macaddrlow, macaddrhigh;
 287         struct eth_pdata *pdata = dev_get_platdata(dev);
 288         struct zynq_gem_priv *priv = dev_get_priv(dev);
 289         struct zynq_gem_regs *regs = priv->iobase;
 290
 291         /* Set the MAC bits [31:0] in BOT */
 292         macaddrlow = pdata->enetaddr[0];
 293         macaddrlow |= pdata->enetaddr[1] << 8;
 294         macaddrlow |= pdata->enetaddr[2] << 16;
 295         macaddrlow |= pdata->enetaddr[3] << 24;
 296
 297         /* Set MAC bits [47:32] in TOP */
 298         macaddrhigh = pdata->enetaddr[4];
 299         macaddrhigh |= pdata->enetaddr[5] << 8;
 300
 301         for (i = 0; i < 4; i++) {
 302                 writel(0, &regs->laddr[i][LADDR_LOW]);
 303                 writel(0, &regs->laddr[i][LADDR_HIGH]);
 304                 /* Do not use MATCHx register */
 305                 writel(0, &regs->match[i]);
 306         }
 307
 308         writel(macaddrlow, &regs->laddr[0][LADDR_LOW]);
 309         writel(macaddrhigh, &regs->laddr[0][LADDR_HIGH]);
 310
 311         return 0;
 312 }
 313
 314 static int zynq_phy_init(struct udevice *dev)
 315 {
 316         int ret;
 317         struct zynq_gem_priv *priv = dev_get_priv(dev);
 318         struct zynq_gem_regs *regs = priv->iobase;
 319         const u32 supported = SUPPORTED_10baseT_Half |
 320                         SUPPORTED_10baseT_Full |
 321                         SUPPORTED_100baseT_Half |
 322                         SUPPORTED_100baseT_Full |
 323                         SUPPORTED_1000baseT_Half |
 324                         SUPPORTED_1000baseT_Full;
 325
 326         /* Enable only MDIO bus */
 327         writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, &regs->nwctrl);
 328
 329         ret = phy_detection(dev);
 330         if (ret) {
 331                 printf("GEM PHY init failed\n");
 332                 return ret;
 333         }
 334
 335         priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
 336                                    priv->interface);
 337         if (!priv->phydev)
 338                 return -ENODEV;
 339
 340         priv->phydev->supported = supported | ADVERTISED_Pause |
 341                                   ADVERTISED_Asym_Pause;
 342         priv->phydev->advertising = priv->phydev->supported;
 343         phy_config(priv->phydev);
 344
 345         return 0;
 346 }
 347
 348 static int zynq_gem_init(struct udevice *dev)
 349 {
 350         u32 i;
 351         unsigned long clk_rate = 0;
 352         struct zynq_gem_priv *priv = dev_get_priv(dev);
 353         struct zynq_gem_regs *regs = priv->iobase;
 354         struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
 355         struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
 356
 357         if (!priv->init) {
 358                 /* Disable all interrupts */
 359                 writel(0xFFFFFFFF, &regs->idr);
 360
 361                 /* Disable the receiver & transmitter */
 362                 writel(0, &regs->nwctrl);
 363                 writel(0, &regs->txsr);
 364                 writel(0, &regs->rxsr);
 365                 writel(0, &regs->phymntnc);
 366
 367                 /* Clear the Hash registers for the mac address
 368                  * pointed by AddressPtr
 369                  */
 370                 writel(0x0, &regs->hashl);
 371                 /* Write bits [63:32] in TOP */
 372                 writel(0x0, &regs->hashh);
 373
 374                 /* Clear all counters */
 375                 for (i = 0; i < STAT_SIZE; i++)
 376                         readl(&regs->stat[i]);
 377
 378                 /* Setup RxBD space */
 379                 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
 380
 381                 for (i = 0; i < RX_BUF; i++) {
 382                         priv->rx_bd[i].status = 0xF0000000;
 383                         priv->rx_bd[i].addr =
 384                                         ((ulong)(priv->rxbuffers) +
 385                                                         (i * PKTSIZE_ALIGN));
 386                 }
 387                 /* WRAP bit to last BD */
 388                 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
 389                 /* Write RxBDs to IP */
 390                 writel((ulong)priv->rx_bd, &regs->rxqbase);
 391
 392                 /* Setup for DMA Configuration register */
 393                 writel(ZYNQ_GEM_DMACR_INIT, &regs->dmacr);
 394
 395                 /* Setup for Network Control register, MDIO, Rx and Tx enable */
 396                 setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
 397
 398                 /* Disable the second priority queue */
 399                 dummy_tx_bd->addr = 0;
 400                 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
 401                                 ZYNQ_GEM_TXBUF_LAST_MASK|
 402                                 ZYNQ_GEM_TXBUF_USED_MASK;
 403
 404                 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
 405                                 ZYNQ_GEM_RXBUF_NEW_MASK;
 406                 dummy_rx_bd->status = 0;
 407                 flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd +
 408                                    sizeof(dummy_tx_bd));
 409                 flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd +
 410                                    sizeof(dummy_rx_bd));
 411
 412                 writel((ulong)dummy_tx_bd, &regs->transmit_q1_ptr);
 413                 writel((ulong)dummy_rx_bd, &regs->receive_q1_ptr);
 414
 415                 priv->init++;
 416         }
 417
 418         phy_startup(priv->phydev);
 419
 420         if (!priv->phydev->link) {
 421                 printf("%s: No link.\n", priv->phydev->dev->name);
 422                 return -1;
 423         }
 424
 425         switch (priv->phydev->speed) {
 426         case SPEED_1000:
 427                 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
 428                        &regs->nwcfg);
 429                 clk_rate = ZYNQ_GEM_FREQUENCY_1000;
 430                 break;
 431         case SPEED_100:
 432                 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100,
 433                        &regs->nwcfg);
 434                 clk_rate = ZYNQ_GEM_FREQUENCY_100;
 435                 break;
 436         case SPEED_10:
 437                 clk_rate = ZYNQ_GEM_FREQUENCY_10;
 438                 break;
 439         }
 440
 441         /* Change the rclk and clk only not using EMIO interface */
 442         if (!priv->emio)
 443                 zynq_slcr_gem_clk_setup((ulong)priv->iobase !=
 444                                         ZYNQ_GEM_BASEADDR0, clk_rate);
 445
 446         setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
 447                                         ZYNQ_GEM_NWCTRL_TXEN_MASK);
 448
 449         return 0;
 450 }
 451
 452 static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
 453 {
 454         u32 addr, size;
 455         struct zynq_gem_priv *priv = dev_get_priv(dev);
 456         struct zynq_gem_regs *regs = priv->iobase;
 457         struct emac_bd *current_bd = &priv->tx_bd[1];
 458
 459         /* Setup Tx BD */
 460         memset(priv->tx_bd, 0, sizeof(struct emac_bd));
 461
 462         priv->tx_bd->addr = (ulong)ptr;
 463         priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
 464                                ZYNQ_GEM_TXBUF_LAST_MASK;
 465         /* Dummy descriptor to mark it as the last in descriptor chain */
 466         current_bd->addr = 0x0;
 467         current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
 468                              ZYNQ_GEM_TXBUF_LAST_MASK|
 469                              ZYNQ_GEM_TXBUF_USED_MASK;
 470
 471         /* setup BD */
 472         writel((ulong)priv->tx_bd, &regs->txqbase);
 473
 474         addr = (ulong) ptr;
 475         addr &= ~(ARCH_DMA_MINALIGN - 1);
 476         size = roundup(len, ARCH_DMA_MINALIGN);
 477         flush_dcache_range(addr, addr + size);
 478
 479         addr = (ulong)priv->rxbuffers;
 480         addr &= ~(ARCH_DMA_MINALIGN - 1);
 481         size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN);
 482         flush_dcache_range(addr, addr + size);
 483         barrier();
 484
 485         /* Start transmit */
 486         setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
 487
 488         /* Read TX BD status */
 489         if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
 490                 printf("TX buffers exhausted in mid frame\n");
 491
 492         return wait_for_bit(__func__, &regs->txsr, ZYNQ_GEM_TSR_DONE,
 493                             true, 20000, true);
 494 }
 495
 496 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
 497 static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
 498 {
 499         int frame_len;
 500         u32 addr;
 501         struct zynq_gem_priv *priv = dev_get_priv(dev);
 502         struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
 503
 504         if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
 505                 return -1;
 506
 507         if (!(current_bd->status &
 508                         (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
 509                 printf("GEM: SOF or EOF not set for last buffer received!\n");
 510                 return -1;
 511         }
 512
 513         frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
 514         if (!frame_len) {
 515                 printf("%s: Zero size packet?\n", __func__);
 516                 return -1;
 517         }
 518
 519         addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
 520         addr &= ~(ARCH_DMA_MINALIGN - 1);
 521         *packetp = (uchar *)(uintptr_t)addr;
 522
 523         return frame_len;
 524 }
 525
 526 static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length)
 527 {
 528         struct zynq_gem_priv *priv = dev_get_priv(dev);
 529         struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
 530         struct emac_bd *first_bd;
 531
 532         if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) {
 533                 priv->rx_first_buf = priv->rxbd_current;
 534         } else {
 535                 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
 536                 current_bd->status = 0xF0000000; /* FIXME */
 537         }
 538
 539         if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
 540                 first_bd = &priv->rx_bd[priv->rx_first_buf];
 541                 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
 542                 first_bd->status = 0xF0000000;
 543         }
 544
 545         if ((++priv->rxbd_current) >= RX_BUF)
 546                 priv->rxbd_current = 0;
 547
 548         return 0;
 549 }
 550
 551 static void zynq_gem_halt(struct udevice *dev)
 552 {
 553         struct zynq_gem_priv *priv = dev_get_priv(dev);
 554         struct zynq_gem_regs *regs = priv->iobase;
 555
 556         clrsetbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
 557                                                 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
 558 }
 559
 560 static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr,
 561                                 int devad, int reg)
 562 {
 563         struct zynq_gem_priv *priv = bus->priv;
 564         int ret;
 565         u16 val;
 566
 567         ret = phyread(priv, addr, reg, &val);
 568         debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret);
 569         return val;
 570 }
 571
 572 static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad,
 573                                  int reg, u16 value)
 574 {
 575         struct zynq_gem_priv *priv = bus->priv;
 576
 577         debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value);
 578         return phywrite(priv, addr, reg, value);
 579 }
 580
 581 static int zynq_gem_probe(struct udevice *dev)
 582 {
 583         void *bd_space;
 584         struct zynq_gem_priv *priv = dev_get_priv(dev);
 585         int ret;
 586
 587         /* Align rxbuffers to ARCH_DMA_MINALIGN */
 588         priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
 589         memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
 590
 591         /* Align bd_space to MMU_SECTION_SHIFT */
 592         bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
 593         mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
 594                                         BD_SPACE, DCACHE_OFF);
 595
 596         /* Initialize the bd spaces for tx and rx bd's */
 597         priv->tx_bd = (struct emac_bd *)bd_space;
 598         priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
 599
 600         priv->bus = mdio_alloc();
 601         priv->bus->read = zynq_gem_miiphy_read;
 602         priv->bus->write = zynq_gem_miiphy_write;
 603         priv->bus->priv = priv;
 604         strcpy(priv->bus->name, "gem");
 605
 606         ret = mdio_register(priv->bus);
 607         if (ret)
 608                 return ret;
 609
 610         zynq_phy_init(dev);
 611
 612         return 0;
 613 }
 614
 615 static int zynq_gem_remove(struct udevice *dev)
 616 {
 617         struct zynq_gem_priv *priv = dev_get_priv(dev);
 618
 619         free(priv->phydev);
 620         mdio_unregister(priv->bus);
 621         mdio_free(priv->bus);
 622
 623         return 0;
 624 }
 625
 626 static const struct eth_ops zynq_gem_ops = {
 627         .start                  = zynq_gem_init,
 628         .send                   = zynq_gem_send,
 629         .recv                   = zynq_gem_recv,
 630         .free_pkt               = zynq_gem_free_pkt,
 631         .stop                   = zynq_gem_halt,
 632         .write_hwaddr           = zynq_gem_setup_mac,
 633 };
 634
 635 static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
 636 {
 637         struct eth_pdata *pdata = dev_get_platdata(dev);
 638         struct zynq_gem_priv *priv = dev_get_priv(dev);
 639         int offset = 0;
 640         const char *phy_mode;
 641
 642         pdata->iobase = (phys_addr_t)dev_get_addr(dev);
 643         priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
 644         /* Hardcode for now */
 645         priv->emio = 0;
 646         priv->phyaddr = -1;
 647
 648         offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
 649                                        "phy-handle");
 650         if (offset > 0)
 651                 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
 652
 653         phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
 654         if (phy_mode)
 655                 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
 656         if (pdata->phy_interface == -1) {
 657                 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
 658                 return -EINVAL;
 659         }
 660         priv->interface = pdata->phy_interface;
 661
 662         printf("ZYNQ GEM: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
 663                priv->phyaddr, phy_string_for_interface(priv->interface));
 664
 665         return 0;
 666 }
 667
 668 static const struct udevice_id zynq_gem_ids[] = {
 669         { .compatible = "cdns,zynqmp-gem" },
 670         { .compatible = "cdns,zynq-gem" },
 671         { .compatible = "cdns,gem" },
 672         { }
 673 };
 674
 675 U_BOOT_DRIVER(zynq_gem) = {
 676         .name   = "zynq_gem",
 677         .id     = UCLASS_ETH,
 678         .of_match = zynq_gem_ids,
 679         .ofdata_to_platdata = zynq_gem_ofdata_to_platdata,
 680         .probe  = zynq_gem_probe,
 681         .remove = zynq_gem_remove,
 682         .ops    = &zynq_gem_ops,
 683         .priv_auto_alloc_size = sizeof(struct zynq_gem_priv),
 684         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
 685 };