drivers/net/zynq_gem.c

   1 /*
   2  * (C) Copyright 2011 Michal Simek
   3  *
   4  * Michal SIMEK <monstr@monstr.eu>
   5  *
   6  * Based on Xilinx gmac driver:
   7  * (C) Copyright 2011 Xilinx
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <dm.h>
  14 #include <net.h>
  15 #include <netdev.h>
  16 #include <config.h>
  17 #include <console.h>
  18 #include <malloc.h>
  19 #include <asm/io.h>
  20 #include <phy.h>
  21 #include <miiphy.h>
  22 #include <wait_bit.h>
  23 #include <watchdog.h>
  24 #include <asm/system.h>
  25 #include <asm/arch/hardware.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <asm-generic/errno.h>
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 /* Bit/mask specification */
  32 #define ZYNQ_GEM_PHYMNTNC_OP_MASK       0x40020000 /* operation mask bits */
  33 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK     0x20000000 /* read operation */
  34 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK     0x10000000 /* write operation */
  35 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK      23 /* Shift bits for PHYAD */
  36 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK      18 /* Shift bits for PHREG */
  37
  38 #define ZYNQ_GEM_RXBUF_EOF_MASK         0x00008000 /* End of frame. */
  39 #define ZYNQ_GEM_RXBUF_SOF_MASK         0x00004000 /* Start of frame. */
  40 #define ZYNQ_GEM_RXBUF_LEN_MASK         0x00003FFF /* Mask for length field */
  41
  42 #define ZYNQ_GEM_RXBUF_WRAP_MASK        0x00000002 /* Wrap bit, last BD */
  43 #define ZYNQ_GEM_RXBUF_NEW_MASK         0x00000001 /* Used bit.. */
  44 #define ZYNQ_GEM_RXBUF_ADD_MASK         0xFFFFFFFC /* Mask for address */
  45
  46 /* Wrap bit, last descriptor */
  47 #define ZYNQ_GEM_TXBUF_WRAP_MASK        0x40000000
  48 #define ZYNQ_GEM_TXBUF_LAST_MASK        0x00008000 /* Last buffer */
  49 #define ZYNQ_GEM_TXBUF_USED_MASK        0x80000000 /* Used by Hw */
  50
  51 #define ZYNQ_GEM_NWCTRL_TXEN_MASK       0x00000008 /* Enable transmit */
  52 #define ZYNQ_GEM_NWCTRL_RXEN_MASK       0x00000004 /* Enable receive */
  53 #define ZYNQ_GEM_NWCTRL_MDEN_MASK       0x00000010 /* Enable MDIO port */
  54 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK    0x00000200 /* Start tx (tx_go) */
  55
  56 #define ZYNQ_GEM_NWCFG_SPEED100         0x000000001 /* 100 Mbps operation */
  57 #define ZYNQ_GEM_NWCFG_SPEED1000        0x000000400 /* 1Gbps operation */
  58 #define ZYNQ_GEM_NWCFG_FDEN             0x000000002 /* Full Duplex mode */
  59 #define ZYNQ_GEM_NWCFG_FSREM            0x000020000 /* FCS removal */
  60 #define ZYNQ_GEM_NWCFG_SGMII_ENBL       0x080000000 /* SGMII Enable */
  61 #define ZYNQ_GEM_NWCFG_PCS_SEL          0x000000800 /* PCS select */
  62 #ifdef CONFIG_ARM64
  63 #define ZYNQ_GEM_NWCFG_MDCCLKDIV        0x000100000 /* Div pclk by 64, max 160MHz */
  64 #else
  65 #define ZYNQ_GEM_NWCFG_MDCCLKDIV        0x0000c0000 /* Div pclk by 48, max 120MHz */
  66 #endif
  67
  68 #ifdef CONFIG_ARM64
  69 # define ZYNQ_GEM_DBUS_WIDTH    (1 << 21) /* 64 bit bus */
  70 #else
  71 # define ZYNQ_GEM_DBUS_WIDTH    (0 << 21) /* 32 bit bus */
  72 #endif
  73
  74 #define ZYNQ_GEM_NWCFG_INIT             (ZYNQ_GEM_DBUS_WIDTH | \
  75                                         ZYNQ_GEM_NWCFG_FDEN | \
  76                                         ZYNQ_GEM_NWCFG_FSREM | \
  77                                         ZYNQ_GEM_NWCFG_MDCCLKDIV)
  78
  79 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK     0x00000004 /* PHY management idle */
  80
  81 #define ZYNQ_GEM_DMACR_BLENGTH          0x00000004 /* INCR4 AHB bursts */
  82 /* Use full configured addressable space (8 Kb) */
  83 #define ZYNQ_GEM_DMACR_RXSIZE           0x00000300
  84 /* Use full configured addressable space (4 Kb) */
  85 #define ZYNQ_GEM_DMACR_TXSIZE           0x00000400
  86 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
  87 #define ZYNQ_GEM_DMACR_RXBUF            0x00180000
  88
  89 #define ZYNQ_GEM_DMACR_INIT             (ZYNQ_GEM_DMACR_BLENGTH | \
  90                                         ZYNQ_GEM_DMACR_RXSIZE | \
  91                                         ZYNQ_GEM_DMACR_TXSIZE | \
  92                                         ZYNQ_GEM_DMACR_RXBUF)
  93
  94 #define ZYNQ_GEM_TSR_DONE               0x00000020 /* Tx done mask */
  95
  96 /* Use MII register 1 (MII status register) to detect PHY */
  97 #define PHY_DETECT_REG  1
  98
  99 /* Mask used to verify certain PHY features (or register contents)
 100  * in the register above:
 101  *  0x1000: 10Mbps full duplex support
 102  *  0x0800: 10Mbps half duplex support
 103  *  0x0008: Auto-negotiation support
 104  */
 105 #define PHY_DETECT_MASK 0x1808
 106
 107 /* TX BD status masks */
 108 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK      0x000007ff
 109 #define ZYNQ_GEM_TXBUF_EXHAUSTED        0x08000000
 110 #define ZYNQ_GEM_TXBUF_UNDERRUN         0x10000000
 111
 112 /* Clock frequencies for different speeds */
 113 #define ZYNQ_GEM_FREQUENCY_10   2500000UL
 114 #define ZYNQ_GEM_FREQUENCY_100  25000000UL
 115 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL
 116
 117 /* Device registers */
 118 struct zynq_gem_regs {
 119         u32 nwctrl; /* 0x0 - Network Control reg */
 120         u32 nwcfg; /* 0x4 - Network Config reg */
 121         u32 nwsr; /* 0x8 - Network Status reg */
 122         u32 reserved1;
 123         u32 dmacr; /* 0x10 - DMA Control reg */
 124         u32 txsr; /* 0x14 - TX Status reg */
 125         u32 rxqbase; /* 0x18 - RX Q Base address reg */
 126         u32 txqbase; /* 0x1c - TX Q Base address reg */
 127         u32 rxsr; /* 0x20 - RX Status reg */
 128         u32 reserved2[2];
 129         u32 idr; /* 0x2c - Interrupt Disable reg */
 130         u32 reserved3;
 131         u32 phymntnc; /* 0x34 - Phy Maintaince reg */
 132         u32 reserved4[18];
 133         u32 hashl; /* 0x80 - Hash Low address reg */
 134         u32 hashh; /* 0x84 - Hash High address reg */
 135 #define LADDR_LOW       0
 136 #define LADDR_HIGH      1
 137         u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
 138         u32 match[4]; /* 0xa8 - Type ID1 Match reg */
 139         u32 reserved6[18];
 140 #define STAT_SIZE       44
 141         u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
 142         u32 reserved7[164];
 143         u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
 144         u32 reserved8[15];
 145         u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
 146 };
 147
 148 /* BD descriptors */
 149 struct emac_bd {
 150         u32 addr; /* Next descriptor pointer */
 151         u32 status;
 152 };
 153
 154 #define RX_BUF 32
 155 /* Page table entries are set to 1MB, or multiples of 1MB
 156  * (not < 1MB). driver uses less bd's so use 1MB bdspace.
 157  */
 158 #define BD_SPACE        0x100000
 159 /* BD separation space */
 160 #define BD_SEPRN_SPACE  (RX_BUF * sizeof(struct emac_bd))
 161
 162 /* Setup the first free TX descriptor */
 163 #define TX_FREE_DESC    2
 164
 165 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
 166 struct zynq_gem_priv {
 167         struct emac_bd *tx_bd;
 168         struct emac_bd *rx_bd;
 169         char *rxbuffers;
 170         u32 rxbd_current;
 171         u32 rx_first_buf;
 172         int phyaddr;
 173         u32 emio;
 174         int init;
 175         struct zynq_gem_regs *iobase;
 176         phy_interface_t interface;
 177         struct phy_device *phydev;
 178         struct mii_dev *bus;
 179 };
 180
 181 static inline int mdio_wait(struct zynq_gem_regs *regs)
 182 {
 183         u32 timeout = 20000;
 184
 185         /* Wait till MDIO interface is ready to accept a new transaction. */
 186         while (--timeout) {
 187                 if (readl(&regs->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)
 188                         break;
 189                 WATCHDOG_RESET();
 190         }
 191
 192         if (!timeout) {
 193                 printf("%s: Timeout\n", __func__);
 194                 return 1;
 195         }
 196
 197         return 0;
 198 }
 199
 200 static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
 201                         u32 op, u16 *data)
 202 {
 203         u32 mgtcr;
 204         struct zynq_gem_regs *regs = priv->iobase;
 205
 206         if (mdio_wait(regs))
 207                 return 1;
 208
 209         /* Construct mgtcr mask for the operation */
 210         mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
 211                 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
 212                 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
 213
 214         /* Write mgtcr and wait for completion */
 215         writel(mgtcr, &regs->phymntnc);
 216
 217         if (mdio_wait(regs))
 218                 return 1;
 219
 220         if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
 221                 *data = readl(&regs->phymntnc);
 222
 223         return 0;
 224 }
 225
 226 static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr,
 227                    u32 regnum, u16 *val)
 228 {
 229         u32 ret;
 230
 231         ret = phy_setup_op(priv, phy_addr, regnum,
 232                            ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
 233
 234         if (!ret)
 235                 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
 236                       phy_addr, regnum, *val);
 237
 238         return ret;
 239 }
 240
 241 static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
 242                     u32 regnum, u16 data)
 243 {
 244         debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
 245               regnum, data);
 246
 247         return phy_setup_op(priv, phy_addr, regnum,
 248                             ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
 249 }
 250
 251 static int phy_detection(struct udevice *dev)
 252 {
 253         int i;
 254         u16 phyreg;
 255         struct zynq_gem_priv *priv = dev->priv;
 256
 257         if (priv->phyaddr != -1) {
 258                 phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg);
 259                 if ((phyreg != 0xFFFF) &&
 260                     ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
 261                         /* Found a valid PHY address */
 262                         debug("Default phy address %d is valid\n",
 263                               priv->phyaddr);
 264                         return 0;
 265                 } else {
 266                         debug("PHY address is not setup correctly %d\n",
 267                               priv->phyaddr);
 268                         priv->phyaddr = -1;
 269                 }
 270         }
 271
 272         debug("detecting phy address\n");
 273         if (priv->phyaddr == -1) {
 274                 /* detect the PHY address */
 275                 for (i = 31; i >= 0; i--) {
 276                         phyread(priv, i, PHY_DETECT_REG, &phyreg);
 277                         if ((phyreg != 0xFFFF) &&
 278                             ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
 279                                 /* Found a valid PHY address */
 280                                 priv->phyaddr = i;
 281                                 debug("Found valid phy address, %d\n", i);
 282                                 return 0;
 283                         }
 284                 }
 285         }
 286         printf("PHY is not detected\n");
 287         return -1;
 288 }
 289
 290 static int zynq_gem_setup_mac(struct udevice *dev)
 291 {
 292         u32 i, macaddrlow, macaddrhigh;
 293         struct eth_pdata *pdata = dev_get_platdata(dev);
 294         struct zynq_gem_priv *priv = dev_get_priv(dev);
 295         struct zynq_gem_regs *regs = priv->iobase;
 296
 297         /* Set the MAC bits [31:0] in BOT */
 298         macaddrlow = pdata->enetaddr[0];
 299         macaddrlow |= pdata->enetaddr[1] << 8;
 300         macaddrlow |= pdata->enetaddr[2] << 16;
 301         macaddrlow |= pdata->enetaddr[3] << 24;
 302
 303         /* Set MAC bits [47:32] in TOP */
 304         macaddrhigh = pdata->enetaddr[4];
 305         macaddrhigh |= pdata->enetaddr[5] << 8;
 306
 307         for (i = 0; i < 4; i++) {
 308                 writel(0, &regs->laddr[i][LADDR_LOW]);
 309                 writel(0, &regs->laddr[i][LADDR_HIGH]);
 310                 /* Do not use MATCHx register */
 311                 writel(0, &regs->match[i]);
 312         }
 313
 314         writel(macaddrlow, &regs->laddr[0][LADDR_LOW]);
 315         writel(macaddrhigh, &regs->laddr[0][LADDR_HIGH]);
 316
 317         return 0;
 318 }
 319
 320 static int zynq_phy_init(struct udevice *dev)
 321 {
 322         int ret;
 323         struct zynq_gem_priv *priv = dev_get_priv(dev);
 324         struct zynq_gem_regs *regs = priv->iobase;
 325         const u32 supported = SUPPORTED_10baseT_Half |
 326                         SUPPORTED_10baseT_Full |
 327                         SUPPORTED_100baseT_Half |
 328                         SUPPORTED_100baseT_Full |
 329                         SUPPORTED_1000baseT_Half |
 330                         SUPPORTED_1000baseT_Full;
 331
 332         /* Enable only MDIO bus */
 333         writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, &regs->nwctrl);
 334
 335         if (priv->interface != PHY_INTERFACE_MODE_SGMII) {
 336                 ret = phy_detection(dev);
 337                 if (ret) {
 338                         printf("GEM PHY init failed\n");
 339                         return ret;
 340                 }
 341         }
 342
 343         priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
 344                                    priv->interface);
 345         if (!priv->phydev)
 346                 return -ENODEV;
 347
 348         priv->phydev->supported = supported | ADVERTISED_Pause |
 349                                   ADVERTISED_Asym_Pause;
 350         priv->phydev->advertising = priv->phydev->supported;
 351         phy_config(priv->phydev);
 352
 353         return 0;
 354 }
 355
 356 static int zynq_gem_init(struct udevice *dev)
 357 {
 358         u32 i, nwconfig;
 359         unsigned long clk_rate = 0;
 360         struct zynq_gem_priv *priv = dev_get_priv(dev);
 361         struct zynq_gem_regs *regs = priv->iobase;
 362         struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
 363         struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
 364
 365         if (!priv->init) {
 366                 /* Disable all interrupts */
 367                 writel(0xFFFFFFFF, &regs->idr);
 368
 369                 /* Disable the receiver & transmitter */
 370                 writel(0, &regs->nwctrl);
 371                 writel(0, &regs->txsr);
 372                 writel(0, &regs->rxsr);
 373                 writel(0, &regs->phymntnc);
 374
 375                 /* Clear the Hash registers for the mac address
 376                  * pointed by AddressPtr
 377                  */
 378                 writel(0x0, &regs->hashl);
 379                 /* Write bits [63:32] in TOP */
 380                 writel(0x0, &regs->hashh);
 381
 382                 /* Clear all counters */
 383                 for (i = 0; i < STAT_SIZE; i++)
 384                         readl(&regs->stat[i]);
 385
 386                 /* Setup RxBD space */
 387                 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
 388
 389                 for (i = 0; i < RX_BUF; i++) {
 390                         priv->rx_bd[i].status = 0xF0000000;
 391                         priv->rx_bd[i].addr =
 392                                         ((ulong)(priv->rxbuffers) +
 393                                                         (i * PKTSIZE_ALIGN));
 394                 }
 395                 /* WRAP bit to last BD */
 396                 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
 397                 /* Write RxBDs to IP */
 398                 writel((ulong)priv->rx_bd, &regs->rxqbase);
 399
 400                 /* Setup for DMA Configuration register */
 401                 writel(ZYNQ_GEM_DMACR_INIT, &regs->dmacr);
 402
 403                 /* Setup for Network Control register, MDIO, Rx and Tx enable */
 404                 setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
 405
 406                 /* Disable the second priority queue */
 407                 dummy_tx_bd->addr = 0;
 408                 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
 409                                 ZYNQ_GEM_TXBUF_LAST_MASK|
 410                                 ZYNQ_GEM_TXBUF_USED_MASK;
 411
 412                 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
 413                                 ZYNQ_GEM_RXBUF_NEW_MASK;
 414                 dummy_rx_bd->status = 0;
 415                 flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd +
 416                                    sizeof(dummy_tx_bd));
 417                 flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd +
 418                                    sizeof(dummy_rx_bd));
 419
 420                 writel((ulong)dummy_tx_bd, &regs->transmit_q1_ptr);
 421                 writel((ulong)dummy_rx_bd, &regs->receive_q1_ptr);
 422
 423                 priv->init++;
 424         }
 425
 426         phy_startup(priv->phydev);
 427
 428         if (!priv->phydev->link) {
 429                 printf("%s: No link.\n", priv->phydev->dev->name);
 430                 return -1;
 431         }
 432
 433         nwconfig = ZYNQ_GEM_NWCFG_INIT;
 434
 435         if (priv->interface == PHY_INTERFACE_MODE_SGMII)
 436                 nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
 437                             ZYNQ_GEM_NWCFG_PCS_SEL;
 438
 439         switch (priv->phydev->speed) {
 440         case SPEED_1000:
 441                 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000,
 442                        &regs->nwcfg);
 443                 clk_rate = ZYNQ_GEM_FREQUENCY_1000;
 444                 break;
 445         case SPEED_100:
 446                 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100,
 447                        &regs->nwcfg);
 448                 clk_rate = ZYNQ_GEM_FREQUENCY_100;
 449                 break;
 450         case SPEED_10:
 451                 clk_rate = ZYNQ_GEM_FREQUENCY_10;
 452                 break;
 453         }
 454
 455         /* Change the rclk and clk only not using EMIO interface */
 456         if (!priv->emio)
 457                 zynq_slcr_gem_clk_setup((ulong)priv->iobase !=
 458                                         ZYNQ_GEM_BASEADDR0, clk_rate);
 459
 460         setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
 461                                         ZYNQ_GEM_NWCTRL_TXEN_MASK);
 462
 463         return 0;
 464 }
 465
 466 static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
 467 {
 468         u32 addr, size;
 469         struct zynq_gem_priv *priv = dev_get_priv(dev);
 470         struct zynq_gem_regs *regs = priv->iobase;
 471         struct emac_bd *current_bd = &priv->tx_bd[1];
 472
 473         /* Setup Tx BD */
 474         memset(priv->tx_bd, 0, sizeof(struct emac_bd));
 475
 476         priv->tx_bd->addr = (ulong)ptr;
 477         priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
 478                                ZYNQ_GEM_TXBUF_LAST_MASK;
 479         /* Dummy descriptor to mark it as the last in descriptor chain */
 480         current_bd->addr = 0x0;
 481         current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
 482                              ZYNQ_GEM_TXBUF_LAST_MASK|
 483                              ZYNQ_GEM_TXBUF_USED_MASK;
 484
 485         /* setup BD */
 486         writel((ulong)priv->tx_bd, &regs->txqbase);
 487
 488         addr = (ulong) ptr;
 489         addr &= ~(ARCH_DMA_MINALIGN - 1);
 490         size = roundup(len, ARCH_DMA_MINALIGN);
 491         flush_dcache_range(addr, addr + size);
 492
 493         addr = (ulong)priv->rxbuffers;
 494         addr &= ~(ARCH_DMA_MINALIGN - 1);
 495         size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN);
 496         flush_dcache_range(addr, addr + size);
 497         barrier();
 498
 499         /* Start transmit */
 500         setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
 501
 502         /* Read TX BD status */
 503         if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
 504                 printf("TX buffers exhausted in mid frame\n");
 505
 506         return wait_for_bit(__func__, &regs->txsr, ZYNQ_GEM_TSR_DONE,
 507                             true, 20000, true);
 508 }
 509
 510 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
 511 static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
 512 {
 513         int frame_len;
 514         u32 addr;
 515         struct zynq_gem_priv *priv = dev_get_priv(dev);
 516         struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
 517
 518         if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
 519                 return -1;
 520
 521         if (!(current_bd->status &
 522                         (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
 523                 printf("GEM: SOF or EOF not set for last buffer received!\n");
 524                 return -1;
 525         }
 526
 527         frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
 528         if (!frame_len) {
 529                 printf("%s: Zero size packet?\n", __func__);
 530                 return -1;
 531         }
 532
 533         addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
 534         addr &= ~(ARCH_DMA_MINALIGN - 1);
 535         *packetp = (uchar *)(uintptr_t)addr;
 536
 537         return frame_len;
 538 }
 539
 540 static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length)
 541 {
 542         struct zynq_gem_priv *priv = dev_get_priv(dev);
 543         struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
 544         struct emac_bd *first_bd;
 545
 546         if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) {
 547                 priv->rx_first_buf = priv->rxbd_current;
 548         } else {
 549                 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
 550                 current_bd->status = 0xF0000000; /* FIXME */
 551         }
 552
 553         if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
 554                 first_bd = &priv->rx_bd[priv->rx_first_buf];
 555                 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
 556                 first_bd->status = 0xF0000000;
 557         }
 558
 559         if ((++priv->rxbd_current) >= RX_BUF)
 560                 priv->rxbd_current = 0;
 561
 562         return 0;
 563 }
 564
 565 static void zynq_gem_halt(struct udevice *dev)
 566 {
 567         struct zynq_gem_priv *priv = dev_get_priv(dev);
 568         struct zynq_gem_regs *regs = priv->iobase;
 569
 570         clrsetbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
 571                                                 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
 572 }
 573
 574 __weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 575 {
 576         return -ENOSYS;
 577 }
 578
 579 static int zynq_gem_read_rom_mac(struct udevice *dev)
 580 {
 581         int retval;
 582         struct eth_pdata *pdata = dev_get_platdata(dev);
 583
 584         retval = zynq_board_read_rom_ethaddr(pdata->enetaddr);
 585         if (retval == -ENOSYS)
 586                 retval = 0;
 587
 588         return retval;
 589 }
 590
 591 static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr,
 592                                 int devad, int reg)
 593 {
 594         struct zynq_gem_priv *priv = bus->priv;
 595         int ret;
 596         u16 val;
 597
 598         ret = phyread(priv, addr, reg, &val);
 599         debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret);
 600         return val;
 601 }
 602
 603 static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad,
 604                                  int reg, u16 value)
 605 {
 606         struct zynq_gem_priv *priv = bus->priv;
 607
 608         debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value);
 609         return phywrite(priv, addr, reg, value);
 610 }
 611
 612 static int zynq_gem_probe(struct udevice *dev)
 613 {
 614         void *bd_space;
 615         struct zynq_gem_priv *priv = dev_get_priv(dev);
 616         int ret;
 617
 618         /* Align rxbuffers to ARCH_DMA_MINALIGN */
 619         priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
 620         memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
 621
 622         /* Align bd_space to MMU_SECTION_SHIFT */
 623         bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
 624         mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
 625                                         BD_SPACE, DCACHE_OFF);
 626
 627         /* Initialize the bd spaces for tx and rx bd's */
 628         priv->tx_bd = (struct emac_bd *)bd_space;
 629         priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
 630
 631         priv->bus = mdio_alloc();
 632         priv->bus->read = zynq_gem_miiphy_read;
 633         priv->bus->write = zynq_gem_miiphy_write;
 634         priv->bus->priv = priv;
 635         strcpy(priv->bus->name, "gem");
 636
 637         ret = mdio_register(priv->bus);
 638         if (ret)
 639                 return ret;
 640
 641         return zynq_phy_init(dev);
 642 }
 643
 644 static int zynq_gem_remove(struct udevice *dev)
 645 {
 646         struct zynq_gem_priv *priv = dev_get_priv(dev);
 647
 648         free(priv->phydev);
 649         mdio_unregister(priv->bus);
 650         mdio_free(priv->bus);
 651
 652         return 0;
 653 }
 654
 655 static const struct eth_ops zynq_gem_ops = {
 656         .start                  = zynq_gem_init,
 657         .send                   = zynq_gem_send,
 658         .recv                   = zynq_gem_recv,
 659         .free_pkt               = zynq_gem_free_pkt,
 660         .stop                   = zynq_gem_halt,
 661         .write_hwaddr           = zynq_gem_setup_mac,
 662         .read_rom_hwaddr        = zynq_gem_read_rom_mac,
 663 };
 664
 665 static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
 666 {
 667         struct eth_pdata *pdata = dev_get_platdata(dev);
 668         struct zynq_gem_priv *priv = dev_get_priv(dev);
 669         int offset = 0;
 670         const char *phy_mode;
 671
 672         pdata->iobase = (phys_addr_t)dev_get_addr(dev);
 673         priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
 674         /* Hardcode for now */
 675         priv->emio = 0;
 676         priv->phyaddr = -1;
 677
 678         offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
 679                                        "phy-handle");
 680         if (offset > 0)
 681                 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
 682
 683         phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
 684         if (phy_mode)
 685                 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
 686         if (pdata->phy_interface == -1) {
 687                 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
 688                 return -EINVAL;
 689         }
 690         priv->interface = pdata->phy_interface;
 691
 692         priv->emio = fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "xlnx,emio");
 693
 694         printf("ZYNQ GEM: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
 695                priv->phyaddr, phy_string_for_interface(priv->interface));
 696
 697         return 0;
 698 }
 699
 700 static const struct udevice_id zynq_gem_ids[] = {
 701         { .compatible = "cdns,zynqmp-gem" },
 702         { .compatible = "cdns,zynq-gem" },
 703         { .compatible = "cdns,gem" },
 704         { }
 705 };
 706
 707 U_BOOT_DRIVER(zynq_gem) = {
 708         .name   = "zynq_gem",
 709         .id     = UCLASS_ETH,
 710         .of_match = zynq_gem_ids,
 711         .ofdata_to_platdata = zynq_gem_ofdata_to_platdata,
 712         .probe  = zynq_gem_probe,
 713         .remove = zynq_gem_remove,
 714         .ops    = &zynq_gem_ops,
 715         .priv_auto_alloc_size = sizeof(struct zynq_gem_priv),
 716         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
 717 };