1 // SPDX-License-Identifier: GPL-2.0
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
8 #include <linux/async.h>
9 #include <linux/blkdev.h>
10 #include <linux/blk-mq.h>
11 #include <linux/blk-mq-pci.h>
12 #include <linux/dmi.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/once.h>
20 #include <linux/pci.h>
21 #include <linux/suspend.h>
22 #include <linux/t10-pi.h>
23 #include <linux/types.h>
24 #include <linux/io-64-nonatomic-lo-hi.h>
25 #include <linux/sed-opal.h>
26 #include <linux/pci-p2pdma.h>
31 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
32 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
34 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
37 * These can be higher, but we need to ensure that any command doesn't
38 * require an sg allocation that needs more than a page of data.
40 #define NVME_MAX_KB_SZ 4096
41 #define NVME_MAX_SEGS 127
43 static int use_threaded_interrupts
;
44 module_param(use_threaded_interrupts
, int, 0);
46 static bool use_cmb_sqes
= true;
47 module_param(use_cmb_sqes
, bool, 0444);
48 MODULE_PARM_DESC(use_cmb_sqes
, "use controller's memory buffer for I/O SQes");
50 static unsigned int max_host_mem_size_mb
= 128;
51 module_param(max_host_mem_size_mb
, uint
, 0444);
52 MODULE_PARM_DESC(max_host_mem_size_mb
,
53 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
55 static unsigned int sgl_threshold
= SZ_32K
;
56 module_param(sgl_threshold
, uint
, 0644);
57 MODULE_PARM_DESC(sgl_threshold
,
58 "Use SGLs when average request segment size is larger or equal to "
59 "this size. Use 0 to disable SGLs.");
61 static int io_queue_depth_set(const char *val
, const struct kernel_param
*kp
);
62 static const struct kernel_param_ops io_queue_depth_ops
= {
63 .set
= io_queue_depth_set
,
67 static int io_queue_depth
= 1024;
68 module_param_cb(io_queue_depth
, &io_queue_depth_ops
, &io_queue_depth
, 0644);
69 MODULE_PARM_DESC(io_queue_depth
, "set io queue depth, should >= 2");
71 static unsigned int write_queues
;
72 module_param(write_queues
, uint
, 0644);
73 MODULE_PARM_DESC(write_queues
,
74 "Number of queues to use for writes. If not set, reads and writes "
75 "will share a queue set.");
77 static unsigned int poll_queues
;
78 module_param(poll_queues
, uint
, 0644);
79 MODULE_PARM_DESC(poll_queues
, "Number of queues to use for polled IO.");
84 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
);
85 static bool __nvme_disable_io_queues(struct nvme_dev
*dev
, u8 opcode
);
88 * Represents an NVM Express device. Each nvme_dev is a PCI function.
91 struct nvme_queue
*queues
;
92 struct blk_mq_tag_set tagset
;
93 struct blk_mq_tag_set admin_tagset
;
96 struct dma_pool
*prp_page_pool
;
97 struct dma_pool
*prp_small_pool
;
98 unsigned online_queues
;
100 unsigned io_queues
[HCTX_MAX_TYPES
];
101 unsigned int num_vecs
;
106 unsigned long bar_mapped_size
;
107 struct work_struct remove_work
;
108 struct mutex shutdown_lock
;
114 struct nvme_ctrl ctrl
;
117 mempool_t
*iod_mempool
;
119 /* shadow doorbell buffer support: */
121 dma_addr_t dbbuf_dbs_dma_addr
;
123 dma_addr_t dbbuf_eis_dma_addr
;
125 /* host memory buffer support: */
127 u32 nr_host_mem_descs
;
128 dma_addr_t host_mem_descs_dma
;
129 struct nvme_host_mem_buf_desc
*host_mem_descs
;
130 void **host_mem_desc_bufs
;
133 static int io_queue_depth_set(const char *val
, const struct kernel_param
*kp
)
137 ret
= kstrtoint(val
, 10, &n
);
138 if (ret
!= 0 || n
< 2)
141 return param_set_int(val
, kp
);
144 static inline unsigned int sq_idx(unsigned int qid
, u32 stride
)
146 return qid
* 2 * stride
;
149 static inline unsigned int cq_idx(unsigned int qid
, u32 stride
)
151 return (qid
* 2 + 1) * stride
;
154 static inline struct nvme_dev
*to_nvme_dev(struct nvme_ctrl
*ctrl
)
156 return container_of(ctrl
, struct nvme_dev
, ctrl
);
160 * An NVM Express queue. Each device has at least two (one for admin
161 * commands and one for I/O commands).
164 struct nvme_dev
*dev
;
167 /* only used for poll queues: */
168 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp
;
169 volatile struct nvme_completion
*cqes
;
170 dma_addr_t sq_dma_addr
;
171 dma_addr_t cq_dma_addr
;
182 #define NVMEQ_ENABLED 0
183 #define NVMEQ_SQ_CMB 1
184 #define NVMEQ_DELETE_ERROR 2
185 #define NVMEQ_POLLED 3
190 struct completion delete_done
;
194 * The nvme_iod describes the data in an I/O.
196 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
197 * to the actual struct scatterlist.
200 struct nvme_request req
;
201 struct nvme_queue
*nvmeq
;
204 int npages
; /* In the PRP list. 0 means small pool in use */
205 int nents
; /* Used in scatterlist */
206 dma_addr_t first_dma
;
207 unsigned int dma_len
; /* length of single DMA segment mapping */
209 struct scatterlist
*sg
;
212 static unsigned int max_io_queues(void)
214 return num_possible_cpus() + write_queues
+ poll_queues
;
217 static unsigned int max_queue_count(void)
219 /* IO queues + admin queue */
220 return 1 + max_io_queues();
223 static inline unsigned int nvme_dbbuf_size(u32 stride
)
225 return (max_queue_count() * 8 * stride
);
228 static int nvme_dbbuf_dma_alloc(struct nvme_dev
*dev
)
230 unsigned int mem_size
= nvme_dbbuf_size(dev
->db_stride
);
235 dev
->dbbuf_dbs
= dma_alloc_coherent(dev
->dev
, mem_size
,
236 &dev
->dbbuf_dbs_dma_addr
,
240 dev
->dbbuf_eis
= dma_alloc_coherent(dev
->dev
, mem_size
,
241 &dev
->dbbuf_eis_dma_addr
,
243 if (!dev
->dbbuf_eis
) {
244 dma_free_coherent(dev
->dev
, mem_size
,
245 dev
->dbbuf_dbs
, dev
->dbbuf_dbs_dma_addr
);
246 dev
->dbbuf_dbs
= NULL
;
253 static void nvme_dbbuf_dma_free(struct nvme_dev
*dev
)
255 unsigned int mem_size
= nvme_dbbuf_size(dev
->db_stride
);
257 if (dev
->dbbuf_dbs
) {
258 dma_free_coherent(dev
->dev
, mem_size
,
259 dev
->dbbuf_dbs
, dev
->dbbuf_dbs_dma_addr
);
260 dev
->dbbuf_dbs
= NULL
;
262 if (dev
->dbbuf_eis
) {
263 dma_free_coherent(dev
->dev
, mem_size
,
264 dev
->dbbuf_eis
, dev
->dbbuf_eis_dma_addr
);
265 dev
->dbbuf_eis
= NULL
;
269 static void nvme_dbbuf_init(struct nvme_dev
*dev
,
270 struct nvme_queue
*nvmeq
, int qid
)
272 if (!dev
->dbbuf_dbs
|| !qid
)
275 nvmeq
->dbbuf_sq_db
= &dev
->dbbuf_dbs
[sq_idx(qid
, dev
->db_stride
)];
276 nvmeq
->dbbuf_cq_db
= &dev
->dbbuf_dbs
[cq_idx(qid
, dev
->db_stride
)];
277 nvmeq
->dbbuf_sq_ei
= &dev
->dbbuf_eis
[sq_idx(qid
, dev
->db_stride
)];
278 nvmeq
->dbbuf_cq_ei
= &dev
->dbbuf_eis
[cq_idx(qid
, dev
->db_stride
)];
281 static void nvme_dbbuf_set(struct nvme_dev
*dev
)
283 struct nvme_command c
;
288 memset(&c
, 0, sizeof(c
));
289 c
.dbbuf
.opcode
= nvme_admin_dbbuf
;
290 c
.dbbuf
.prp1
= cpu_to_le64(dev
->dbbuf_dbs_dma_addr
);
291 c
.dbbuf
.prp2
= cpu_to_le64(dev
->dbbuf_eis_dma_addr
);
293 if (nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0)) {
294 dev_warn(dev
->ctrl
.device
, "unable to set dbbuf\n");
295 /* Free memory and continue on */
296 nvme_dbbuf_dma_free(dev
);
300 static inline int nvme_dbbuf_need_event(u16 event_idx
, u16 new_idx
, u16 old
)
302 return (u16
)(new_idx
- event_idx
- 1) < (u16
)(new_idx
- old
);
305 /* Update dbbuf and return true if an MMIO is required */
306 static bool nvme_dbbuf_update_and_check_event(u16 value
, u32
*dbbuf_db
,
307 volatile u32
*dbbuf_ei
)
313 * Ensure that the queue is written before updating
314 * the doorbell in memory
318 old_value
= *dbbuf_db
;
322 * Ensure that the doorbell is updated before reading the event
323 * index from memory. The controller needs to provide similar
324 * ordering to ensure the envent index is updated before reading
329 if (!nvme_dbbuf_need_event(*dbbuf_ei
, value
, old_value
))
337 * Will slightly overestimate the number of pages needed. This is OK
338 * as it only leads to a small amount of wasted memory for the lifetime of
341 static int nvme_npages(unsigned size
, struct nvme_dev
*dev
)
343 unsigned nprps
= DIV_ROUND_UP(size
+ dev
->ctrl
.page_size
,
344 dev
->ctrl
.page_size
);
345 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
349 * Calculates the number of pages needed for the SGL segments. For example a 4k
350 * page can accommodate 256 SGL descriptors.
352 static int nvme_pci_npages_sgl(unsigned int num_seg
)
354 return DIV_ROUND_UP(num_seg
* sizeof(struct nvme_sgl_desc
), PAGE_SIZE
);
357 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev
*dev
,
358 unsigned int size
, unsigned int nseg
, bool use_sgl
)
363 alloc_size
= sizeof(__le64
*) * nvme_pci_npages_sgl(nseg
);
365 alloc_size
= sizeof(__le64
*) * nvme_npages(size
, dev
);
367 return alloc_size
+ sizeof(struct scatterlist
) * nseg
;
370 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
371 unsigned int hctx_idx
)
373 struct nvme_dev
*dev
= data
;
374 struct nvme_queue
*nvmeq
= &dev
->queues
[0];
376 WARN_ON(hctx_idx
!= 0);
377 WARN_ON(dev
->admin_tagset
.tags
[0] != hctx
->tags
);
379 hctx
->driver_data
= nvmeq
;
383 static int nvme_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
384 unsigned int hctx_idx
)
386 struct nvme_dev
*dev
= data
;
387 struct nvme_queue
*nvmeq
= &dev
->queues
[hctx_idx
+ 1];
389 WARN_ON(dev
->tagset
.tags
[hctx_idx
] != hctx
->tags
);
390 hctx
->driver_data
= nvmeq
;
394 static int nvme_init_request(struct blk_mq_tag_set
*set
, struct request
*req
,
395 unsigned int hctx_idx
, unsigned int numa_node
)
397 struct nvme_dev
*dev
= set
->driver_data
;
398 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
399 int queue_idx
= (set
== &dev
->tagset
) ? hctx_idx
+ 1 : 0;
400 struct nvme_queue
*nvmeq
= &dev
->queues
[queue_idx
];
405 nvme_req(req
)->ctrl
= &dev
->ctrl
;
409 static int queue_irq_offset(struct nvme_dev
*dev
)
411 /* if we have more than 1 vec, admin queue offsets us by 1 */
412 if (dev
->num_vecs
> 1)
418 static int nvme_pci_map_queues(struct blk_mq_tag_set
*set
)
420 struct nvme_dev
*dev
= set
->driver_data
;
423 offset
= queue_irq_offset(dev
);
424 for (i
= 0, qoff
= 0; i
< set
->nr_maps
; i
++) {
425 struct blk_mq_queue_map
*map
= &set
->map
[i
];
427 map
->nr_queues
= dev
->io_queues
[i
];
428 if (!map
->nr_queues
) {
429 BUG_ON(i
== HCTX_TYPE_DEFAULT
);
434 * The poll queue(s) doesn't have an IRQ (and hence IRQ
435 * affinity), so use the regular blk-mq cpu mapping
437 map
->queue_offset
= qoff
;
438 if (i
!= HCTX_TYPE_POLL
&& offset
)
439 blk_mq_pci_map_queues(map
, to_pci_dev(dev
->dev
), offset
);
441 blk_mq_map_queues(map
);
442 qoff
+= map
->nr_queues
;
443 offset
+= map
->nr_queues
;
450 * Write sq tail if we are asked to, or if the next command would wrap.
452 static inline void nvme_write_sq_db(struct nvme_queue
*nvmeq
, bool write_sq
)
455 u16 next_tail
= nvmeq
->sq_tail
+ 1;
457 if (next_tail
== nvmeq
->q_depth
)
459 if (next_tail
!= nvmeq
->last_sq_tail
)
463 if (nvme_dbbuf_update_and_check_event(nvmeq
->sq_tail
,
464 nvmeq
->dbbuf_sq_db
, nvmeq
->dbbuf_sq_ei
))
465 writel(nvmeq
->sq_tail
, nvmeq
->q_db
);
466 nvmeq
->last_sq_tail
= nvmeq
->sq_tail
;
470 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
471 * @nvmeq: The queue to use
472 * @cmd: The command to send
473 * @write_sq: whether to write to the SQ doorbell
475 static void nvme_submit_cmd(struct nvme_queue
*nvmeq
, struct nvme_command
*cmd
,
478 spin_lock(&nvmeq
->sq_lock
);
479 memcpy(nvmeq
->sq_cmds
+ (nvmeq
->sq_tail
<< nvmeq
->sqes
),
481 if (++nvmeq
->sq_tail
== nvmeq
->q_depth
)
483 nvme_write_sq_db(nvmeq
, write_sq
);
484 spin_unlock(&nvmeq
->sq_lock
);
487 static void nvme_commit_rqs(struct blk_mq_hw_ctx
*hctx
)
489 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
491 spin_lock(&nvmeq
->sq_lock
);
492 if (nvmeq
->sq_tail
!= nvmeq
->last_sq_tail
)
493 nvme_write_sq_db(nvmeq
, true);
494 spin_unlock(&nvmeq
->sq_lock
);
497 static void **nvme_pci_iod_list(struct request
*req
)
499 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
500 return (void **)(iod
->sg
+ blk_rq_nr_phys_segments(req
));
503 static inline bool nvme_pci_use_sgls(struct nvme_dev
*dev
, struct request
*req
)
505 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
506 int nseg
= blk_rq_nr_phys_segments(req
);
507 unsigned int avg_seg_size
;
512 avg_seg_size
= DIV_ROUND_UP(blk_rq_payload_bytes(req
), nseg
);
514 if (!(dev
->ctrl
.sgls
& ((1 << 0) | (1 << 1))))
516 if (!iod
->nvmeq
->qid
)
518 if (!sgl_threshold
|| avg_seg_size
< sgl_threshold
)
523 static void nvme_unmap_data(struct nvme_dev
*dev
, struct request
*req
)
525 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
526 const int last_prp
= dev
->ctrl
.page_size
/ sizeof(__le64
) - 1;
527 dma_addr_t dma_addr
= iod
->first_dma
, next_dma_addr
;
531 dma_unmap_page(dev
->dev
, dma_addr
, iod
->dma_len
,
536 WARN_ON_ONCE(!iod
->nents
);
538 if (is_pci_p2pdma_page(sg_page(iod
->sg
)))
539 pci_p2pdma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
,
542 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, rq_dma_dir(req
));
545 if (iod
->npages
== 0)
546 dma_pool_free(dev
->prp_small_pool
, nvme_pci_iod_list(req
)[0],
549 for (i
= 0; i
< iod
->npages
; i
++) {
550 void *addr
= nvme_pci_iod_list(req
)[i
];
553 struct nvme_sgl_desc
*sg_list
= addr
;
556 le64_to_cpu((sg_list
[SGES_PER_PAGE
- 1]).addr
);
558 __le64
*prp_list
= addr
;
560 next_dma_addr
= le64_to_cpu(prp_list
[last_prp
]);
563 dma_pool_free(dev
->prp_page_pool
, addr
, dma_addr
);
564 dma_addr
= next_dma_addr
;
567 mempool_free(iod
->sg
, dev
->iod_mempool
);
570 static void nvme_print_sgl(struct scatterlist
*sgl
, int nents
)
573 struct scatterlist
*sg
;
575 for_each_sg(sgl
, sg
, nents
, i
) {
576 dma_addr_t phys
= sg_phys(sg
);
577 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
578 "dma_address:%pad dma_length:%d\n",
579 i
, &phys
, sg
->offset
, sg
->length
, &sg_dma_address(sg
),
584 static blk_status_t
nvme_pci_setup_prps(struct nvme_dev
*dev
,
585 struct request
*req
, struct nvme_rw_command
*cmnd
)
587 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
588 struct dma_pool
*pool
;
589 int length
= blk_rq_payload_bytes(req
);
590 struct scatterlist
*sg
= iod
->sg
;
591 int dma_len
= sg_dma_len(sg
);
592 u64 dma_addr
= sg_dma_address(sg
);
593 u32 page_size
= dev
->ctrl
.page_size
;
594 int offset
= dma_addr
& (page_size
- 1);
596 void **list
= nvme_pci_iod_list(req
);
600 length
-= (page_size
- offset
);
606 dma_len
-= (page_size
- offset
);
608 dma_addr
+= (page_size
- offset
);
611 dma_addr
= sg_dma_address(sg
);
612 dma_len
= sg_dma_len(sg
);
615 if (length
<= page_size
) {
616 iod
->first_dma
= dma_addr
;
620 nprps
= DIV_ROUND_UP(length
, page_size
);
621 if (nprps
<= (256 / 8)) {
622 pool
= dev
->prp_small_pool
;
625 pool
= dev
->prp_page_pool
;
629 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
631 iod
->first_dma
= dma_addr
;
633 return BLK_STS_RESOURCE
;
636 iod
->first_dma
= prp_dma
;
639 if (i
== page_size
>> 3) {
640 __le64
*old_prp_list
= prp_list
;
641 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
643 return BLK_STS_RESOURCE
;
644 list
[iod
->npages
++] = prp_list
;
645 prp_list
[0] = old_prp_list
[i
- 1];
646 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
649 prp_list
[i
++] = cpu_to_le64(dma_addr
);
650 dma_len
-= page_size
;
651 dma_addr
+= page_size
;
657 if (unlikely(dma_len
< 0))
660 dma_addr
= sg_dma_address(sg
);
661 dma_len
= sg_dma_len(sg
);
665 cmnd
->dptr
.prp1
= cpu_to_le64(sg_dma_address(iod
->sg
));
666 cmnd
->dptr
.prp2
= cpu_to_le64(iod
->first_dma
);
671 WARN(DO_ONCE(nvme_print_sgl
, iod
->sg
, iod
->nents
),
672 "Invalid SGL for payload:%d nents:%d\n",
673 blk_rq_payload_bytes(req
), iod
->nents
);
674 return BLK_STS_IOERR
;
677 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc
*sge
,
678 struct scatterlist
*sg
)
680 sge
->addr
= cpu_to_le64(sg_dma_address(sg
));
681 sge
->length
= cpu_to_le32(sg_dma_len(sg
));
682 sge
->type
= NVME_SGL_FMT_DATA_DESC
<< 4;
685 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc
*sge
,
686 dma_addr_t dma_addr
, int entries
)
688 sge
->addr
= cpu_to_le64(dma_addr
);
689 if (entries
< SGES_PER_PAGE
) {
690 sge
->length
= cpu_to_le32(entries
* sizeof(*sge
));
691 sge
->type
= NVME_SGL_FMT_LAST_SEG_DESC
<< 4;
693 sge
->length
= cpu_to_le32(PAGE_SIZE
);
694 sge
->type
= NVME_SGL_FMT_SEG_DESC
<< 4;
698 static blk_status_t
nvme_pci_setup_sgls(struct nvme_dev
*dev
,
699 struct request
*req
, struct nvme_rw_command
*cmd
, int entries
)
701 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
702 struct dma_pool
*pool
;
703 struct nvme_sgl_desc
*sg_list
;
704 struct scatterlist
*sg
= iod
->sg
;
708 /* setting the transfer type as SGL */
709 cmd
->flags
= NVME_CMD_SGL_METABUF
;
712 nvme_pci_sgl_set_data(&cmd
->dptr
.sgl
, sg
);
716 if (entries
<= (256 / sizeof(struct nvme_sgl_desc
))) {
717 pool
= dev
->prp_small_pool
;
720 pool
= dev
->prp_page_pool
;
724 sg_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &sgl_dma
);
727 return BLK_STS_RESOURCE
;
730 nvme_pci_iod_list(req
)[0] = sg_list
;
731 iod
->first_dma
= sgl_dma
;
733 nvme_pci_sgl_set_seg(&cmd
->dptr
.sgl
, sgl_dma
, entries
);
736 if (i
== SGES_PER_PAGE
) {
737 struct nvme_sgl_desc
*old_sg_desc
= sg_list
;
738 struct nvme_sgl_desc
*link
= &old_sg_desc
[i
- 1];
740 sg_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &sgl_dma
);
742 return BLK_STS_RESOURCE
;
745 nvme_pci_iod_list(req
)[iod
->npages
++] = sg_list
;
746 sg_list
[i
++] = *link
;
747 nvme_pci_sgl_set_seg(link
, sgl_dma
, entries
);
750 nvme_pci_sgl_set_data(&sg_list
[i
++], sg
);
752 } while (--entries
> 0);
757 static blk_status_t
nvme_setup_prp_simple(struct nvme_dev
*dev
,
758 struct request
*req
, struct nvme_rw_command
*cmnd
,
761 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
762 unsigned int offset
= bv
->bv_offset
& (dev
->ctrl
.page_size
- 1);
763 unsigned int first_prp_len
= dev
->ctrl
.page_size
- offset
;
765 iod
->first_dma
= dma_map_bvec(dev
->dev
, bv
, rq_dma_dir(req
), 0);
766 if (dma_mapping_error(dev
->dev
, iod
->first_dma
))
767 return BLK_STS_RESOURCE
;
768 iod
->dma_len
= bv
->bv_len
;
770 cmnd
->dptr
.prp1
= cpu_to_le64(iod
->first_dma
);
771 if (bv
->bv_len
> first_prp_len
)
772 cmnd
->dptr
.prp2
= cpu_to_le64(iod
->first_dma
+ first_prp_len
);
776 static blk_status_t
nvme_setup_sgl_simple(struct nvme_dev
*dev
,
777 struct request
*req
, struct nvme_rw_command
*cmnd
,
780 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
782 iod
->first_dma
= dma_map_bvec(dev
->dev
, bv
, rq_dma_dir(req
), 0);
783 if (dma_mapping_error(dev
->dev
, iod
->first_dma
))
784 return BLK_STS_RESOURCE
;
785 iod
->dma_len
= bv
->bv_len
;
787 cmnd
->flags
= NVME_CMD_SGL_METABUF
;
788 cmnd
->dptr
.sgl
.addr
= cpu_to_le64(iod
->first_dma
);
789 cmnd
->dptr
.sgl
.length
= cpu_to_le32(iod
->dma_len
);
790 cmnd
->dptr
.sgl
.type
= NVME_SGL_FMT_DATA_DESC
<< 4;
794 static blk_status_t
nvme_map_data(struct nvme_dev
*dev
, struct request
*req
,
795 struct nvme_command
*cmnd
)
797 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
798 blk_status_t ret
= BLK_STS_RESOURCE
;
801 if (blk_rq_nr_phys_segments(req
) == 1) {
802 struct bio_vec bv
= req_bvec(req
);
804 if (!is_pci_p2pdma_page(bv
.bv_page
)) {
805 if (bv
.bv_offset
+ bv
.bv_len
<= dev
->ctrl
.page_size
* 2)
806 return nvme_setup_prp_simple(dev
, req
,
809 if (iod
->nvmeq
->qid
&&
810 dev
->ctrl
.sgls
& ((1 << 0) | (1 << 1)))
811 return nvme_setup_sgl_simple(dev
, req
,
817 iod
->sg
= mempool_alloc(dev
->iod_mempool
, GFP_ATOMIC
);
819 return BLK_STS_RESOURCE
;
820 sg_init_table(iod
->sg
, blk_rq_nr_phys_segments(req
));
821 iod
->nents
= blk_rq_map_sg(req
->q
, req
, iod
->sg
);
825 if (is_pci_p2pdma_page(sg_page(iod
->sg
)))
826 nr_mapped
= pci_p2pdma_map_sg_attrs(dev
->dev
, iod
->sg
,
827 iod
->nents
, rq_dma_dir(req
), DMA_ATTR_NO_WARN
);
829 nr_mapped
= dma_map_sg_attrs(dev
->dev
, iod
->sg
, iod
->nents
,
830 rq_dma_dir(req
), DMA_ATTR_NO_WARN
);
834 iod
->use_sgl
= nvme_pci_use_sgls(dev
, req
);
836 ret
= nvme_pci_setup_sgls(dev
, req
, &cmnd
->rw
, nr_mapped
);
838 ret
= nvme_pci_setup_prps(dev
, req
, &cmnd
->rw
);
840 if (ret
!= BLK_STS_OK
)
841 nvme_unmap_data(dev
, req
);
845 static blk_status_t
nvme_map_metadata(struct nvme_dev
*dev
, struct request
*req
,
846 struct nvme_command
*cmnd
)
848 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
850 iod
->meta_dma
= dma_map_bvec(dev
->dev
, rq_integrity_vec(req
),
852 if (dma_mapping_error(dev
->dev
, iod
->meta_dma
))
853 return BLK_STS_IOERR
;
854 cmnd
->rw
.metadata
= cpu_to_le64(iod
->meta_dma
);
859 * NOTE: ns is NULL when called on the admin queue.
861 static blk_status_t
nvme_queue_rq(struct blk_mq_hw_ctx
*hctx
,
862 const struct blk_mq_queue_data
*bd
)
864 struct nvme_ns
*ns
= hctx
->queue
->queuedata
;
865 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
866 struct nvme_dev
*dev
= nvmeq
->dev
;
867 struct request
*req
= bd
->rq
;
868 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
869 struct nvme_command cmnd
;
877 * We should not need to do this, but we're still using this to
878 * ensure we can drain requests on a dying queue.
880 if (unlikely(!test_bit(NVMEQ_ENABLED
, &nvmeq
->flags
)))
881 return BLK_STS_IOERR
;
883 ret
= nvme_setup_cmd(ns
, req
, &cmnd
);
887 if (blk_rq_nr_phys_segments(req
)) {
888 ret
= nvme_map_data(dev
, req
, &cmnd
);
893 if (blk_integrity_rq(req
)) {
894 ret
= nvme_map_metadata(dev
, req
, &cmnd
);
899 blk_mq_start_request(req
);
900 nvme_submit_cmd(nvmeq
, &cmnd
, bd
->last
);
903 nvme_unmap_data(dev
, req
);
905 nvme_cleanup_cmd(req
);
909 static void nvme_pci_complete_rq(struct request
*req
)
911 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
912 struct nvme_dev
*dev
= iod
->nvmeq
->dev
;
914 if (blk_integrity_rq(req
))
915 dma_unmap_page(dev
->dev
, iod
->meta_dma
,
916 rq_integrity_vec(req
)->bv_len
, rq_data_dir(req
));
917 if (blk_rq_nr_phys_segments(req
))
918 nvme_unmap_data(dev
, req
);
919 nvme_complete_rq(req
);
922 /* We read the CQE phase first to check if the rest of the entry is valid */
923 static inline bool nvme_cqe_pending(struct nvme_queue
*nvmeq
)
925 return (le16_to_cpu(nvmeq
->cqes
[nvmeq
->cq_head
].status
) & 1) ==
929 static inline void nvme_ring_cq_doorbell(struct nvme_queue
*nvmeq
)
931 u16 head
= nvmeq
->cq_head
;
933 if (nvme_dbbuf_update_and_check_event(head
, nvmeq
->dbbuf_cq_db
,
935 writel(head
, nvmeq
->q_db
+ nvmeq
->dev
->db_stride
);
938 static inline struct blk_mq_tags
*nvme_queue_tagset(struct nvme_queue
*nvmeq
)
941 return nvmeq
->dev
->admin_tagset
.tags
[0];
942 return nvmeq
->dev
->tagset
.tags
[nvmeq
->qid
- 1];
945 static inline void nvme_handle_cqe(struct nvme_queue
*nvmeq
, u16 idx
)
947 volatile struct nvme_completion
*cqe
= &nvmeq
->cqes
[idx
];
950 if (unlikely(cqe
->command_id
>= nvmeq
->q_depth
)) {
951 dev_warn(nvmeq
->dev
->ctrl
.device
,
952 "invalid id %d completed on queue %d\n",
953 cqe
->command_id
, le16_to_cpu(cqe
->sq_id
));
958 * AEN requests are special as they don't time out and can
959 * survive any kind of queue freeze and often don't respond to
960 * aborts. We don't even bother to allocate a struct request
961 * for them but rather special case them here.
963 if (unlikely(nvme_is_aen_req(nvmeq
->qid
, cqe
->command_id
))) {
964 nvme_complete_async_event(&nvmeq
->dev
->ctrl
,
965 cqe
->status
, &cqe
->result
);
969 req
= blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq
), cqe
->command_id
);
970 trace_nvme_sq(req
, cqe
->sq_head
, nvmeq
->sq_tail
);
971 nvme_end_request(req
, cqe
->status
, cqe
->result
);
974 static inline void nvme_update_cq_head(struct nvme_queue
*nvmeq
)
976 u16 tmp
= nvmeq
->cq_head
+ 1;
978 if (tmp
== nvmeq
->q_depth
) {
980 nvmeq
->cq_phase
^= 1;
982 nvmeq
->cq_head
= tmp
;
986 static inline int nvme_process_cq(struct nvme_queue
*nvmeq
)
990 while (nvme_cqe_pending(nvmeq
)) {
993 * load-load control dependency between phase and the rest of
994 * the cqe requires a full read memory barrier
997 nvme_handle_cqe(nvmeq
, nvmeq
->cq_head
);
998 nvme_update_cq_head(nvmeq
);
1002 nvme_ring_cq_doorbell(nvmeq
);
1006 static irqreturn_t
nvme_irq(int irq
, void *data
)
1008 struct nvme_queue
*nvmeq
= data
;
1009 irqreturn_t ret
= IRQ_NONE
;
1012 * The rmb/wmb pair ensures we see all updates from a previous run of
1013 * the irq handler, even if that was on another CPU.
1016 if (nvme_process_cq(nvmeq
))
1023 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
1025 struct nvme_queue
*nvmeq
= data
;
1026 if (nvme_cqe_pending(nvmeq
))
1027 return IRQ_WAKE_THREAD
;
1032 * Poll for completions for any interrupt driven queue
1033 * Can be called from any context.
1035 static void nvme_poll_irqdisable(struct nvme_queue
*nvmeq
)
1037 struct pci_dev
*pdev
= to_pci_dev(nvmeq
->dev
->dev
);
1039 WARN_ON_ONCE(test_bit(NVMEQ_POLLED
, &nvmeq
->flags
));
1041 disable_irq(pci_irq_vector(pdev
, nvmeq
->cq_vector
));
1042 nvme_process_cq(nvmeq
);
1043 enable_irq(pci_irq_vector(pdev
, nvmeq
->cq_vector
));
1046 static int nvme_poll(struct blk_mq_hw_ctx
*hctx
)
1048 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
1051 if (!nvme_cqe_pending(nvmeq
))
1054 spin_lock(&nvmeq
->cq_poll_lock
);
1055 found
= nvme_process_cq(nvmeq
);
1056 spin_unlock(&nvmeq
->cq_poll_lock
);
1061 static void nvme_pci_submit_async_event(struct nvme_ctrl
*ctrl
)
1063 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
1064 struct nvme_queue
*nvmeq
= &dev
->queues
[0];
1065 struct nvme_command c
;
1067 memset(&c
, 0, sizeof(c
));
1068 c
.common
.opcode
= nvme_admin_async_event
;
1069 c
.common
.command_id
= NVME_AQ_BLK_MQ_DEPTH
;
1070 nvme_submit_cmd(nvmeq
, &c
, true);
1073 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
1075 struct nvme_command c
;
1077 memset(&c
, 0, sizeof(c
));
1078 c
.delete_queue
.opcode
= opcode
;
1079 c
.delete_queue
.qid
= cpu_to_le16(id
);
1081 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1084 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
1085 struct nvme_queue
*nvmeq
, s16 vector
)
1087 struct nvme_command c
;
1088 int flags
= NVME_QUEUE_PHYS_CONTIG
;
1090 if (!test_bit(NVMEQ_POLLED
, &nvmeq
->flags
))
1091 flags
|= NVME_CQ_IRQ_ENABLED
;
1094 * Note: we (ab)use the fact that the prp fields survive if no data
1095 * is attached to the request.
1097 memset(&c
, 0, sizeof(c
));
1098 c
.create_cq
.opcode
= nvme_admin_create_cq
;
1099 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
1100 c
.create_cq
.cqid
= cpu_to_le16(qid
);
1101 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
1102 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
1103 c
.create_cq
.irq_vector
= cpu_to_le16(vector
);
1105 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1108 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
1109 struct nvme_queue
*nvmeq
)
1111 struct nvme_ctrl
*ctrl
= &dev
->ctrl
;
1112 struct nvme_command c
;
1113 int flags
= NVME_QUEUE_PHYS_CONTIG
;
1116 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1117 * set. Since URGENT priority is zeroes, it makes all queues
1120 if (ctrl
->quirks
& NVME_QUIRK_MEDIUM_PRIO_SQ
)
1121 flags
|= NVME_SQ_PRIO_MEDIUM
;
1124 * Note: we (ab)use the fact that the prp fields survive if no data
1125 * is attached to the request.
1127 memset(&c
, 0, sizeof(c
));
1128 c
.create_sq
.opcode
= nvme_admin_create_sq
;
1129 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
1130 c
.create_sq
.sqid
= cpu_to_le16(qid
);
1131 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
1132 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
1133 c
.create_sq
.cqid
= cpu_to_le16(qid
);
1135 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1138 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
1140 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
1143 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
1145 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
1148 static void abort_endio(struct request
*req
, blk_status_t error
)
1150 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
1151 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
1153 dev_warn(nvmeq
->dev
->ctrl
.device
,
1154 "Abort status: 0x%x", nvme_req(req
)->status
);
1155 atomic_inc(&nvmeq
->dev
->ctrl
.abort_limit
);
1156 blk_mq_free_request(req
);
1159 static bool nvme_should_reset(struct nvme_dev
*dev
, u32 csts
)
1162 /* If true, indicates loss of adapter communication, possibly by a
1163 * NVMe Subsystem reset.
1165 bool nssro
= dev
->subsystem
&& (csts
& NVME_CSTS_NSSRO
);
1167 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1168 switch (dev
->ctrl
.state
) {
1169 case NVME_CTRL_RESETTING
:
1170 case NVME_CTRL_CONNECTING
:
1176 /* We shouldn't reset unless the controller is on fatal error state
1177 * _or_ if we lost the communication with it.
1179 if (!(csts
& NVME_CSTS_CFS
) && !nssro
)
1185 static void nvme_warn_reset(struct nvme_dev
*dev
, u32 csts
)
1187 /* Read a config register to help see what died. */
1191 result
= pci_read_config_word(to_pci_dev(dev
->dev
), PCI_STATUS
,
1193 if (result
== PCIBIOS_SUCCESSFUL
)
1194 dev_warn(dev
->ctrl
.device
,
1195 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1198 dev_warn(dev
->ctrl
.device
,
1199 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1203 static enum blk_eh_timer_return
nvme_timeout(struct request
*req
, bool reserved
)
1205 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
1206 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
1207 struct nvme_dev
*dev
= nvmeq
->dev
;
1208 struct request
*abort_req
;
1209 struct nvme_command cmd
;
1210 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1212 /* If PCI error recovery process is happening, we cannot reset or
1213 * the recovery mechanism will surely fail.
1216 if (pci_channel_offline(to_pci_dev(dev
->dev
)))
1217 return BLK_EH_RESET_TIMER
;
1220 * Reset immediately if the controller is failed
1222 if (nvme_should_reset(dev
, csts
)) {
1223 nvme_warn_reset(dev
, csts
);
1224 nvme_dev_disable(dev
, false);
1225 nvme_reset_ctrl(&dev
->ctrl
);
1230 * Did we miss an interrupt?
1232 if (test_bit(NVMEQ_POLLED
, &nvmeq
->flags
))
1233 nvme_poll(req
->mq_hctx
);
1235 nvme_poll_irqdisable(nvmeq
);
1237 if (blk_mq_request_completed(req
)) {
1238 dev_warn(dev
->ctrl
.device
,
1239 "I/O %d QID %d timeout, completion polled\n",
1240 req
->tag
, nvmeq
->qid
);
1245 * Shutdown immediately if controller times out while starting. The
1246 * reset work will see the pci device disabled when it gets the forced
1247 * cancellation error. All outstanding requests are completed on
1248 * shutdown, so we return BLK_EH_DONE.
1250 switch (dev
->ctrl
.state
) {
1251 case NVME_CTRL_CONNECTING
:
1252 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DELETING
);
1254 case NVME_CTRL_DELETING
:
1255 dev_warn_ratelimited(dev
->ctrl
.device
,
1256 "I/O %d QID %d timeout, disable controller\n",
1257 req
->tag
, nvmeq
->qid
);
1258 nvme_dev_disable(dev
, true);
1259 nvme_req(req
)->flags
|= NVME_REQ_CANCELLED
;
1261 case NVME_CTRL_RESETTING
:
1262 return BLK_EH_RESET_TIMER
;
1268 * Shutdown the controller immediately and schedule a reset if the
1269 * command was already aborted once before and still hasn't been
1270 * returned to the driver, or if this is the admin queue.
1272 if (!nvmeq
->qid
|| iod
->aborted
) {
1273 dev_warn(dev
->ctrl
.device
,
1274 "I/O %d QID %d timeout, reset controller\n",
1275 req
->tag
, nvmeq
->qid
);
1276 nvme_dev_disable(dev
, false);
1277 nvme_reset_ctrl(&dev
->ctrl
);
1279 nvme_req(req
)->flags
|= NVME_REQ_CANCELLED
;
1283 if (atomic_dec_return(&dev
->ctrl
.abort_limit
) < 0) {
1284 atomic_inc(&dev
->ctrl
.abort_limit
);
1285 return BLK_EH_RESET_TIMER
;
1289 memset(&cmd
, 0, sizeof(cmd
));
1290 cmd
.abort
.opcode
= nvme_admin_abort_cmd
;
1291 cmd
.abort
.cid
= req
->tag
;
1292 cmd
.abort
.sqid
= cpu_to_le16(nvmeq
->qid
);
1294 dev_warn(nvmeq
->dev
->ctrl
.device
,
1295 "I/O %d QID %d timeout, aborting\n",
1296 req
->tag
, nvmeq
->qid
);
1298 abort_req
= nvme_alloc_request(dev
->ctrl
.admin_q
, &cmd
,
1299 BLK_MQ_REQ_NOWAIT
, NVME_QID_ANY
);
1300 if (IS_ERR(abort_req
)) {
1301 atomic_inc(&dev
->ctrl
.abort_limit
);
1302 return BLK_EH_RESET_TIMER
;
1305 abort_req
->timeout
= ADMIN_TIMEOUT
;
1306 abort_req
->end_io_data
= NULL
;
1307 blk_execute_rq_nowait(abort_req
->q
, NULL
, abort_req
, 0, abort_endio
);
1310 * The aborted req will be completed on receiving the abort req.
1311 * We enable the timer again. If hit twice, it'll cause a device reset,
1312 * as the device then is in a faulty state.
1314 return BLK_EH_RESET_TIMER
;
1317 static void nvme_free_queue(struct nvme_queue
*nvmeq
)
1319 dma_free_coherent(nvmeq
->dev
->dev
, CQ_SIZE(nvmeq
),
1320 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
1321 if (!nvmeq
->sq_cmds
)
1324 if (test_and_clear_bit(NVMEQ_SQ_CMB
, &nvmeq
->flags
)) {
1325 pci_free_p2pmem(to_pci_dev(nvmeq
->dev
->dev
),
1326 nvmeq
->sq_cmds
, SQ_SIZE(nvmeq
));
1328 dma_free_coherent(nvmeq
->dev
->dev
, SQ_SIZE(nvmeq
),
1329 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
1333 static void nvme_free_queues(struct nvme_dev
*dev
, int lowest
)
1337 for (i
= dev
->ctrl
.queue_count
- 1; i
>= lowest
; i
--) {
1338 dev
->ctrl
.queue_count
--;
1339 nvme_free_queue(&dev
->queues
[i
]);
1344 * nvme_suspend_queue - put queue into suspended state
1345 * @nvmeq: queue to suspend
1347 static int nvme_suspend_queue(struct nvme_queue
*nvmeq
)
1349 if (!test_and_clear_bit(NVMEQ_ENABLED
, &nvmeq
->flags
))
1352 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1355 nvmeq
->dev
->online_queues
--;
1356 if (!nvmeq
->qid
&& nvmeq
->dev
->ctrl
.admin_q
)
1357 blk_mq_quiesce_queue(nvmeq
->dev
->ctrl
.admin_q
);
1358 if (!test_and_clear_bit(NVMEQ_POLLED
, &nvmeq
->flags
))
1359 pci_free_irq(to_pci_dev(nvmeq
->dev
->dev
), nvmeq
->cq_vector
, nvmeq
);
1363 static void nvme_suspend_io_queues(struct nvme_dev
*dev
)
1367 for (i
= dev
->ctrl
.queue_count
- 1; i
> 0; i
--)
1368 nvme_suspend_queue(&dev
->queues
[i
]);
1371 static void nvme_disable_admin_queue(struct nvme_dev
*dev
, bool shutdown
)
1373 struct nvme_queue
*nvmeq
= &dev
->queues
[0];
1376 nvme_shutdown_ctrl(&dev
->ctrl
);
1378 nvme_disable_ctrl(&dev
->ctrl
);
1380 nvme_poll_irqdisable(nvmeq
);
1384 * Called only on a device that has been disabled and after all other threads
1385 * that can check this device's completion queues have synced. This is the
1386 * last chance for the driver to see a natural completion before
1387 * nvme_cancel_request() terminates all incomplete requests.
1389 static void nvme_reap_pending_cqes(struct nvme_dev
*dev
)
1393 for (i
= dev
->ctrl
.queue_count
- 1; i
> 0; i
--)
1394 nvme_process_cq(&dev
->queues
[i
]);
1397 static int nvme_cmb_qdepth(struct nvme_dev
*dev
, int nr_io_queues
,
1400 int q_depth
= dev
->q_depth
;
1401 unsigned q_size_aligned
= roundup(q_depth
* entry_size
,
1402 dev
->ctrl
.page_size
);
1404 if (q_size_aligned
* nr_io_queues
> dev
->cmb_size
) {
1405 u64 mem_per_q
= div_u64(dev
->cmb_size
, nr_io_queues
);
1406 mem_per_q
= round_down(mem_per_q
, dev
->ctrl
.page_size
);
1407 q_depth
= div_u64(mem_per_q
, entry_size
);
1410 * Ensure the reduced q_depth is above some threshold where it
1411 * would be better to map queues in system memory with the
1421 static int nvme_alloc_sq_cmds(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1424 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1426 if (qid
&& dev
->cmb_use_sqes
&& (dev
->cmbsz
& NVME_CMBSZ_SQS
)) {
1427 nvmeq
->sq_cmds
= pci_alloc_p2pmem(pdev
, SQ_SIZE(nvmeq
));
1428 if (nvmeq
->sq_cmds
) {
1429 nvmeq
->sq_dma_addr
= pci_p2pmem_virt_to_bus(pdev
,
1431 if (nvmeq
->sq_dma_addr
) {
1432 set_bit(NVMEQ_SQ_CMB
, &nvmeq
->flags
);
1436 pci_free_p2pmem(pdev
, nvmeq
->sq_cmds
, SQ_SIZE(nvmeq
));
1440 nvmeq
->sq_cmds
= dma_alloc_coherent(dev
->dev
, SQ_SIZE(nvmeq
),
1441 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
1442 if (!nvmeq
->sq_cmds
)
1447 static int nvme_alloc_queue(struct nvme_dev
*dev
, int qid
, int depth
)
1449 struct nvme_queue
*nvmeq
= &dev
->queues
[qid
];
1451 if (dev
->ctrl
.queue_count
> qid
)
1454 nvmeq
->sqes
= qid
? dev
->io_sqes
: NVME_ADM_SQES
;
1455 nvmeq
->q_depth
= depth
;
1456 nvmeq
->cqes
= dma_alloc_coherent(dev
->dev
, CQ_SIZE(nvmeq
),
1457 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
1461 if (nvme_alloc_sq_cmds(dev
, nvmeq
, qid
))
1465 spin_lock_init(&nvmeq
->sq_lock
);
1466 spin_lock_init(&nvmeq
->cq_poll_lock
);
1468 nvmeq
->cq_phase
= 1;
1469 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1471 dev
->ctrl
.queue_count
++;
1476 dma_free_coherent(dev
->dev
, CQ_SIZE(nvmeq
), (void *)nvmeq
->cqes
,
1477 nvmeq
->cq_dma_addr
);
1482 static int queue_request_irq(struct nvme_queue
*nvmeq
)
1484 struct pci_dev
*pdev
= to_pci_dev(nvmeq
->dev
->dev
);
1485 int nr
= nvmeq
->dev
->ctrl
.instance
;
1487 if (use_threaded_interrupts
) {
1488 return pci_request_irq(pdev
, nvmeq
->cq_vector
, nvme_irq_check
,
1489 nvme_irq
, nvmeq
, "nvme%dq%d", nr
, nvmeq
->qid
);
1491 return pci_request_irq(pdev
, nvmeq
->cq_vector
, nvme_irq
,
1492 NULL
, nvmeq
, "nvme%dq%d", nr
, nvmeq
->qid
);
1496 static void nvme_init_queue(struct nvme_queue
*nvmeq
, u16 qid
)
1498 struct nvme_dev
*dev
= nvmeq
->dev
;
1501 nvmeq
->last_sq_tail
= 0;
1503 nvmeq
->cq_phase
= 1;
1504 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1505 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(nvmeq
));
1506 nvme_dbbuf_init(dev
, nvmeq
, qid
);
1507 dev
->online_queues
++;
1508 wmb(); /* ensure the first interrupt sees the initialization */
1511 static int nvme_create_queue(struct nvme_queue
*nvmeq
, int qid
, bool polled
)
1513 struct nvme_dev
*dev
= nvmeq
->dev
;
1517 clear_bit(NVMEQ_DELETE_ERROR
, &nvmeq
->flags
);
1520 * A queue's vector matches the queue identifier unless the controller
1521 * has only one vector available.
1524 vector
= dev
->num_vecs
== 1 ? 0 : qid
;
1526 set_bit(NVMEQ_POLLED
, &nvmeq
->flags
);
1528 result
= adapter_alloc_cq(dev
, qid
, nvmeq
, vector
);
1532 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
1538 nvmeq
->cq_vector
= vector
;
1539 nvme_init_queue(nvmeq
, qid
);
1542 result
= queue_request_irq(nvmeq
);
1547 set_bit(NVMEQ_ENABLED
, &nvmeq
->flags
);
1551 dev
->online_queues
--;
1552 adapter_delete_sq(dev
, qid
);
1554 adapter_delete_cq(dev
, qid
);
1558 static const struct blk_mq_ops nvme_mq_admin_ops
= {
1559 .queue_rq
= nvme_queue_rq
,
1560 .complete
= nvme_pci_complete_rq
,
1561 .init_hctx
= nvme_admin_init_hctx
,
1562 .init_request
= nvme_init_request
,
1563 .timeout
= nvme_timeout
,
1566 static const struct blk_mq_ops nvme_mq_ops
= {
1567 .queue_rq
= nvme_queue_rq
,
1568 .complete
= nvme_pci_complete_rq
,
1569 .commit_rqs
= nvme_commit_rqs
,
1570 .init_hctx
= nvme_init_hctx
,
1571 .init_request
= nvme_init_request
,
1572 .map_queues
= nvme_pci_map_queues
,
1573 .timeout
= nvme_timeout
,
1577 static void nvme_dev_remove_admin(struct nvme_dev
*dev
)
1579 if (dev
->ctrl
.admin_q
&& !blk_queue_dying(dev
->ctrl
.admin_q
)) {
1581 * If the controller was reset during removal, it's possible
1582 * user requests may be waiting on a stopped queue. Start the
1583 * queue to flush these to completion.
1585 blk_mq_unquiesce_queue(dev
->ctrl
.admin_q
);
1586 blk_cleanup_queue(dev
->ctrl
.admin_q
);
1587 blk_mq_free_tag_set(&dev
->admin_tagset
);
1591 static int nvme_alloc_admin_tags(struct nvme_dev
*dev
)
1593 if (!dev
->ctrl
.admin_q
) {
1594 dev
->admin_tagset
.ops
= &nvme_mq_admin_ops
;
1595 dev
->admin_tagset
.nr_hw_queues
= 1;
1597 dev
->admin_tagset
.queue_depth
= NVME_AQ_MQ_TAG_DEPTH
;
1598 dev
->admin_tagset
.timeout
= ADMIN_TIMEOUT
;
1599 dev
->admin_tagset
.numa_node
= dev_to_node(dev
->dev
);
1600 dev
->admin_tagset
.cmd_size
= sizeof(struct nvme_iod
);
1601 dev
->admin_tagset
.flags
= BLK_MQ_F_NO_SCHED
;
1602 dev
->admin_tagset
.driver_data
= dev
;
1604 if (blk_mq_alloc_tag_set(&dev
->admin_tagset
))
1606 dev
->ctrl
.admin_tagset
= &dev
->admin_tagset
;
1608 dev
->ctrl
.admin_q
= blk_mq_init_queue(&dev
->admin_tagset
);
1609 if (IS_ERR(dev
->ctrl
.admin_q
)) {
1610 blk_mq_free_tag_set(&dev
->admin_tagset
);
1613 if (!blk_get_queue(dev
->ctrl
.admin_q
)) {
1614 nvme_dev_remove_admin(dev
);
1615 dev
->ctrl
.admin_q
= NULL
;
1619 blk_mq_unquiesce_queue(dev
->ctrl
.admin_q
);
1624 static unsigned long db_bar_size(struct nvme_dev
*dev
, unsigned nr_io_queues
)
1626 return NVME_REG_DBS
+ ((nr_io_queues
+ 1) * 8 * dev
->db_stride
);
1629 static int nvme_remap_bar(struct nvme_dev
*dev
, unsigned long size
)
1631 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1633 if (size
<= dev
->bar_mapped_size
)
1635 if (size
> pci_resource_len(pdev
, 0))
1639 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), size
);
1641 dev
->bar_mapped_size
= 0;
1644 dev
->bar_mapped_size
= size
;
1645 dev
->dbs
= dev
->bar
+ NVME_REG_DBS
;
1650 static int nvme_pci_configure_admin_queue(struct nvme_dev
*dev
)
1654 struct nvme_queue
*nvmeq
;
1656 result
= nvme_remap_bar(dev
, db_bar_size(dev
, 0));
1660 dev
->subsystem
= readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 1, 0) ?
1661 NVME_CAP_NSSRC(dev
->ctrl
.cap
) : 0;
1663 if (dev
->subsystem
&&
1664 (readl(dev
->bar
+ NVME_REG_CSTS
) & NVME_CSTS_NSSRO
))
1665 writel(NVME_CSTS_NSSRO
, dev
->bar
+ NVME_REG_CSTS
);
1667 result
= nvme_disable_ctrl(&dev
->ctrl
);
1671 result
= nvme_alloc_queue(dev
, 0, NVME_AQ_DEPTH
);
1675 nvmeq
= &dev
->queues
[0];
1676 aqa
= nvmeq
->q_depth
- 1;
1679 writel(aqa
, dev
->bar
+ NVME_REG_AQA
);
1680 lo_hi_writeq(nvmeq
->sq_dma_addr
, dev
->bar
+ NVME_REG_ASQ
);
1681 lo_hi_writeq(nvmeq
->cq_dma_addr
, dev
->bar
+ NVME_REG_ACQ
);
1683 result
= nvme_enable_ctrl(&dev
->ctrl
);
1687 nvmeq
->cq_vector
= 0;
1688 nvme_init_queue(nvmeq
, 0);
1689 result
= queue_request_irq(nvmeq
);
1691 dev
->online_queues
--;
1695 set_bit(NVMEQ_ENABLED
, &nvmeq
->flags
);
1699 static int nvme_create_io_queues(struct nvme_dev
*dev
)
1701 unsigned i
, max
, rw_queues
;
1704 for (i
= dev
->ctrl
.queue_count
; i
<= dev
->max_qid
; i
++) {
1705 if (nvme_alloc_queue(dev
, i
, dev
->q_depth
)) {
1711 max
= min(dev
->max_qid
, dev
->ctrl
.queue_count
- 1);
1712 if (max
!= 1 && dev
->io_queues
[HCTX_TYPE_POLL
]) {
1713 rw_queues
= dev
->io_queues
[HCTX_TYPE_DEFAULT
] +
1714 dev
->io_queues
[HCTX_TYPE_READ
];
1719 for (i
= dev
->online_queues
; i
<= max
; i
++) {
1720 bool polled
= i
> rw_queues
;
1722 ret
= nvme_create_queue(&dev
->queues
[i
], i
, polled
);
1728 * Ignore failing Create SQ/CQ commands, we can continue with less
1729 * than the desired amount of queues, and even a controller without
1730 * I/O queues can still be used to issue admin commands. This might
1731 * be useful to upgrade a buggy firmware for example.
1733 return ret
>= 0 ? 0 : ret
;
1736 static ssize_t
nvme_cmb_show(struct device
*dev
,
1737 struct device_attribute
*attr
,
1740 struct nvme_dev
*ndev
= to_nvme_dev(dev_get_drvdata(dev
));
1742 return scnprintf(buf
, PAGE_SIZE
, "cmbloc : x%08x\ncmbsz : x%08x\n",
1743 ndev
->cmbloc
, ndev
->cmbsz
);
1745 static DEVICE_ATTR(cmb
, S_IRUGO
, nvme_cmb_show
, NULL
);
1747 static u64
nvme_cmb_size_unit(struct nvme_dev
*dev
)
1749 u8 szu
= (dev
->cmbsz
>> NVME_CMBSZ_SZU_SHIFT
) & NVME_CMBSZ_SZU_MASK
;
1751 return 1ULL << (12 + 4 * szu
);
1754 static u32
nvme_cmb_size(struct nvme_dev
*dev
)
1756 return (dev
->cmbsz
>> NVME_CMBSZ_SZ_SHIFT
) & NVME_CMBSZ_SZ_MASK
;
1759 static void nvme_map_cmb(struct nvme_dev
*dev
)
1762 resource_size_t bar_size
;
1763 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1769 dev
->cmbsz
= readl(dev
->bar
+ NVME_REG_CMBSZ
);
1772 dev
->cmbloc
= readl(dev
->bar
+ NVME_REG_CMBLOC
);
1774 size
= nvme_cmb_size_unit(dev
) * nvme_cmb_size(dev
);
1775 offset
= nvme_cmb_size_unit(dev
) * NVME_CMB_OFST(dev
->cmbloc
);
1776 bar
= NVME_CMB_BIR(dev
->cmbloc
);
1777 bar_size
= pci_resource_len(pdev
, bar
);
1779 if (offset
> bar_size
)
1783 * Controllers may support a CMB size larger than their BAR,
1784 * for example, due to being behind a bridge. Reduce the CMB to
1785 * the reported size of the BAR
1787 if (size
> bar_size
- offset
)
1788 size
= bar_size
- offset
;
1790 if (pci_p2pdma_add_resource(pdev
, bar
, size
, offset
)) {
1791 dev_warn(dev
->ctrl
.device
,
1792 "failed to register the CMB\n");
1796 dev
->cmb_size
= size
;
1797 dev
->cmb_use_sqes
= use_cmb_sqes
&& (dev
->cmbsz
& NVME_CMBSZ_SQS
);
1799 if ((dev
->cmbsz
& (NVME_CMBSZ_WDS
| NVME_CMBSZ_RDS
)) ==
1800 (NVME_CMBSZ_WDS
| NVME_CMBSZ_RDS
))
1801 pci_p2pmem_publish(pdev
, true);
1803 if (sysfs_add_file_to_group(&dev
->ctrl
.device
->kobj
,
1804 &dev_attr_cmb
.attr
, NULL
))
1805 dev_warn(dev
->ctrl
.device
,
1806 "failed to add sysfs attribute for CMB\n");
1809 static inline void nvme_release_cmb(struct nvme_dev
*dev
)
1811 if (dev
->cmb_size
) {
1812 sysfs_remove_file_from_group(&dev
->ctrl
.device
->kobj
,
1813 &dev_attr_cmb
.attr
, NULL
);
1818 static int nvme_set_host_mem(struct nvme_dev
*dev
, u32 bits
)
1820 u64 dma_addr
= dev
->host_mem_descs_dma
;
1821 struct nvme_command c
;
1824 memset(&c
, 0, sizeof(c
));
1825 c
.features
.opcode
= nvme_admin_set_features
;
1826 c
.features
.fid
= cpu_to_le32(NVME_FEAT_HOST_MEM_BUF
);
1827 c
.features
.dword11
= cpu_to_le32(bits
);
1828 c
.features
.dword12
= cpu_to_le32(dev
->host_mem_size
>>
1829 ilog2(dev
->ctrl
.page_size
));
1830 c
.features
.dword13
= cpu_to_le32(lower_32_bits(dma_addr
));
1831 c
.features
.dword14
= cpu_to_le32(upper_32_bits(dma_addr
));
1832 c
.features
.dword15
= cpu_to_le32(dev
->nr_host_mem_descs
);
1834 ret
= nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1836 dev_warn(dev
->ctrl
.device
,
1837 "failed to set host mem (err %d, flags %#x).\n",
1843 static void nvme_free_host_mem(struct nvme_dev
*dev
)
1847 for (i
= 0; i
< dev
->nr_host_mem_descs
; i
++) {
1848 struct nvme_host_mem_buf_desc
*desc
= &dev
->host_mem_descs
[i
];
1849 size_t size
= le32_to_cpu(desc
->size
) * dev
->ctrl
.page_size
;
1851 dma_free_attrs(dev
->dev
, size
, dev
->host_mem_desc_bufs
[i
],
1852 le64_to_cpu(desc
->addr
),
1853 DMA_ATTR_NO_KERNEL_MAPPING
| DMA_ATTR_NO_WARN
);
1856 kfree(dev
->host_mem_desc_bufs
);
1857 dev
->host_mem_desc_bufs
= NULL
;
1858 dma_free_coherent(dev
->dev
,
1859 dev
->nr_host_mem_descs
* sizeof(*dev
->host_mem_descs
),
1860 dev
->host_mem_descs
, dev
->host_mem_descs_dma
);
1861 dev
->host_mem_descs
= NULL
;
1862 dev
->nr_host_mem_descs
= 0;
1865 static int __nvme_alloc_host_mem(struct nvme_dev
*dev
, u64 preferred
,
1868 struct nvme_host_mem_buf_desc
*descs
;
1869 u32 max_entries
, len
;
1870 dma_addr_t descs_dma
;
1875 tmp
= (preferred
+ chunk_size
- 1);
1876 do_div(tmp
, chunk_size
);
1879 if (dev
->ctrl
.hmmaxd
&& dev
->ctrl
.hmmaxd
< max_entries
)
1880 max_entries
= dev
->ctrl
.hmmaxd
;
1882 descs
= dma_alloc_coherent(dev
->dev
, max_entries
* sizeof(*descs
),
1883 &descs_dma
, GFP_KERNEL
);
1887 bufs
= kcalloc(max_entries
, sizeof(*bufs
), GFP_KERNEL
);
1889 goto out_free_descs
;
1891 for (size
= 0; size
< preferred
&& i
< max_entries
; size
+= len
) {
1892 dma_addr_t dma_addr
;
1894 len
= min_t(u64
, chunk_size
, preferred
- size
);
1895 bufs
[i
] = dma_alloc_attrs(dev
->dev
, len
, &dma_addr
, GFP_KERNEL
,
1896 DMA_ATTR_NO_KERNEL_MAPPING
| DMA_ATTR_NO_WARN
);
1900 descs
[i
].addr
= cpu_to_le64(dma_addr
);
1901 descs
[i
].size
= cpu_to_le32(len
/ dev
->ctrl
.page_size
);
1908 dev
->nr_host_mem_descs
= i
;
1909 dev
->host_mem_size
= size
;
1910 dev
->host_mem_descs
= descs
;
1911 dev
->host_mem_descs_dma
= descs_dma
;
1912 dev
->host_mem_desc_bufs
= bufs
;
1917 size_t size
= le32_to_cpu(descs
[i
].size
) * dev
->ctrl
.page_size
;
1919 dma_free_attrs(dev
->dev
, size
, bufs
[i
],
1920 le64_to_cpu(descs
[i
].addr
),
1921 DMA_ATTR_NO_KERNEL_MAPPING
| DMA_ATTR_NO_WARN
);
1926 dma_free_coherent(dev
->dev
, max_entries
* sizeof(*descs
), descs
,
1929 dev
->host_mem_descs
= NULL
;
1933 static int nvme_alloc_host_mem(struct nvme_dev
*dev
, u64 min
, u64 preferred
)
1937 /* start big and work our way down */
1938 for (chunk_size
= min_t(u64
, preferred
, PAGE_SIZE
* MAX_ORDER_NR_PAGES
);
1939 chunk_size
>= max_t(u32
, dev
->ctrl
.hmminds
* 4096, PAGE_SIZE
* 2);
1941 if (!__nvme_alloc_host_mem(dev
, preferred
, chunk_size
)) {
1942 if (!min
|| dev
->host_mem_size
>= min
)
1944 nvme_free_host_mem(dev
);
1951 static int nvme_setup_host_mem(struct nvme_dev
*dev
)
1953 u64 max
= (u64
)max_host_mem_size_mb
* SZ_1M
;
1954 u64 preferred
= (u64
)dev
->ctrl
.hmpre
* 4096;
1955 u64 min
= (u64
)dev
->ctrl
.hmmin
* 4096;
1956 u32 enable_bits
= NVME_HOST_MEM_ENABLE
;
1959 preferred
= min(preferred
, max
);
1961 dev_warn(dev
->ctrl
.device
,
1962 "min host memory (%lld MiB) above limit (%d MiB).\n",
1963 min
>> ilog2(SZ_1M
), max_host_mem_size_mb
);
1964 nvme_free_host_mem(dev
);
1969 * If we already have a buffer allocated check if we can reuse it.
1971 if (dev
->host_mem_descs
) {
1972 if (dev
->host_mem_size
>= min
)
1973 enable_bits
|= NVME_HOST_MEM_RETURN
;
1975 nvme_free_host_mem(dev
);
1978 if (!dev
->host_mem_descs
) {
1979 if (nvme_alloc_host_mem(dev
, min
, preferred
)) {
1980 dev_warn(dev
->ctrl
.device
,
1981 "failed to allocate host memory buffer.\n");
1982 return 0; /* controller must work without HMB */
1985 dev_info(dev
->ctrl
.device
,
1986 "allocated %lld MiB host memory buffer.\n",
1987 dev
->host_mem_size
>> ilog2(SZ_1M
));
1990 ret
= nvme_set_host_mem(dev
, enable_bits
);
1992 nvme_free_host_mem(dev
);
1997 * nirqs is the number of interrupts available for write and read
1998 * queues. The core already reserved an interrupt for the admin queue.
2000 static void nvme_calc_irq_sets(struct irq_affinity
*affd
, unsigned int nrirqs
)
2002 struct nvme_dev
*dev
= affd
->priv
;
2003 unsigned int nr_read_queues
;
2006 * If there is no interupt available for queues, ensure that
2007 * the default queue is set to 1. The affinity set size is
2008 * also set to one, but the irq core ignores it for this case.
2010 * If only one interrupt is available or 'write_queue' == 0, combine
2011 * write and read queues.
2013 * If 'write_queues' > 0, ensure it leaves room for at least one read
2019 } else if (nrirqs
== 1 || !write_queues
) {
2021 } else if (write_queues
>= nrirqs
) {
2024 nr_read_queues
= nrirqs
- write_queues
;
2027 dev
->io_queues
[HCTX_TYPE_DEFAULT
] = nrirqs
- nr_read_queues
;
2028 affd
->set_size
[HCTX_TYPE_DEFAULT
] = nrirqs
- nr_read_queues
;
2029 dev
->io_queues
[HCTX_TYPE_READ
] = nr_read_queues
;
2030 affd
->set_size
[HCTX_TYPE_READ
] = nr_read_queues
;
2031 affd
->nr_sets
= nr_read_queues
? 2 : 1;
2034 static int nvme_setup_irqs(struct nvme_dev
*dev
, unsigned int nr_io_queues
)
2036 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2037 struct irq_affinity affd
= {
2039 .calc_sets
= nvme_calc_irq_sets
,
2042 unsigned int irq_queues
, this_p_queues
;
2045 * Poll queues don't need interrupts, but we need at least one IO
2046 * queue left over for non-polled IO.
2048 this_p_queues
= poll_queues
;
2049 if (this_p_queues
>= nr_io_queues
) {
2050 this_p_queues
= nr_io_queues
- 1;
2053 irq_queues
= nr_io_queues
- this_p_queues
+ 1;
2055 dev
->io_queues
[HCTX_TYPE_POLL
] = this_p_queues
;
2057 /* Initialize for the single interrupt case */
2058 dev
->io_queues
[HCTX_TYPE_DEFAULT
] = 1;
2059 dev
->io_queues
[HCTX_TYPE_READ
] = 0;
2062 * Some Apple controllers require all queues to use the
2065 if (dev
->ctrl
.quirks
& NVME_QUIRK_SINGLE_VECTOR
)
2068 return pci_alloc_irq_vectors_affinity(pdev
, 1, irq_queues
,
2069 PCI_IRQ_ALL_TYPES
| PCI_IRQ_AFFINITY
, &affd
);
2072 static void nvme_disable_io_queues(struct nvme_dev
*dev
)
2074 if (__nvme_disable_io_queues(dev
, nvme_admin_delete_sq
))
2075 __nvme_disable_io_queues(dev
, nvme_admin_delete_cq
);
2078 static int nvme_setup_io_queues(struct nvme_dev
*dev
)
2080 struct nvme_queue
*adminq
= &dev
->queues
[0];
2081 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2082 int result
, nr_io_queues
;
2085 nr_io_queues
= max_io_queues();
2088 * If tags are shared with admin queue (Apple bug), then
2089 * make sure we only use one IO queue.
2091 if (dev
->ctrl
.quirks
& NVME_QUIRK_SHARED_TAGS
)
2094 result
= nvme_set_queue_count(&dev
->ctrl
, &nr_io_queues
);
2098 if (nr_io_queues
== 0)
2101 clear_bit(NVMEQ_ENABLED
, &adminq
->flags
);
2103 if (dev
->cmb_use_sqes
) {
2104 result
= nvme_cmb_qdepth(dev
, nr_io_queues
,
2105 sizeof(struct nvme_command
));
2107 dev
->q_depth
= result
;
2109 dev
->cmb_use_sqes
= false;
2113 size
= db_bar_size(dev
, nr_io_queues
);
2114 result
= nvme_remap_bar(dev
, size
);
2117 if (!--nr_io_queues
)
2120 adminq
->q_db
= dev
->dbs
;
2123 /* Deregister the admin queue's interrupt */
2124 pci_free_irq(pdev
, 0, adminq
);
2127 * If we enable msix early due to not intx, disable it again before
2128 * setting up the full range we need.
2130 pci_free_irq_vectors(pdev
);
2132 result
= nvme_setup_irqs(dev
, nr_io_queues
);
2136 dev
->num_vecs
= result
;
2137 result
= max(result
- 1, 1);
2138 dev
->max_qid
= result
+ dev
->io_queues
[HCTX_TYPE_POLL
];
2141 * Should investigate if there's a performance win from allocating
2142 * more queues than interrupt vectors; it might allow the submission
2143 * path to scale better, even if the receive path is limited by the
2144 * number of interrupts.
2146 result
= queue_request_irq(adminq
);
2149 set_bit(NVMEQ_ENABLED
, &adminq
->flags
);
2151 result
= nvme_create_io_queues(dev
);
2152 if (result
|| dev
->online_queues
< 2)
2155 if (dev
->online_queues
- 1 < dev
->max_qid
) {
2156 nr_io_queues
= dev
->online_queues
- 1;
2157 nvme_disable_io_queues(dev
);
2158 nvme_suspend_io_queues(dev
);
2161 dev_info(dev
->ctrl
.device
, "%d/%d/%d default/read/poll queues\n",
2162 dev
->io_queues
[HCTX_TYPE_DEFAULT
],
2163 dev
->io_queues
[HCTX_TYPE_READ
],
2164 dev
->io_queues
[HCTX_TYPE_POLL
]);
2168 static void nvme_del_queue_end(struct request
*req
, blk_status_t error
)
2170 struct nvme_queue
*nvmeq
= req
->end_io_data
;
2172 blk_mq_free_request(req
);
2173 complete(&nvmeq
->delete_done
);
2176 static void nvme_del_cq_end(struct request
*req
, blk_status_t error
)
2178 struct nvme_queue
*nvmeq
= req
->end_io_data
;
2181 set_bit(NVMEQ_DELETE_ERROR
, &nvmeq
->flags
);
2183 nvme_del_queue_end(req
, error
);
2186 static int nvme_delete_queue(struct nvme_queue
*nvmeq
, u8 opcode
)
2188 struct request_queue
*q
= nvmeq
->dev
->ctrl
.admin_q
;
2189 struct request
*req
;
2190 struct nvme_command cmd
;
2192 memset(&cmd
, 0, sizeof(cmd
));
2193 cmd
.delete_queue
.opcode
= opcode
;
2194 cmd
.delete_queue
.qid
= cpu_to_le16(nvmeq
->qid
);
2196 req
= nvme_alloc_request(q
, &cmd
, BLK_MQ_REQ_NOWAIT
, NVME_QID_ANY
);
2198 return PTR_ERR(req
);
2200 req
->timeout
= ADMIN_TIMEOUT
;
2201 req
->end_io_data
= nvmeq
;
2203 init_completion(&nvmeq
->delete_done
);
2204 blk_execute_rq_nowait(q
, NULL
, req
, false,
2205 opcode
== nvme_admin_delete_cq
?
2206 nvme_del_cq_end
: nvme_del_queue_end
);
2210 static bool __nvme_disable_io_queues(struct nvme_dev
*dev
, u8 opcode
)
2212 int nr_queues
= dev
->online_queues
- 1, sent
= 0;
2213 unsigned long timeout
;
2216 timeout
= ADMIN_TIMEOUT
;
2217 while (nr_queues
> 0) {
2218 if (nvme_delete_queue(&dev
->queues
[nr_queues
], opcode
))
2224 struct nvme_queue
*nvmeq
= &dev
->queues
[nr_queues
+ sent
];
2226 timeout
= wait_for_completion_io_timeout(&nvmeq
->delete_done
,
2238 static void nvme_dev_add(struct nvme_dev
*dev
)
2242 if (!dev
->ctrl
.tagset
) {
2243 dev
->tagset
.ops
= &nvme_mq_ops
;
2244 dev
->tagset
.nr_hw_queues
= dev
->online_queues
- 1;
2245 dev
->tagset
.nr_maps
= 2; /* default + read */
2246 if (dev
->io_queues
[HCTX_TYPE_POLL
])
2247 dev
->tagset
.nr_maps
++;
2248 dev
->tagset
.timeout
= NVME_IO_TIMEOUT
;
2249 dev
->tagset
.numa_node
= dev_to_node(dev
->dev
);
2250 dev
->tagset
.queue_depth
=
2251 min_t(int, dev
->q_depth
, BLK_MQ_MAX_DEPTH
) - 1;
2252 dev
->tagset
.cmd_size
= sizeof(struct nvme_iod
);
2253 dev
->tagset
.flags
= BLK_MQ_F_SHOULD_MERGE
;
2254 dev
->tagset
.driver_data
= dev
;
2257 * Some Apple controllers requires tags to be unique
2258 * across admin and IO queue, so reserve the first 32
2259 * tags of the IO queue.
2261 if (dev
->ctrl
.quirks
& NVME_QUIRK_SHARED_TAGS
)
2262 dev
->tagset
.reserved_tags
= NVME_AQ_DEPTH
;
2264 ret
= blk_mq_alloc_tag_set(&dev
->tagset
);
2266 dev_warn(dev
->ctrl
.device
,
2267 "IO queues tagset allocation failed %d\n", ret
);
2270 dev
->ctrl
.tagset
= &dev
->tagset
;
2272 blk_mq_update_nr_hw_queues(&dev
->tagset
, dev
->online_queues
- 1);
2274 /* Free previously allocated queues that are no longer usable */
2275 nvme_free_queues(dev
, dev
->online_queues
);
2278 nvme_dbbuf_set(dev
);
2281 static int nvme_pci_enable(struct nvme_dev
*dev
)
2283 int result
= -ENOMEM
;
2284 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2286 if (pci_enable_device_mem(pdev
))
2289 pci_set_master(pdev
);
2291 if (dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(64)))
2294 if (readl(dev
->bar
+ NVME_REG_CSTS
) == -1) {
2300 * Some devices and/or platforms don't advertise or work with INTx
2301 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2302 * adjust this later.
2304 result
= pci_alloc_irq_vectors(pdev
, 1, 1, PCI_IRQ_ALL_TYPES
);
2308 dev
->ctrl
.cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
2310 dev
->q_depth
= min_t(int, NVME_CAP_MQES(dev
->ctrl
.cap
) + 1,
2312 dev
->ctrl
.sqsize
= dev
->q_depth
- 1; /* 0's based queue depth */
2313 dev
->db_stride
= 1 << NVME_CAP_STRIDE(dev
->ctrl
.cap
);
2314 dev
->dbs
= dev
->bar
+ 4096;
2317 * Some Apple controllers require a non-standard SQE size.
2318 * Interestingly they also seem to ignore the CC:IOSQES register
2319 * so we don't bother updating it here.
2321 if (dev
->ctrl
.quirks
& NVME_QUIRK_128_BYTES_SQES
)
2324 dev
->io_sqes
= NVME_NVM_IOSQES
;
2327 * Temporary fix for the Apple controller found in the MacBook8,1 and
2328 * some MacBook7,1 to avoid controller resets and data loss.
2330 if (pdev
->vendor
== PCI_VENDOR_ID_APPLE
&& pdev
->device
== 0x2001) {
2332 dev_warn(dev
->ctrl
.device
, "detected Apple NVMe controller, "
2333 "set queue depth=%u to work around controller resets\n",
2335 } else if (pdev
->vendor
== PCI_VENDOR_ID_SAMSUNG
&&
2336 (pdev
->device
== 0xa821 || pdev
->device
== 0xa822) &&
2337 NVME_CAP_MQES(dev
->ctrl
.cap
) == 0) {
2339 dev_err(dev
->ctrl
.device
, "detected PM1725 NVMe controller, "
2340 "set queue depth=%u\n", dev
->q_depth
);
2344 * Controllers with the shared tags quirk need the IO queue to be
2345 * big enough so that we get 32 tags for the admin queue
2347 if ((dev
->ctrl
.quirks
& NVME_QUIRK_SHARED_TAGS
) &&
2348 (dev
->q_depth
< (NVME_AQ_DEPTH
+ 2))) {
2349 dev
->q_depth
= NVME_AQ_DEPTH
+ 2;
2350 dev_warn(dev
->ctrl
.device
, "IO queue depth clamped to %d\n",
2357 pci_enable_pcie_error_reporting(pdev
);
2358 pci_save_state(pdev
);
2362 pci_disable_device(pdev
);
2366 static void nvme_dev_unmap(struct nvme_dev
*dev
)
2370 pci_release_mem_regions(to_pci_dev(dev
->dev
));
2373 static void nvme_pci_disable(struct nvme_dev
*dev
)
2375 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2377 pci_free_irq_vectors(pdev
);
2379 if (pci_is_enabled(pdev
)) {
2380 pci_disable_pcie_error_reporting(pdev
);
2381 pci_disable_device(pdev
);
2385 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
)
2387 bool dead
= true, freeze
= false;
2388 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2390 mutex_lock(&dev
->shutdown_lock
);
2391 if (pci_is_enabled(pdev
)) {
2392 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
2394 if (dev
->ctrl
.state
== NVME_CTRL_LIVE
||
2395 dev
->ctrl
.state
== NVME_CTRL_RESETTING
) {
2397 nvme_start_freeze(&dev
->ctrl
);
2399 dead
= !!((csts
& NVME_CSTS_CFS
) || !(csts
& NVME_CSTS_RDY
) ||
2400 pdev
->error_state
!= pci_channel_io_normal
);
2404 * Give the controller a chance to complete all entered requests if
2405 * doing a safe shutdown.
2407 if (!dead
&& shutdown
&& freeze
)
2408 nvme_wait_freeze_timeout(&dev
->ctrl
, NVME_IO_TIMEOUT
);
2410 nvme_stop_queues(&dev
->ctrl
);
2412 if (!dead
&& dev
->ctrl
.queue_count
> 0) {
2413 nvme_disable_io_queues(dev
);
2414 nvme_disable_admin_queue(dev
, shutdown
);
2416 nvme_suspend_io_queues(dev
);
2417 nvme_suspend_queue(&dev
->queues
[0]);
2418 nvme_pci_disable(dev
);
2419 nvme_reap_pending_cqes(dev
);
2421 blk_mq_tagset_busy_iter(&dev
->tagset
, nvme_cancel_request
, &dev
->ctrl
);
2422 blk_mq_tagset_busy_iter(&dev
->admin_tagset
, nvme_cancel_request
, &dev
->ctrl
);
2423 blk_mq_tagset_wait_completed_request(&dev
->tagset
);
2424 blk_mq_tagset_wait_completed_request(&dev
->admin_tagset
);
2427 * The driver will not be starting up queues again if shutting down so
2428 * must flush all entered requests to their failed completion to avoid
2429 * deadlocking blk-mq hot-cpu notifier.
2432 nvme_start_queues(&dev
->ctrl
);
2433 if (dev
->ctrl
.admin_q
&& !blk_queue_dying(dev
->ctrl
.admin_q
))
2434 blk_mq_unquiesce_queue(dev
->ctrl
.admin_q
);
2436 mutex_unlock(&dev
->shutdown_lock
);
2439 static int nvme_disable_prepare_reset(struct nvme_dev
*dev
, bool shutdown
)
2441 if (!nvme_wait_reset(&dev
->ctrl
))
2443 nvme_dev_disable(dev
, shutdown
);
2447 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
2449 dev
->prp_page_pool
= dma_pool_create("prp list page", dev
->dev
,
2450 PAGE_SIZE
, PAGE_SIZE
, 0);
2451 if (!dev
->prp_page_pool
)
2454 /* Optimisation for I/Os between 4k and 128k */
2455 dev
->prp_small_pool
= dma_pool_create("prp list 256", dev
->dev
,
2457 if (!dev
->prp_small_pool
) {
2458 dma_pool_destroy(dev
->prp_page_pool
);
2464 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
2466 dma_pool_destroy(dev
->prp_page_pool
);
2467 dma_pool_destroy(dev
->prp_small_pool
);
2470 static void nvme_free_tagset(struct nvme_dev
*dev
)
2472 if (dev
->tagset
.tags
)
2473 blk_mq_free_tag_set(&dev
->tagset
);
2474 dev
->ctrl
.tagset
= NULL
;
2477 static void nvme_pci_free_ctrl(struct nvme_ctrl
*ctrl
)
2479 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
2481 nvme_dbbuf_dma_free(dev
);
2482 nvme_free_tagset(dev
);
2483 if (dev
->ctrl
.admin_q
)
2484 blk_put_queue(dev
->ctrl
.admin_q
);
2485 free_opal_dev(dev
->ctrl
.opal_dev
);
2486 mempool_destroy(dev
->iod_mempool
);
2487 put_device(dev
->dev
);
2492 static void nvme_remove_dead_ctrl(struct nvme_dev
*dev
)
2495 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2496 * may be holding this pci_dev's device lock.
2498 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DELETING
);
2499 nvme_get_ctrl(&dev
->ctrl
);
2500 nvme_dev_disable(dev
, false);
2501 nvme_kill_queues(&dev
->ctrl
);
2502 if (!queue_work(nvme_wq
, &dev
->remove_work
))
2503 nvme_put_ctrl(&dev
->ctrl
);
2506 static void nvme_reset_work(struct work_struct
*work
)
2508 struct nvme_dev
*dev
=
2509 container_of(work
, struct nvme_dev
, ctrl
.reset_work
);
2510 bool was_suspend
= !!(dev
->ctrl
.ctrl_config
& NVME_CC_SHN_NORMAL
);
2513 if (WARN_ON(dev
->ctrl
.state
!= NVME_CTRL_RESETTING
)) {
2519 * If we're called to reset a live controller first shut it down before
2522 if (dev
->ctrl
.ctrl_config
& NVME_CC_ENABLE
)
2523 nvme_dev_disable(dev
, false);
2524 nvme_sync_queues(&dev
->ctrl
);
2526 mutex_lock(&dev
->shutdown_lock
);
2527 result
= nvme_pci_enable(dev
);
2531 result
= nvme_pci_configure_admin_queue(dev
);
2535 result
= nvme_alloc_admin_tags(dev
);
2540 * Limit the max command size to prevent iod->sg allocations going
2541 * over a single page.
2543 dev
->ctrl
.max_hw_sectors
= min_t(u32
,
2544 NVME_MAX_KB_SZ
<< 1, dma_max_mapping_size(dev
->dev
) >> 9);
2545 dev
->ctrl
.max_segments
= NVME_MAX_SEGS
;
2548 * Don't limit the IOMMU merged segment size.
2550 dma_set_max_seg_size(dev
->dev
, 0xffffffff);
2552 mutex_unlock(&dev
->shutdown_lock
);
2555 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2556 * initializing procedure here.
2558 if (!nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_CONNECTING
)) {
2559 dev_warn(dev
->ctrl
.device
,
2560 "failed to mark controller CONNECTING\n");
2565 result
= nvme_init_identify(&dev
->ctrl
);
2569 if (dev
->ctrl
.oacs
& NVME_CTRL_OACS_SEC_SUPP
) {
2570 if (!dev
->ctrl
.opal_dev
)
2571 dev
->ctrl
.opal_dev
=
2572 init_opal_dev(&dev
->ctrl
, &nvme_sec_submit
);
2573 else if (was_suspend
)
2574 opal_unlock_from_suspend(dev
->ctrl
.opal_dev
);
2576 free_opal_dev(dev
->ctrl
.opal_dev
);
2577 dev
->ctrl
.opal_dev
= NULL
;
2580 if (dev
->ctrl
.oacs
& NVME_CTRL_OACS_DBBUF_SUPP
) {
2581 result
= nvme_dbbuf_dma_alloc(dev
);
2584 "unable to allocate dma for dbbuf\n");
2587 if (dev
->ctrl
.hmpre
) {
2588 result
= nvme_setup_host_mem(dev
);
2593 result
= nvme_setup_io_queues(dev
);
2598 * Keep the controller around but remove all namespaces if we don't have
2599 * any working I/O queue.
2601 if (dev
->online_queues
< 2) {
2602 dev_warn(dev
->ctrl
.device
, "IO queues not created\n");
2603 nvme_kill_queues(&dev
->ctrl
);
2604 nvme_remove_namespaces(&dev
->ctrl
);
2605 nvme_free_tagset(dev
);
2607 nvme_start_queues(&dev
->ctrl
);
2608 nvme_wait_freeze(&dev
->ctrl
);
2610 nvme_unfreeze(&dev
->ctrl
);
2614 * If only admin queue live, keep it to do further investigation or
2617 if (!nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_LIVE
)) {
2618 dev_warn(dev
->ctrl
.device
,
2619 "failed to mark controller live state\n");
2624 nvme_start_ctrl(&dev
->ctrl
);
2628 mutex_unlock(&dev
->shutdown_lock
);
2631 dev_warn(dev
->ctrl
.device
,
2632 "Removing after probe failure status: %d\n", result
);
2633 nvme_remove_dead_ctrl(dev
);
2636 static void nvme_remove_dead_ctrl_work(struct work_struct
*work
)
2638 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, remove_work
);
2639 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2641 if (pci_get_drvdata(pdev
))
2642 device_release_driver(&pdev
->dev
);
2643 nvme_put_ctrl(&dev
->ctrl
);
2646 static int nvme_pci_reg_read32(struct nvme_ctrl
*ctrl
, u32 off
, u32
*val
)
2648 *val
= readl(to_nvme_dev(ctrl
)->bar
+ off
);
2652 static int nvme_pci_reg_write32(struct nvme_ctrl
*ctrl
, u32 off
, u32 val
)
2654 writel(val
, to_nvme_dev(ctrl
)->bar
+ off
);
2658 static int nvme_pci_reg_read64(struct nvme_ctrl
*ctrl
, u32 off
, u64
*val
)
2660 *val
= lo_hi_readq(to_nvme_dev(ctrl
)->bar
+ off
);
2664 static int nvme_pci_get_address(struct nvme_ctrl
*ctrl
, char *buf
, int size
)
2666 struct pci_dev
*pdev
= to_pci_dev(to_nvme_dev(ctrl
)->dev
);
2668 return snprintf(buf
, size
, "%s\n", dev_name(&pdev
->dev
));
2671 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops
= {
2673 .module
= THIS_MODULE
,
2674 .flags
= NVME_F_METADATA_SUPPORTED
|
2676 .reg_read32
= nvme_pci_reg_read32
,
2677 .reg_write32
= nvme_pci_reg_write32
,
2678 .reg_read64
= nvme_pci_reg_read64
,
2679 .free_ctrl
= nvme_pci_free_ctrl
,
2680 .submit_async_event
= nvme_pci_submit_async_event
,
2681 .get_address
= nvme_pci_get_address
,
2684 static int nvme_dev_map(struct nvme_dev
*dev
)
2686 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2688 if (pci_request_mem_regions(pdev
, "nvme"))
2691 if (nvme_remap_bar(dev
, NVME_REG_DBS
+ 4096))
2696 pci_release_mem_regions(pdev
);
2700 static unsigned long check_vendor_combination_bug(struct pci_dev
*pdev
)
2702 if (pdev
->vendor
== 0x144d && pdev
->device
== 0xa802) {
2704 * Several Samsung devices seem to drop off the PCIe bus
2705 * randomly when APST is on and uses the deepest sleep state.
2706 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2707 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2708 * 950 PRO 256GB", but it seems to be restricted to two Dell
2711 if (dmi_match(DMI_SYS_VENDOR
, "Dell Inc.") &&
2712 (dmi_match(DMI_PRODUCT_NAME
, "XPS 15 9550") ||
2713 dmi_match(DMI_PRODUCT_NAME
, "Precision 5510")))
2714 return NVME_QUIRK_NO_DEEPEST_PS
;
2715 } else if (pdev
->vendor
== 0x144d && pdev
->device
== 0xa804) {
2717 * Samsung SSD 960 EVO drops off the PCIe bus after system
2718 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2719 * within few minutes after bootup on a Coffee Lake board -
2722 if (dmi_match(DMI_BOARD_VENDOR
, "ASUSTeK COMPUTER INC.") &&
2723 (dmi_match(DMI_BOARD_NAME
, "PRIME B350M-A") ||
2724 dmi_match(DMI_BOARD_NAME
, "PRIME Z370-A")))
2725 return NVME_QUIRK_NO_APST
;
2726 } else if ((pdev
->vendor
== 0x144d && (pdev
->device
== 0xa801 ||
2727 pdev
->device
== 0xa808 || pdev
->device
== 0xa809)) ||
2728 (pdev
->vendor
== 0x1e0f && pdev
->device
== 0x0001)) {
2730 * Forcing to use host managed nvme power settings for
2731 * lowest idle power with quick resume latency on
2732 * Samsung and Toshiba SSDs based on suspend behavior
2733 * on Coffee Lake board for LENOVO C640
2735 if ((dmi_match(DMI_BOARD_VENDOR
, "LENOVO")) &&
2736 dmi_match(DMI_BOARD_NAME
, "LNVNB161216"))
2737 return NVME_QUIRK_SIMPLE_SUSPEND
;
2743 static void nvme_async_probe(void *data
, async_cookie_t cookie
)
2745 struct nvme_dev
*dev
= data
;
2747 flush_work(&dev
->ctrl
.reset_work
);
2748 flush_work(&dev
->ctrl
.scan_work
);
2749 nvme_put_ctrl(&dev
->ctrl
);
2752 static int nvme_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
2754 int node
, result
= -ENOMEM
;
2755 struct nvme_dev
*dev
;
2756 unsigned long quirks
= id
->driver_data
;
2759 node
= dev_to_node(&pdev
->dev
);
2760 if (node
== NUMA_NO_NODE
)
2761 set_dev_node(&pdev
->dev
, first_memory_node
);
2763 dev
= kzalloc_node(sizeof(*dev
), GFP_KERNEL
, node
);
2767 dev
->queues
= kcalloc_node(max_queue_count(), sizeof(struct nvme_queue
),
2772 dev
->dev
= get_device(&pdev
->dev
);
2773 pci_set_drvdata(pdev
, dev
);
2775 result
= nvme_dev_map(dev
);
2779 INIT_WORK(&dev
->ctrl
.reset_work
, nvme_reset_work
);
2780 INIT_WORK(&dev
->remove_work
, nvme_remove_dead_ctrl_work
);
2781 mutex_init(&dev
->shutdown_lock
);
2783 result
= nvme_setup_prp_pools(dev
);
2787 quirks
|= check_vendor_combination_bug(pdev
);
2790 * Double check that our mempool alloc size will cover the biggest
2791 * command we support.
2793 alloc_size
= nvme_pci_iod_alloc_size(dev
, NVME_MAX_KB_SZ
,
2794 NVME_MAX_SEGS
, true);
2795 WARN_ON_ONCE(alloc_size
> PAGE_SIZE
);
2797 dev
->iod_mempool
= mempool_create_node(1, mempool_kmalloc
,
2799 (void *) alloc_size
,
2801 if (!dev
->iod_mempool
) {
2806 result
= nvme_init_ctrl(&dev
->ctrl
, &pdev
->dev
, &nvme_pci_ctrl_ops
,
2809 goto release_mempool
;
2811 dev_info(dev
->ctrl
.device
, "pci function %s\n", dev_name(&pdev
->dev
));
2813 nvme_reset_ctrl(&dev
->ctrl
);
2814 async_schedule(nvme_async_probe
, dev
);
2819 mempool_destroy(dev
->iod_mempool
);
2821 nvme_release_prp_pools(dev
);
2823 nvme_dev_unmap(dev
);
2825 put_device(dev
->dev
);
2832 static void nvme_reset_prepare(struct pci_dev
*pdev
)
2834 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2837 * We don't need to check the return value from waiting for the reset
2838 * state as pci_dev device lock is held, making it impossible to race
2841 nvme_disable_prepare_reset(dev
, false);
2842 nvme_sync_queues(&dev
->ctrl
);
2845 static void nvme_reset_done(struct pci_dev
*pdev
)
2847 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2849 if (!nvme_try_sched_reset(&dev
->ctrl
))
2850 flush_work(&dev
->ctrl
.reset_work
);
2853 static void nvme_shutdown(struct pci_dev
*pdev
)
2855 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2856 nvme_disable_prepare_reset(dev
, true);
2860 * The driver's remove may be called on a device in a partially initialized
2861 * state. This function must not have any dependencies on the device state in
2864 static void nvme_remove(struct pci_dev
*pdev
)
2866 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2868 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DELETING
);
2869 pci_set_drvdata(pdev
, NULL
);
2871 if (!pci_device_is_present(pdev
)) {
2872 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DEAD
);
2873 nvme_dev_disable(dev
, true);
2874 nvme_dev_remove_admin(dev
);
2877 flush_work(&dev
->ctrl
.reset_work
);
2878 nvme_stop_ctrl(&dev
->ctrl
);
2879 nvme_remove_namespaces(&dev
->ctrl
);
2880 nvme_dev_disable(dev
, true);
2881 nvme_release_cmb(dev
);
2882 nvme_free_host_mem(dev
);
2883 nvme_dev_remove_admin(dev
);
2884 nvme_free_queues(dev
, 0);
2885 nvme_release_prp_pools(dev
);
2886 nvme_dev_unmap(dev
);
2887 nvme_uninit_ctrl(&dev
->ctrl
);
2890 #ifdef CONFIG_PM_SLEEP
2891 static int nvme_get_power_state(struct nvme_ctrl
*ctrl
, u32
*ps
)
2893 return nvme_get_features(ctrl
, NVME_FEAT_POWER_MGMT
, 0, NULL
, 0, ps
);
2896 static int nvme_set_power_state(struct nvme_ctrl
*ctrl
, u32 ps
)
2898 return nvme_set_features(ctrl
, NVME_FEAT_POWER_MGMT
, ps
, NULL
, 0, NULL
);
2901 static int nvme_resume(struct device
*dev
)
2903 struct nvme_dev
*ndev
= pci_get_drvdata(to_pci_dev(dev
));
2904 struct nvme_ctrl
*ctrl
= &ndev
->ctrl
;
2906 if (ndev
->last_ps
== U32_MAX
||
2907 nvme_set_power_state(ctrl
, ndev
->last_ps
) != 0)
2908 return nvme_try_sched_reset(&ndev
->ctrl
);
2912 static int nvme_suspend(struct device
*dev
)
2914 struct pci_dev
*pdev
= to_pci_dev(dev
);
2915 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2916 struct nvme_ctrl
*ctrl
= &ndev
->ctrl
;
2919 ndev
->last_ps
= U32_MAX
;
2922 * The platform does not remove power for a kernel managed suspend so
2923 * use host managed nvme power settings for lowest idle power if
2924 * possible. This should have quicker resume latency than a full device
2925 * shutdown. But if the firmware is involved after the suspend or the
2926 * device does not support any non-default power states, shut down the
2929 * If ASPM is not enabled for the device, shut down the device and allow
2930 * the PCI bus layer to put it into D3 in order to take the PCIe link
2931 * down, so as to allow the platform to achieve its minimum low-power
2932 * state (which may not be possible if the link is up).
2934 if (pm_suspend_via_firmware() || !ctrl
->npss
||
2935 !pcie_aspm_enabled(pdev
) ||
2936 (ndev
->ctrl
.quirks
& NVME_QUIRK_SIMPLE_SUSPEND
))
2937 return nvme_disable_prepare_reset(ndev
, true);
2939 nvme_start_freeze(ctrl
);
2940 nvme_wait_freeze(ctrl
);
2941 nvme_sync_queues(ctrl
);
2943 if (ctrl
->state
!= NVME_CTRL_LIVE
)
2946 ret
= nvme_get_power_state(ctrl
, &ndev
->last_ps
);
2951 * A saved state prevents pci pm from generically controlling the
2952 * device's power. If we're using protocol specific settings, we don't
2953 * want pci interfering.
2955 pci_save_state(pdev
);
2957 ret
= nvme_set_power_state(ctrl
, ctrl
->npss
);
2962 /* discard the saved state */
2963 pci_load_saved_state(pdev
, NULL
);
2966 * Clearing npss forces a controller reset on resume. The
2967 * correct value will be rediscovered then.
2969 ret
= nvme_disable_prepare_reset(ndev
, true);
2973 nvme_unfreeze(ctrl
);
2977 static int nvme_simple_suspend(struct device
*dev
)
2979 struct nvme_dev
*ndev
= pci_get_drvdata(to_pci_dev(dev
));
2980 return nvme_disable_prepare_reset(ndev
, true);
2983 static int nvme_simple_resume(struct device
*dev
)
2985 struct pci_dev
*pdev
= to_pci_dev(dev
);
2986 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2988 return nvme_try_sched_reset(&ndev
->ctrl
);
2991 static const struct dev_pm_ops nvme_dev_pm_ops
= {
2992 .suspend
= nvme_suspend
,
2993 .resume
= nvme_resume
,
2994 .freeze
= nvme_simple_suspend
,
2995 .thaw
= nvme_simple_resume
,
2996 .poweroff
= nvme_simple_suspend
,
2997 .restore
= nvme_simple_resume
,
2999 #endif /* CONFIG_PM_SLEEP */
3001 static pci_ers_result_t
nvme_error_detected(struct pci_dev
*pdev
,
3002 pci_channel_state_t state
)
3004 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
3007 * A frozen channel requires a reset. When detected, this method will
3008 * shutdown the controller to quiesce. The controller will be restarted
3009 * after the slot reset through driver's slot_reset callback.
3012 case pci_channel_io_normal
:
3013 return PCI_ERS_RESULT_CAN_RECOVER
;
3014 case pci_channel_io_frozen
:
3015 dev_warn(dev
->ctrl
.device
,
3016 "frozen state error detected, reset controller\n");
3017 nvme_dev_disable(dev
, false);
3018 return PCI_ERS_RESULT_NEED_RESET
;
3019 case pci_channel_io_perm_failure
:
3020 dev_warn(dev
->ctrl
.device
,
3021 "failure state error detected, request disconnect\n");
3022 return PCI_ERS_RESULT_DISCONNECT
;
3024 return PCI_ERS_RESULT_NEED_RESET
;
3027 static pci_ers_result_t
nvme_slot_reset(struct pci_dev
*pdev
)
3029 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
3031 dev_info(dev
->ctrl
.device
, "restart after slot reset\n");
3032 pci_restore_state(pdev
);
3033 nvme_reset_ctrl(&dev
->ctrl
);
3034 return PCI_ERS_RESULT_RECOVERED
;
3037 static void nvme_error_resume(struct pci_dev
*pdev
)
3039 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
3041 flush_work(&dev
->ctrl
.reset_work
);
3044 static const struct pci_error_handlers nvme_err_handler
= {
3045 .error_detected
= nvme_error_detected
,
3046 .slot_reset
= nvme_slot_reset
,
3047 .resume
= nvme_error_resume
,
3048 .reset_prepare
= nvme_reset_prepare
,
3049 .reset_done
= nvme_reset_done
,
3052 static const struct pci_device_id nvme_id_table
[] = {
3053 { PCI_VDEVICE(INTEL
, 0x0953),
3054 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
3055 NVME_QUIRK_DEALLOCATE_ZEROES
, },
3056 { PCI_VDEVICE(INTEL
, 0x0a53),
3057 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
3058 NVME_QUIRK_DEALLOCATE_ZEROES
, },
3059 { PCI_VDEVICE(INTEL
, 0x0a54),
3060 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
3061 NVME_QUIRK_DEALLOCATE_ZEROES
, },
3062 { PCI_VDEVICE(INTEL
, 0x0a55),
3063 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
3064 NVME_QUIRK_DEALLOCATE_ZEROES
, },
3065 { PCI_VDEVICE(INTEL
, 0xf1a5), /* Intel 600P/P3100 */
3066 .driver_data
= NVME_QUIRK_NO_DEEPEST_PS
|
3067 NVME_QUIRK_MEDIUM_PRIO_SQ
|
3068 NVME_QUIRK_NO_TEMP_THRESH_CHANGE
},
3069 { PCI_VDEVICE(INTEL
, 0xf1a6), /* Intel 760p/Pro 7600p */
3070 .driver_data
= NVME_QUIRK_IGNORE_DEV_SUBNQN
, },
3071 { PCI_VDEVICE(INTEL
, 0x5845), /* Qemu emulated controller */
3072 .driver_data
= NVME_QUIRK_IDENTIFY_CNS
|
3073 NVME_QUIRK_DISABLE_WRITE_ZEROES
, },
3074 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3075 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
3076 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3077 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
3078 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3079 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
3080 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3081 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
3082 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3083 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
3084 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3085 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
3086 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
3087 .driver_data
= NVME_QUIRK_LIGHTNVM
, },
3088 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
3089 .driver_data
= NVME_QUIRK_LIGHTNVM
, },
3090 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
3091 .driver_data
= NVME_QUIRK_LIGHTNVM
, },
3092 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3093 .driver_data
= NVME_QUIRK_IGNORE_DEV_SUBNQN
, },
3094 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3095 .driver_data
= NVME_QUIRK_NO_DEEPEST_PS
|
3096 NVME_QUIRK_IGNORE_DEV_SUBNQN
, },
3097 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
3098 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2001),
3099 .driver_data
= NVME_QUIRK_SINGLE_VECTOR
},
3100 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2003) },
3101 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2005),
3102 .driver_data
= NVME_QUIRK_SINGLE_VECTOR
|
3103 NVME_QUIRK_128_BYTES_SQES
|
3104 NVME_QUIRK_SHARED_TAGS
},
3107 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
3109 static struct pci_driver nvme_driver
= {
3111 .id_table
= nvme_id_table
,
3112 .probe
= nvme_probe
,
3113 .remove
= nvme_remove
,
3114 .shutdown
= nvme_shutdown
,
3115 #ifdef CONFIG_PM_SLEEP
3117 .pm
= &nvme_dev_pm_ops
,
3120 .sriov_configure
= pci_sriov_configure_simple
,
3121 .err_handler
= &nvme_err_handler
,
3124 static int __init
nvme_init(void)
3126 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
3127 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
3128 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
3129 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS
< 2);
3131 write_queues
= min(write_queues
, num_possible_cpus());
3132 poll_queues
= min(poll_queues
, num_possible_cpus());
3133 return pci_register_driver(&nvme_driver
);
3136 static void __exit
nvme_exit(void)
3138 pci_unregister_driver(&nvme_driver
);
3139 flush_workqueue(nvme_wq
);
3142 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3143 MODULE_LICENSE("GPL");
3144 MODULE_VERSION("1.0");
3145 module_init(nvme_init
);
3146 module_exit(nvme_exit
);