drivers/pch/pch7.c

   1 /*
   2  * Copyright (C) 2014 Google, Inc
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <pch.h>
  10
  11 #define GPIO_BASE       0x44
  12 #define BIOS_CTRL       0xd8
  13
  14 static int pch7_get_spi_base(struct udevice *dev, ulong *sbasep)
  15 {
  16         u32 rcba;
  17
  18         dm_pci_read_config32(dev, PCH_RCBA, &rcba);
  19         /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
  20         rcba = rcba & 0xffffc000;
  21         *sbasep = rcba + 0x3020;
  22
  23         return 0;
  24 }
  25
  26 static int pch7_set_spi_protect(struct udevice *dev, bool protect)
  27 {
  28         uint8_t bios_cntl;
  29
  30         /* Adjust the BIOS write protect to dis/allow write commands */
  31         dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl);
  32         if (protect)
  33                 bios_cntl &= ~BIOS_CTRL_BIOSWE;
  34         else
  35                 bios_cntl |= BIOS_CTRL_BIOSWE;
  36         dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl);
  37
  38         return 0;
  39 }
  40
  41 static int pch7_get_gpio_base(struct udevice *dev, u32 *gbasep)
  42 {
  43         u32 base;
  44
  45         /*
  46          * GPIO_BASE moved to its current offset with ICH6, but prior to
  47          * that it was unused (or undocumented). Check that it looks
  48          * okay: not all ones or zeros.
  49          *
  50          * Note we don't need check bit0 here, because the Tunnel Creek
  51          * GPIO base address register bit0 is reserved (read returns 0),
  52          * while on the Ivybridge the bit0 is used to indicate it is an
  53          * I/O space.
  54          */
  55         dm_pci_read_config32(dev, GPIO_BASE, &base);
  56         if (base == 0x00000000 || base == 0xffffffff) {
  57                 debug("%s: unexpected BASE value\n", __func__);
  58                 return -ENODEV;
  59         }
  60
  61         /*
  62          * Okay, I guess we're looking at the right device. The actual
  63          * GPIO registers are in the PCI device's I/O space, starting
  64          * at the offset that we just read. Bit 0 indicates that it's
  65          * an I/O address, not a memory address, so mask that off.
  66          */
  67         *gbasep = base & 1 ? base & ~3 : base & ~15;
  68
  69         return 0;
  70 }
  71
  72 static const struct pch_ops pch7_ops = {
  73         .get_spi_base   = pch7_get_spi_base,
  74         .set_spi_protect = pch7_set_spi_protect,
  75         .get_gpio_base  = pch7_get_gpio_base,
  76 };
  77
  78 static const struct udevice_id pch7_ids[] = {
  79         { .compatible = "intel,pch7" },
  80         { }
  81 };
  82
  83 U_BOOT_DRIVER(pch7_drv) = {
  84         .name           = "intel-pch7",
  85         .id             = UCLASS_PCH,
  86         .of_match       = pch7_ids,
  87         .ops            = &pch7_ops,
  88 };