]>
git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/pch/pch9.c
2 * Copyright (C) 2014 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
11 #define GPIO_BASE 0x48
13 #define SBASE_ADDR 0x54
15 static int pch9_get_spi_base(struct udevice
*dev
, ulong
*sbasep
)
19 dm_pci_read_config32(dev
, SBASE_ADDR
, &sbase_addr
);
20 *sbasep
= sbase_addr
& 0xfffffe00;
25 static int pch9_get_gpio_base(struct udevice
*dev
, u32
*gbasep
)
30 * GPIO_BASE moved to its current offset with ICH6, but prior to
31 * that it was unused (or undocumented). Check that it looks
32 * okay: not all ones or zeros.
34 * Note we don't need check bit0 here, because the Tunnel Creek
35 * GPIO base address register bit0 is reserved (read returns 0),
36 * while on the Ivybridge the bit0 is used to indicate it is an
39 dm_pci_read_config32(dev
, GPIO_BASE
, &base
);
40 if (base
== 0x00000000 || base
== 0xffffffff) {
41 debug("%s: unexpected BASE value\n", __func__
);
46 * Okay, I guess we're looking at the right device. The actual
47 * GPIO registers are in the PCI device's I/O space, starting
48 * at the offset that we just read. Bit 0 indicates that it's
49 * an I/O address, not a memory address, so mask that off.
51 *gbasep
= base
& 1 ? base
& ~3 : base
& ~15;
56 static int pch9_get_io_base(struct udevice
*dev
, u32
*iobasep
)
60 dm_pci_read_config32(dev
, IO_BASE
, &base
);
61 if (base
== 0x00000000 || base
== 0xffffffff) {
62 debug("%s: unexpected BASE value\n", __func__
);
66 *iobasep
= base
& 1 ? base
& ~3 : base
& ~15;
71 static const struct pch_ops pch9_ops
= {
72 .get_spi_base
= pch9_get_spi_base
,
73 .get_gpio_base
= pch9_get_gpio_base
,
74 .get_io_base
= pch9_get_io_base
,
77 static const struct udevice_id pch9_ids
[] = {
78 { .compatible
= "intel,pch9" },
82 U_BOOT_DRIVER(pch9_drv
) = {