2 * Copyright 2007-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/fsl_serdes.h>
11 DECLARE_GLOBAL_DATA_PTR
;
14 * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
16 * Initialize controller and call the common driver/pci pci_hose_scan to
17 * scan for bridges and devices.
19 * Hose fields which need to be pre-initialized by board specific code:
29 #include <asm/fsl_pci.h>
31 /* Freescale-specific PCI config registers */
32 #define FSL_PCI_PBFR 0x44
33 #define FSL_PCIE_CAP_ID 0x4c
34 #define FSL_PCIE_CFG_RDY 0x4b0
35 #define FSL_PROG_IF_AGENT 0x1
37 #ifndef CONFIG_SYS_PCI_MEMORY_BUS
38 #define CONFIG_SYS_PCI_MEMORY_BUS 0
41 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS
42 #define CONFIG_SYS_PCI_MEMORY_PHYS 0
45 #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
46 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
49 /* Setup one inbound ATMU window.
51 * We let the caller decide what the window size should be
53 static void set_inbound_window(volatile pit_t
*pi
,
57 u32 sz
= (__ilog2_u64(size
) - 1);
58 u32 flag
= PIWAR_EN
| PIWAR_LOCAL
|
59 PIWAR_READ_SNOOP
| PIWAR_WRITE_SNOOP
;
61 out_be32(&pi
->pitar
, r
->phys_start
>> 12);
62 out_be32(&pi
->piwbar
, r
->bus_start
>> 12);
63 #ifdef CONFIG_SYS_PCI_64BIT
64 out_be32(&pi
->piwbear
, r
->bus_start
>> 44);
66 out_be32(&pi
->piwbear
, 0);
68 if (r
->flags
& PCI_REGION_PREFETCH
)
70 out_be32(&pi
->piwar
, flag
| sz
);
73 int fsl_setup_hose(struct pci_controller
*hose
, unsigned long addr
)
75 volatile ccsr_fsl_pci_t
*pci
= (ccsr_fsl_pci_t
*) addr
;
77 /* Reset hose to make sure its in a clean state */
78 memset(hose
, 0, sizeof(struct pci_controller
));
80 pci_setup_indirect(hose
, (u32
)&pci
->cfg_addr
, (u32
)&pci
->cfg_data
);
82 return fsl_is_pci_agent(hose
);
85 static int fsl_pci_setup_inbound_windows(struct pci_controller
*hose
,
86 u64 out_lo
, u8 pcie_cap
,
89 struct pci_region
*r
= hose
->regions
+ hose
->region_count
;
90 u64 sz
= min((u64
)gd
->ram_size
, (1ull << 32));
92 phys_addr_t phys_start
= CONFIG_SYS_PCI_MEMORY_PHYS
;
93 pci_addr_t bus_start
= CONFIG_SYS_PCI_MEMORY_BUS
;
96 /* we have no space available for inbound memory mapping */
97 if (bus_start
> out_lo
) {
98 printf ("no space for inbound mapping of memory\n");
103 if ((bus_start
+ sz
) > out_lo
) {
104 sz
= out_lo
- bus_start
;
105 debug ("limiting size to %llx\n", sz
);
108 pci_sz
= 1ull << __ilog2_u64(sz
);
110 * we can overlap inbound/outbound windows on PCI-E since RX & TX
113 if ((pcie_cap
== PCI_CAP_ID_EXP
) && (pci_sz
< sz
)) {
114 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
115 (u64
)bus_start
, (u64
)phys_start
, (u64
)sz
);
116 pci_set_region(r
, bus_start
, phys_start
, sz
,
117 PCI_REGION_MEM
| PCI_REGION_SYS_MEMORY
|
118 PCI_REGION_PREFETCH
);
120 /* if we aren't an exact power of two match, pci_sz is smaller
121 * round it up to the next power of two. We report the actual
122 * size to pci region tracking.
125 sz
= 2ull << __ilog2_u64(sz
);
127 set_inbound_window(pi
--, r
++, sz
);
128 sz
= 0; /* make sure we dont set the R2 window */
130 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
131 (u64
)bus_start
, (u64
)phys_start
, (u64
)pci_sz
);
132 pci_set_region(r
, bus_start
, phys_start
, pci_sz
,
133 PCI_REGION_MEM
| PCI_REGION_SYS_MEMORY
|
134 PCI_REGION_PREFETCH
);
135 set_inbound_window(pi
--, r
++, pci_sz
);
139 phys_start
+= pci_sz
;
141 pci_sz
= 1ull << __ilog2_u64(sz
);
143 debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
144 (u64
)bus_start
, (u64
)phys_start
, (u64
)pci_sz
);
145 pci_set_region(r
, bus_start
, phys_start
, pci_sz
,
146 PCI_REGION_MEM
| PCI_REGION_SYS_MEMORY
|
147 PCI_REGION_PREFETCH
);
148 set_inbound_window(pi
--, r
++, pci_sz
);
151 phys_start
+= pci_sz
;
155 #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
157 * On 64-bit capable systems, set up a mapping for all of DRAM
158 * in high pci address space.
160 pci_sz
= 1ull << __ilog2_u64(gd
->ram_size
);
161 /* round up to the next largest power of two */
162 if (gd
->ram_size
> pci_sz
)
163 pci_sz
= 1ull << (__ilog2_u64(gd
->ram_size
) + 1);
164 debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
165 (u64
)CONFIG_SYS_PCI64_MEMORY_BUS
,
166 (u64
)CONFIG_SYS_PCI_MEMORY_PHYS
,
169 CONFIG_SYS_PCI64_MEMORY_BUS
,
170 CONFIG_SYS_PCI_MEMORY_PHYS
,
172 PCI_REGION_MEM
| PCI_REGION_SYS_MEMORY
|
173 PCI_REGION_PREFETCH
);
174 set_inbound_window(pi
--, r
++, pci_sz
);
176 pci_sz
= 1ull << __ilog2_u64(sz
);
178 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
179 (u64
)bus_start
, (u64
)phys_start
, (u64
)pci_sz
);
180 pci_set_region(r
, bus_start
, phys_start
, pci_sz
,
181 PCI_REGION_MEM
| PCI_REGION_SYS_MEMORY
|
182 PCI_REGION_PREFETCH
);
185 phys_start
+= pci_sz
;
186 set_inbound_window(pi
--, r
++, pci_sz
);
190 #ifdef CONFIG_PHYS_64BIT
191 if (sz
&& (((u64
)gd
->ram_size
) < (1ull << 32)))
192 printf("Was not able to map all of memory via "
193 "inbound windows -- %lld remaining\n", sz
);
196 hose
->region_count
= r
- hose
->regions
;
201 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
202 static void fsl_pcie_boot_master(pit_t
*pi
)
204 /* configure inbound window for slave's u-boot image */
205 debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
206 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
207 (u64
)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS
,
208 (u64
)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1
,
209 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE
);
210 struct pci_region r_inbound
;
211 u32 sz_inbound
= __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE
)
213 pci_set_region(&r_inbound
,
214 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1
,
215 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS
,
217 PCI_REGION_MEM
| PCI_REGION_SYS_MEMORY
);
219 set_inbound_window(pi
--, &r_inbound
,
220 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE
);
222 /* configure inbound window for slave's u-boot image */
223 debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
224 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
225 (u64
)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS
,
226 (u64
)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2
,
227 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE
);
228 pci_set_region(&r_inbound
,
229 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2
,
230 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS
,
232 PCI_REGION_MEM
| PCI_REGION_SYS_MEMORY
);
234 set_inbound_window(pi
--, &r_inbound
,
235 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE
);
237 /* configure inbound window for slave's ucode and ENV */
238 debug("PCIEBOOT - MASTER: Inbound window for slave's "
240 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
241 (u64
)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS
,
242 (u64
)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS
,
243 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE
);
244 sz_inbound
= __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE
)
246 pci_set_region(&r_inbound
,
247 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS
,
248 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS
,
250 PCI_REGION_MEM
| PCI_REGION_SYS_MEMORY
);
252 set_inbound_window(pi
--, &r_inbound
,
253 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE
);
256 static void fsl_pcie_boot_master_release_slave(int port
)
258 unsigned long release_addr
;
260 /* now release slave's core 0 */
263 release_addr
= CONFIG_SYS_PCIE1_MEM_VIRT
264 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET
;
266 #ifdef CONFIG_SYS_PCIE2_MEM_VIRT
268 release_addr
= CONFIG_SYS_PCIE2_MEM_VIRT
269 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET
;
272 #ifdef CONFIG_SYS_PCIE3_MEM_VIRT
274 release_addr
= CONFIG_SYS_PCIE3_MEM_VIRT
275 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET
;
282 if (release_addr
!= 0) {
283 out_be32((void *)release_addr
,
284 CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK
);
285 debug("PCIEBOOT - MASTER: "
286 "Release slave successfully! Now the slave should start up!\n");
288 debug("PCIEBOOT - MASTER: "
289 "Release slave failed!\n");
294 void fsl_pci_init(struct pci_controller
*hose
, struct fsl_pci_info
*pci_info
)
296 u32 cfg_addr
= (u32
)&((ccsr_fsl_pci_t
*)pci_info
->regs
)->cfg_addr
;
297 u32 cfg_data
= (u32
)&((ccsr_fsl_pci_t
*)pci_info
->regs
)->cfg_data
;
301 int enabled
, r
, inbound
= 0;
304 volatile ccsr_fsl_pci_t
*pci
= (ccsr_fsl_pci_t
*)cfg_addr
;
305 struct pci_region
*reg
= hose
->regions
+ hose
->region_count
;
306 pci_dev_t dev
= PCI_BDF(hose
->first_busno
, 0, 0);
308 /* Initialize ATMU registers based on hose regions and flags */
309 volatile pot_t
*po
= &pci
->pot
[1]; /* skip 0 */
312 u64 out_hi
= 0, out_lo
= -1ULL;
313 u32 pcicsrbar
, pcicsrbar_sz
;
315 pci_setup_indirect(hose
, cfg_addr
, cfg_data
);
317 block_rev
= in_be32(&pci
->block_rev1
);
318 if (PEX_IP_BLK_REV_2_2
<= block_rev
) {
319 pi
= &pci
->pit
[2]; /* 0xDC0 */
321 pi
= &pci
->pit
[3]; /* 0xDE0 */
324 /* Handle setup of outbound windows first */
325 for (r
= 0; r
< hose
->region_count
; r
++) {
326 unsigned long flags
= hose
->regions
[r
].flags
;
327 u32 sz
= (__ilog2_u64((u64
)hose
->regions
[r
].size
) - 1);
329 flags
&= PCI_REGION_SYS_MEMORY
|PCI_REGION_TYPE
;
330 if (flags
!= PCI_REGION_SYS_MEMORY
) {
331 u64 start
= hose
->regions
[r
].bus_start
;
332 u64 end
= start
+ hose
->regions
[r
].size
;
334 out_be32(&po
->powbar
, hose
->regions
[r
].phys_start
>> 12);
335 out_be32(&po
->potar
, start
>> 12);
336 #ifdef CONFIG_SYS_PCI_64BIT
337 out_be32(&po
->potear
, start
>> 44);
339 out_be32(&po
->potear
, 0);
341 if (hose
->regions
[r
].flags
& PCI_REGION_IO
) {
342 out_be32(&po
->powar
, POWAR_EN
| sz
|
343 POWAR_IO_READ
| POWAR_IO_WRITE
);
345 out_be32(&po
->powar
, POWAR_EN
| sz
|
346 POWAR_MEM_READ
| POWAR_MEM_WRITE
);
347 out_lo
= min(start
, out_lo
);
348 out_hi
= max(end
, out_hi
);
353 debug("Outbound memory range: %llx:%llx\n", out_lo
, out_hi
);
355 /* setup PCSRBAR/PEXCSRBAR */
356 pci_hose_write_config_dword(hose
, dev
, PCI_BASE_ADDRESS_0
, 0xffffffff);
357 pci_hose_read_config_dword (hose
, dev
, PCI_BASE_ADDRESS_0
, &pcicsrbar_sz
);
358 pcicsrbar_sz
= ~pcicsrbar_sz
+ 1;
360 if (out_hi
< (0x100000000ull
- pcicsrbar_sz
) ||
361 (out_lo
> 0x100000000ull
))
362 pcicsrbar
= 0x100000000ull
- pcicsrbar_sz
;
364 pcicsrbar
= (out_lo
- pcicsrbar_sz
) & -pcicsrbar_sz
;
365 pci_hose_write_config_dword(hose
, dev
, PCI_BASE_ADDRESS_0
, pcicsrbar
);
367 out_lo
= min(out_lo
, (u64
)pcicsrbar
);
369 debug("PCICSRBAR @ 0x%x\n", pcicsrbar
);
371 pci_set_region(reg
++, pcicsrbar
, CONFIG_SYS_CCSRBAR_PHYS
,
372 pcicsrbar_sz
, PCI_REGION_SYS_MEMORY
);
373 hose
->region_count
++;
375 /* see if we are a PCIe or PCI controller */
376 pci_hose_read_config_byte(hose
, dev
, FSL_PCIE_CAP_ID
, &pcie_cap
);
378 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
379 /* boot from PCIE --master */
380 char *s
= getenv("bootmaster");
382 sprintf(pcie
, "PCIE%d", pci_info
->pci_num
);
384 if (s
&& (strcmp(s
, pcie
) == 0)) {
385 debug("PCIEBOOT - MASTER: Master port [ %d ] for pcie boot.\n",
387 fsl_pcie_boot_master((pit_t
*)pi
);
390 inbound
= fsl_pci_setup_inbound_windows(hose
,
391 out_lo
, pcie_cap
, pi
);
395 inbound
= fsl_pci_setup_inbound_windows(hose
, out_lo
, pcie_cap
, pi
);
398 for (r
= 0; r
< hose
->region_count
; r
++)
399 debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n", r
,
400 (u64
)hose
->regions
[r
].phys_start
,
401 (u64
)hose
->regions
[r
].bus_start
,
402 (u64
)hose
->regions
[r
].size
,
403 hose
->regions
[r
].flags
);
405 pci_register_hose(hose
);
406 pciauto_config_init(hose
); /* grab pci_{mem,prefetch,io} */
407 hose
->current_busno
= hose
->first_busno
;
409 out_be32(&pci
->pedr
, 0xffffffff); /* Clear any errors */
410 out_be32(&pci
->peer
, ~0x20140); /* Enable All Error Interrupts except
411 * - Master abort (pci)
412 * - Master PERR (pci)
415 pci_hose_read_config_dword(hose
, dev
, PCI_DCR
, &temp32
);
416 temp32
|= 0xf000e; /* set URR, FER, NFER (but not CER) */
417 pci_hose_write_config_dword(hose
, dev
, PCI_DCR
, temp32
);
419 #if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
421 pci_hose_read_config_dword(hose
, dev
, PCI_LCR
, &temp32
);
422 temp32
&= ~0x03; /* Disable ASPM */
423 pci_hose_write_config_dword(hose
, dev
, PCI_LCR
, temp32
);
426 if (pcie_cap
== PCI_CAP_ID_EXP
) {
427 pci_hose_read_config_word(hose
, dev
, PCI_LTSSM
, <ssm
);
428 enabled
= ltssm
>= PCI_LTSSM_L0
;
430 #ifdef CONFIG_FSL_PCIE_RESET
433 debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm
);
434 /* assert PCIe reset */
435 setbits_be32(&pci
->pdb_stat
, 0x08000000);
436 (void) in_be32(&pci
->pdb_stat
);
438 debug(" Asserting PCIe reset @%p = %x\n",
439 &pci
->pdb_stat
, in_be32(&pci
->pdb_stat
));
440 /* clear PCIe reset */
441 clrbits_be32(&pci
->pdb_stat
, 0x08000000);
443 for (i
=0; i
<100 && ltssm
< PCI_LTSSM_L0
; i
++) {
444 pci_hose_read_config_word(hose
, dev
, PCI_LTSSM
,
447 debug("....PCIe link error. "
448 "LTSSM=0x%02x.\n", ltssm
);
450 enabled
= ltssm
>= PCI_LTSSM_L0
;
452 /* we need to re-write the bar0 since a reset will
455 pci_hose_write_config_dword(hose
, dev
,
456 PCI_BASE_ADDRESS_0
, pcicsrbar
);
460 #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
462 serdes_corenet_t
*srds_regs
= (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR
;
463 temp32
= in_be32(&srds_regs
->srdspccr0
);
465 if ((temp32
>> 28) == 3) {
468 out_be32(&srds_regs
->srdspccr0
, 2 << 28);
469 setbits_be32(&pci
->pdb_stat
, 0x08000000);
470 in_be32(&pci
->pdb_stat
);
472 clrbits_be32(&pci
->pdb_stat
, 0x08000000);
474 for (i
=0; i
< 100 && ltssm
< PCI_LTSSM_L0
; i
++) {
475 pci_hose_read_config_word(hose
, dev
, PCI_LTSSM
, <ssm
);
478 enabled
= ltssm
>= PCI_LTSSM_L0
;
483 /* Let the user know there's no PCIe link */
484 printf("no link, regs @ 0x%lx\n", pci_info
->regs
);
485 hose
->last_busno
= hose
->first_busno
;
489 out_be32(&pci
->pme_msg_det
, 0xffffffff);
490 out_be32(&pci
->pme_msg_int_en
, 0xffffffff);
492 /* Print the negotiated PCIe link width */
493 pci_hose_read_config_word(hose
, dev
, PCI_LSR
, &temp16
);
494 printf("x%d, regs @ 0x%lx\n", (temp16
& 0x3f0 ) >> 4,
497 hose
->current_busno
++; /* Start scan with secondary */
498 pciauto_prescan_setup_bridge(hose
, dev
, hose
->current_busno
);
501 /* Use generic setup_device to initialize standard pci regs,
502 * but do not allocate any windows since any BAR found (such
503 * as PCSRBAR) is not in this cpu's memory space.
505 pciauto_setup_device(hose
, dev
, 0, hose
->pci_mem
,
506 hose
->pci_prefetch
, hose
->pci_io
);
509 pci_hose_read_config_word(hose
, dev
, PCI_COMMAND
, &temp16
);
510 pci_hose_write_config_word(hose
, dev
, PCI_COMMAND
,
511 temp16
| PCI_COMMAND_MEMORY
);
514 #ifndef CONFIG_PCI_NOSCAN
515 if (!fsl_is_pci_agent(hose
)) {
516 debug(" Scanning PCI bus %02x\n",
517 hose
->current_busno
);
518 hose
->last_busno
= pci_hose_scan_bus(hose
, hose
->current_busno
);
520 debug(" Not scanning PCI bus %02x. PI=%x\n",
521 hose
->current_busno
, temp8
);
522 hose
->last_busno
= hose
->current_busno
;
525 /* if we are PCIe - update limit regs and subordinate busno
526 * for the virtual P2P bridge
528 if (pcie_cap
== PCI_CAP_ID_EXP
) {
529 pciauto_postscan_setup_bridge(hose
, dev
, hose
->last_busno
);
532 hose
->last_busno
= hose
->current_busno
;
535 /* Clear all error indications */
536 if (pcie_cap
== PCI_CAP_ID_EXP
)
537 out_be32(&pci
->pme_msg_det
, 0xffffffff);
538 out_be32(&pci
->pedr
, 0xffffffff);
540 pci_hose_read_config_word (hose
, dev
, PCI_DSR
, &temp16
);
542 pci_hose_write_config_word(hose
, dev
, PCI_DSR
, 0xffff);
545 pci_hose_read_config_word (hose
, dev
, PCI_SEC_STATUS
, &temp16
);
547 pci_hose_write_config_word(hose
, dev
, PCI_SEC_STATUS
, 0xffff);
551 int fsl_is_pci_agent(struct pci_controller
*hose
)
554 pci_dev_t dev
= PCI_BDF(hose
->first_busno
, 0, 0);
556 pci_hose_read_config_byte(hose
, dev
, FSL_PCIE_CAP_ID
, &pcie_cap
);
557 if (pcie_cap
== PCI_CAP_ID_EXP
) {
560 pci_hose_read_config_byte(hose
, dev
, PCI_HEADER_TYPE
,
562 return (header_type
& 0x7f) == PCI_HEADER_TYPE_NORMAL
;
566 pci_hose_read_config_byte(hose
, dev
, PCI_CLASS_PROG
, &prog_if
);
567 return (prog_if
== FSL_PROG_IF_AGENT
);
571 int fsl_pci_init_port(struct fsl_pci_info
*pci_info
,
572 struct pci_controller
*hose
, int busno
)
574 volatile ccsr_fsl_pci_t
*pci
;
575 struct pci_region
*r
;
576 pci_dev_t dev
= PCI_BDF(busno
,0,0);
579 pci
= (ccsr_fsl_pci_t
*) pci_info
->regs
;
581 /* on non-PCIe controllers we don't have pme_msg_det so this code
582 * should do nothing since the read will return 0
584 if (in_be32(&pci
->pme_msg_det
)) {
585 out_be32(&pci
->pme_msg_det
, 0xffffffff);
586 debug (" with errors. Clearing. Now 0x%08x",
590 r
= hose
->regions
+ hose
->region_count
;
592 /* outbound memory */
606 hose
->region_count
= r
- hose
->regions
;
607 hose
->first_busno
= busno
;
609 fsl_pci_init(hose
, pci_info
);
611 if (fsl_is_pci_agent(hose
)) {
612 fsl_pci_config_unlock(hose
);
613 hose
->last_busno
= hose
->first_busno
;
614 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
616 /* boot from PCIE --master releases slave's core 0 */
617 char *s
= getenv("bootmaster");
619 sprintf(pcie
, "PCIE%d", pci_info
->pci_num
);
621 if (s
&& (strcmp(s
, pcie
) == 0))
622 fsl_pcie_boot_master_release_slave(pci_info
->pci_num
);
626 pci_hose_read_config_byte(hose
, dev
, FSL_PCIE_CAP_ID
, &pcie_cap
);
627 printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap
== PCI_CAP_ID_EXP
?
628 "e" : "", pci_info
->pci_num
,
629 hose
->first_busno
, hose
->last_busno
);
631 return(hose
->last_busno
+ 1);
634 /* Enable inbound PCI config cycles for agent/endpoint interface */
635 void fsl_pci_config_unlock(struct pci_controller
*hose
)
637 pci_dev_t dev
= PCI_BDF(hose
->first_busno
,0,0);
641 if (!fsl_is_pci_agent(hose
))
644 pci_hose_read_config_byte(hose
, dev
, FSL_PCIE_CAP_ID
, &pcie_cap
);
645 if (pcie_cap
!= 0x0) {
646 /* PCIe - set CFG_READY bit of Configuration Ready Register */
647 pci_hose_write_config_byte(hose
, dev
, FSL_PCIE_CFG_RDY
, 0x1);
649 /* PCI - clear ACL bit of PBFR */
650 pci_hose_read_config_word(hose
, dev
, FSL_PCI_PBFR
, &pbfr
);
652 pci_hose_write_config_word(hose
, dev
, FSL_PCI_PBFR
, pbfr
);
656 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || \
657 defined(CONFIG_PCIE3) || defined(CONFIG_PCIE4)
658 int fsl_configure_pcie(struct fsl_pci_info
*info
,
659 struct pci_controller
*hose
,
660 const char *connected
, int busno
)
664 set_next_law(info
->mem_phys
, law_size_bits(info
->mem_size
), info
->law
);
665 set_next_law(info
->io_phys
, law_size_bits(info
->io_size
), info
->law
);
667 is_endpoint
= fsl_setup_hose(hose
, info
->regs
);
668 printf("PCIe%u: %s", info
->pci_num
,
669 is_endpoint
? "Endpoint" : "Root Complex");
671 printf(" of %s", connected
);
674 return fsl_pci_init_port(info
, hose
, busno
);
677 #if defined(CONFIG_FSL_CORENET)
678 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
679 #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR3_PCIE1
680 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR3_PCIE2
681 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR3_PCIE3
682 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR3_PCIE4
684 #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1
685 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2
686 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3
687 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4
689 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
690 #elif defined(CONFIG_MPC85xx)
691 #define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE
692 #define _DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2
693 #define _DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3
694 #define _DEVDISR_PCIE4 0
695 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
696 #elif defined(CONFIG_MPC86xx)
697 #define _DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIE1
698 #define _DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIE2
699 #define _DEVDISR_PCIE3 0
700 #define _DEVDISR_PCIE4 0
701 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \
702 (&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
704 #error "No defines for DEVDISR_PCIE"
707 /* Implement a dummy function for those platforms w/o SERDES */
708 static const char *__board_serdes_name(enum srds_prtcl device
)
711 #ifdef CONFIG_SYS_PCIE1_NAME
713 return CONFIG_SYS_PCIE1_NAME
;
715 #ifdef CONFIG_SYS_PCIE2_NAME
717 return CONFIG_SYS_PCIE2_NAME
;
719 #ifdef CONFIG_SYS_PCIE3_NAME
721 return CONFIG_SYS_PCIE3_NAME
;
723 #ifdef CONFIG_SYS_PCIE4_NAME
725 return CONFIG_SYS_PCIE4_NAME
;
734 __attribute__((weak
, alias("__board_serdes_name"))) const char *
735 board_serdes_name(enum srds_prtcl device
);
737 static u32 devdisr_mask
[] = {
744 int fsl_pcie_init_ctrl(int busno
, u32 devdisr
, enum srds_prtcl dev
,
745 struct fsl_pci_info
*pci_info
)
747 struct pci_controller
*hose
;
748 int num
= dev
- PCIE1
;
750 hose
= calloc(1, sizeof(struct pci_controller
));
754 if (is_serdes_configured(dev
) && !(devdisr
& devdisr_mask
[num
])) {
755 busno
= fsl_configure_pcie(pci_info
, hose
,
756 board_serdes_name(dev
), busno
);
758 printf("PCIe%d: disabled\n", num
+ 1);
764 int fsl_pcie_init_board(int busno
)
766 struct fsl_pci_info pci_info
;
767 ccsr_gur_t
*gur
= (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR
;
771 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
772 addr
= &gur
->devdisr3
;
774 addr
= &gur
->devdisr
;
776 devdisr
= in_be32(addr
);
779 SET_STD_PCIE_INFO(pci_info
, 1);
780 busno
= fsl_pcie_init_ctrl(busno
, devdisr
, PCIE1
, &pci_info
);
782 setbits_be32(addr
, _DEVDISR_PCIE1
); /* disable */
786 SET_STD_PCIE_INFO(pci_info
, 2);
787 busno
= fsl_pcie_init_ctrl(busno
, devdisr
, PCIE2
, &pci_info
);
789 setbits_be32(addr
, _DEVDISR_PCIE2
); /* disable */
793 SET_STD_PCIE_INFO(pci_info
, 3);
794 busno
= fsl_pcie_init_ctrl(busno
, devdisr
, PCIE3
, &pci_info
);
796 setbits_be32(addr
, _DEVDISR_PCIE3
); /* disable */
800 SET_STD_PCIE_INFO(pci_info
, 4);
801 busno
= fsl_pcie_init_ctrl(busno
, devdisr
, PCIE4
, &pci_info
);
803 setbits_be32(addr
, _DEVDISR_PCIE4
); /* disable */
809 int fsl_pcie_init_ctrl(int busno
, u32 devdisr
, enum srds_prtcl dev
,
810 struct fsl_pci_info
*pci_info
)
815 int fsl_pcie_init_board(int busno
)
821 #ifdef CONFIG_OF_BOARD_SETUP
823 #include <fdt_support.h>
825 void ft_fsl_pci_setup(void *blob
, const char *pci_compat
,
826 unsigned long ctrl_addr
)
830 phys_addr_t p_ctrl_addr
= (phys_addr_t
)ctrl_addr
;
831 struct pci_controller
*hose
;
833 hose
= find_hose_by_cfg_addr((void *)(ctrl_addr
));
835 /* convert ctrl_addr to true physical address */
836 p_ctrl_addr
= (phys_addr_t
)ctrl_addr
- CONFIG_SYS_CCSRBAR
;
837 p_ctrl_addr
+= CONFIG_SYS_CCSRBAR_PHYS
;
839 off
= fdt_node_offset_by_compat_reg(blob
, pci_compat
, p_ctrl_addr
);
844 /* We assume a cfg_addr not being set means we didn't setup the controller */
845 if ((hose
== NULL
) || (hose
->cfg_addr
== NULL
)) {
846 fdt_del_node(blob
, off
);
849 bus_range
[1] = hose
->last_busno
- hose
->first_busno
;
850 fdt_setprop(blob
, off
, "bus-range", &bus_range
[0], 2*4);
851 fdt_pci_dma_ranges(blob
, off
, hose
);