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Minor Coding Style Cleanup.
[people/ms/u-boot.git] / drivers / pci / fsl_pci_init.c
1 /*
2 * Copyright 2007-2010 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 */
19
20 #include <common.h>
21 #include <malloc.h>
22 #include <asm/fsl_serdes.h>
23
24 DECLARE_GLOBAL_DATA_PTR;
25
26 /*
27 * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
28 *
29 * Initialize controller and call the common driver/pci pci_hose_scan to
30 * scan for bridges and devices.
31 *
32 * Hose fields which need to be pre-initialized by board specific code:
33 * regions[]
34 * first_busno
35 *
36 * Fields updated:
37 * last_busno
38 */
39
40 #include <pci.h>
41 #include <asm/io.h>
42 #include <asm/fsl_pci.h>
43
44 /* Freescale-specific PCI config registers */
45 #define FSL_PCI_PBFR 0x44
46 #define FSL_PCIE_CAP_ID 0x4c
47 #define FSL_PCIE_CFG_RDY 0x4b0
48 #define FSL_PROG_IF_AGENT 0x1
49
50 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
51 pci_dev_t dev, int sub_bus);
52 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
53 pci_dev_t dev, int sub_bus);
54 void pciauto_config_init(struct pci_controller *hose);
55
56 #ifndef CONFIG_SYS_PCI_MEMORY_BUS
57 #define CONFIG_SYS_PCI_MEMORY_BUS 0
58 #endif
59
60 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS
61 #define CONFIG_SYS_PCI_MEMORY_PHYS 0
62 #endif
63
64 #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
65 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
66 #endif
67
68 /* Setup one inbound ATMU window.
69 *
70 * We let the caller decide what the window size should be
71 */
72 static void set_inbound_window(volatile pit_t *pi,
73 struct pci_region *r,
74 u64 size)
75 {
76 u32 sz = (__ilog2_u64(size) - 1);
77 u32 flag = PIWAR_EN | PIWAR_LOCAL |
78 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
79
80 out_be32(&pi->pitar, r->phys_start >> 12);
81 out_be32(&pi->piwbar, r->bus_start >> 12);
82 #ifdef CONFIG_SYS_PCI_64BIT
83 out_be32(&pi->piwbear, r->bus_start >> 44);
84 #else
85 out_be32(&pi->piwbear, 0);
86 #endif
87 if (r->flags & PCI_REGION_PREFETCH)
88 flag |= PIWAR_PF;
89 out_be32(&pi->piwar, flag | sz);
90 }
91
92 int fsl_setup_hose(struct pci_controller *hose, unsigned long addr)
93 {
94 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr;
95
96 /* Reset hose to make sure its in a clean state */
97 memset(hose, 0, sizeof(struct pci_controller));
98
99 pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
100
101 return fsl_is_pci_agent(hose);
102 }
103
104 static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
105 u64 out_lo, u8 pcie_cap,
106 volatile pit_t *pi)
107 {
108 struct pci_region *r = hose->regions + hose->region_count;
109 u64 sz = min((u64)gd->ram_size, (1ull << 32));
110
111 phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
112 pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
113 pci_size_t pci_sz;
114
115 /* we have no space available for inbound memory mapping */
116 if (bus_start > out_lo) {
117 printf ("no space for inbound mapping of memory\n");
118 return 0;
119 }
120
121 /* limit size */
122 if ((bus_start + sz) > out_lo) {
123 sz = out_lo - bus_start;
124 debug ("limiting size to %llx\n", sz);
125 }
126
127 pci_sz = 1ull << __ilog2_u64(sz);
128 /*
129 * we can overlap inbound/outbound windows on PCI-E since RX & TX
130 * links a separate
131 */
132 if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) {
133 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
134 (u64)bus_start, (u64)phys_start, (u64)sz);
135 pci_set_region(r, bus_start, phys_start, sz,
136 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
137 PCI_REGION_PREFETCH);
138
139 /* if we aren't an exact power of two match, pci_sz is smaller
140 * round it up to the next power of two. We report the actual
141 * size to pci region tracking.
142 */
143 if (pci_sz != sz)
144 sz = 2ull << __ilog2_u64(sz);
145
146 set_inbound_window(pi--, r++, sz);
147 sz = 0; /* make sure we dont set the R2 window */
148 } else {
149 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
150 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
151 pci_set_region(r, bus_start, phys_start, pci_sz,
152 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
153 PCI_REGION_PREFETCH);
154 set_inbound_window(pi--, r++, pci_sz);
155
156 sz -= pci_sz;
157 bus_start += pci_sz;
158 phys_start += pci_sz;
159
160 pci_sz = 1ull << __ilog2_u64(sz);
161 if (sz) {
162 debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
163 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
164 pci_set_region(r, bus_start, phys_start, pci_sz,
165 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
166 PCI_REGION_PREFETCH);
167 set_inbound_window(pi--, r++, pci_sz);
168 sz -= pci_sz;
169 bus_start += pci_sz;
170 phys_start += pci_sz;
171 }
172 }
173
174 #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
175 /*
176 * On 64-bit capable systems, set up a mapping for all of DRAM
177 * in high pci address space.
178 */
179 pci_sz = 1ull << __ilog2_u64(gd->ram_size);
180 /* round up to the next largest power of two */
181 if (gd->ram_size > pci_sz)
182 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
183 debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
184 (u64)CONFIG_SYS_PCI64_MEMORY_BUS,
185 (u64)CONFIG_SYS_PCI_MEMORY_PHYS,
186 (u64)pci_sz);
187 pci_set_region(r,
188 CONFIG_SYS_PCI64_MEMORY_BUS,
189 CONFIG_SYS_PCI_MEMORY_PHYS,
190 pci_sz,
191 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
192 PCI_REGION_PREFETCH);
193 set_inbound_window(pi--, r++, pci_sz);
194 #else
195 pci_sz = 1ull << __ilog2_u64(sz);
196 if (sz) {
197 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
198 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
199 pci_set_region(r, bus_start, phys_start, pci_sz,
200 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
201 PCI_REGION_PREFETCH);
202 sz -= pci_sz;
203 bus_start += pci_sz;
204 phys_start += pci_sz;
205 set_inbound_window(pi--, r++, pci_sz);
206 }
207 #endif
208
209 #ifdef CONFIG_PHYS_64BIT
210 if (sz && (((u64)gd->ram_size) < (1ull << 32)))
211 printf("Was not able to map all of memory via "
212 "inbound windows -- %lld remaining\n", sz);
213 #endif
214
215 hose->region_count = r - hose->regions;
216
217 return 1;
218 }
219
220 void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
221 {
222 u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
223 u32 cfg_data = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_data;
224 u16 temp16;
225 u32 temp32;
226 int enabled, r, inbound = 0;
227 u16 ltssm;
228 u8 temp8, pcie_cap;
229 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
230 struct pci_region *reg = hose->regions + hose->region_count;
231 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
232
233 /* Initialize ATMU registers based on hose regions and flags */
234 volatile pot_t *po = &pci->pot[1]; /* skip 0 */
235 volatile pit_t *pi = &pci->pit[2]; /* ranges from: 3 to 1 */
236
237 u64 out_hi = 0, out_lo = -1ULL;
238 u32 pcicsrbar, pcicsrbar_sz;
239
240 pci_setup_indirect(hose, cfg_addr, cfg_data);
241
242 /* Handle setup of outbound windows first */
243 for (r = 0; r < hose->region_count; r++) {
244 unsigned long flags = hose->regions[r].flags;
245 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
246
247 flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE;
248 if (flags != PCI_REGION_SYS_MEMORY) {
249 u64 start = hose->regions[r].bus_start;
250 u64 end = start + hose->regions[r].size;
251
252 out_be32(&po->powbar, hose->regions[r].phys_start >> 12);
253 out_be32(&po->potar, start >> 12);
254 #ifdef CONFIG_SYS_PCI_64BIT
255 out_be32(&po->potear, start >> 44);
256 #else
257 out_be32(&po->potear, 0);
258 #endif
259 if (hose->regions[r].flags & PCI_REGION_IO) {
260 out_be32(&po->powar, POWAR_EN | sz |
261 POWAR_IO_READ | POWAR_IO_WRITE);
262 } else {
263 out_be32(&po->powar, POWAR_EN | sz |
264 POWAR_MEM_READ | POWAR_MEM_WRITE);
265 out_lo = min(start, out_lo);
266 out_hi = max(end, out_hi);
267 }
268 po++;
269 }
270 }
271 debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi);
272
273 /* setup PCSRBAR/PEXCSRBAR */
274 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
275 pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
276 pcicsrbar_sz = ~pcicsrbar_sz + 1;
277
278 if (out_hi < (0x100000000ull - pcicsrbar_sz) ||
279 (out_lo > 0x100000000ull))
280 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
281 else
282 pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz;
283 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar);
284
285 out_lo = min(out_lo, (u64)pcicsrbar);
286
287 debug("PCICSRBAR @ 0x%x\n", pcicsrbar);
288
289 pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS,
290 pcicsrbar_sz, PCI_REGION_SYS_MEMORY);
291 hose->region_count++;
292
293 /* see if we are a PCIe or PCI controller */
294 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
295
296 /* inbound */
297 inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi);
298
299 for (r = 0; r < hose->region_count; r++)
300 debug("PCI reg:%d %016llx:%016llx %016llx %08x\n", r,
301 (u64)hose->regions[r].phys_start,
302 hose->regions[r].bus_start,
303 hose->regions[r].size,
304 hose->regions[r].flags);
305
306 pci_register_hose(hose);
307 pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */
308 hose->current_busno = hose->first_busno;
309
310 out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */
311 out_be32(&pci->peer, ~0x20140); /* Enable All Error Interupts except
312 * - Master abort (pci)
313 * - Master PERR (pci)
314 * - ICCA (PCIe)
315 */
316 pci_hose_read_config_dword(hose, dev, PCI_DCR, &temp32);
317 temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */
318 pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32);
319
320 if (pcie_cap == PCI_CAP_ID_EXP) {
321 pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm);
322 enabled = ltssm >= PCI_LTSSM_L0;
323
324 #ifdef CONFIG_FSL_PCIE_RESET
325 if (ltssm == 1) {
326 int i;
327 debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm);
328 /* assert PCIe reset */
329 setbits_be32(&pci->pdb_stat, 0x08000000);
330 (void) in_be32(&pci->pdb_stat);
331 udelay(100);
332 debug(" Asserting PCIe reset @%x = %x\n",
333 &pci->pdb_stat, in_be32(&pci->pdb_stat));
334 /* clear PCIe reset */
335 clrbits_be32(&pci->pdb_stat, 0x08000000);
336 asm("sync;isync");
337 for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
338 pci_hose_read_config_word(hose, dev, PCI_LTSSM,
339 &ltssm);
340 udelay(1000);
341 debug("....PCIe link error. "
342 "LTSSM=0x%02x.\n", ltssm);
343 }
344 enabled = ltssm >= PCI_LTSSM_L0;
345
346 /* we need to re-write the bar0 since a reset will
347 * clear it
348 */
349 pci_hose_write_config_dword(hose, dev,
350 PCI_BASE_ADDRESS_0, pcicsrbar);
351 }
352 #endif
353
354 if (!enabled) {
355 /* Let the user know there's no PCIe link */
356 printf("no link, regs @ 0x%lx\n", pci_info->regs);
357 hose->last_busno = hose->first_busno;
358 return;
359 }
360
361 out_be32(&pci->pme_msg_det, 0xffffffff);
362 out_be32(&pci->pme_msg_int_en, 0xffffffff);
363
364 /* Print the negotiated PCIe link width */
365 pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16);
366 printf("x%d, regs @ 0x%lx\n", (temp16 & 0x3f0 ) >> 4,
367 pci_info->regs);
368
369 hose->current_busno++; /* Start scan with secondary */
370 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
371 }
372
373 /* Use generic setup_device to initialize standard pci regs,
374 * but do not allocate any windows since any BAR found (such
375 * as PCSRBAR) is not in this cpu's memory space.
376 */
377 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
378 hose->pci_prefetch, hose->pci_io);
379
380 if (inbound) {
381 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
382 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
383 temp16 | PCI_COMMAND_MEMORY);
384 }
385
386 #ifndef CONFIG_PCI_NOSCAN
387 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8);
388
389 /* Programming Interface (PCI_CLASS_PROG)
390 * 0 == pci host or pcie root-complex,
391 * 1 == pci agent or pcie end-point
392 */
393 if (!temp8) {
394 debug(" Scanning PCI bus %02x\n",
395 hose->current_busno);
396 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
397 } else {
398 debug(" Not scanning PCI bus %02x. PI=%x\n",
399 hose->current_busno, temp8);
400 hose->last_busno = hose->current_busno;
401 }
402
403 /* if we are PCIe - update limit regs and subordinate busno
404 * for the virtual P2P bridge
405 */
406 if (pcie_cap == PCI_CAP_ID_EXP) {
407 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
408 }
409 #else
410 hose->last_busno = hose->current_busno;
411 #endif
412
413 /* Clear all error indications */
414 if (pcie_cap == PCI_CAP_ID_EXP)
415 out_be32(&pci->pme_msg_det, 0xffffffff);
416 out_be32(&pci->pedr, 0xffffffff);
417
418 pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16);
419 if (temp16) {
420 pci_hose_write_config_word(hose, dev, PCI_DSR, 0xffff);
421 }
422
423 pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
424 if (temp16) {
425 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
426 }
427 }
428
429 int fsl_is_pci_agent(struct pci_controller *hose)
430 {
431 u8 prog_if;
432 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
433
434 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if);
435
436 return (prog_if == FSL_PROG_IF_AGENT);
437 }
438
439 int fsl_pci_init_port(struct fsl_pci_info *pci_info,
440 struct pci_controller *hose, int busno)
441 {
442 volatile ccsr_fsl_pci_t *pci;
443 struct pci_region *r;
444 pci_dev_t dev = PCI_BDF(busno,0,0);
445 u8 pcie_cap;
446
447 pci = (ccsr_fsl_pci_t *) pci_info->regs;
448
449 /* on non-PCIe controllers we don't have pme_msg_det so this code
450 * should do nothing since the read will return 0
451 */
452 if (in_be32(&pci->pme_msg_det)) {
453 out_be32(&pci->pme_msg_det, 0xffffffff);
454 debug (" with errors. Clearing. Now 0x%08x",
455 pci->pme_msg_det);
456 }
457
458 r = hose->regions + hose->region_count;
459
460 /* outbound memory */
461 pci_set_region(r++,
462 pci_info->mem_bus,
463 pci_info->mem_phys,
464 pci_info->mem_size,
465 PCI_REGION_MEM);
466
467 /* outbound io */
468 pci_set_region(r++,
469 pci_info->io_bus,
470 pci_info->io_phys,
471 pci_info->io_size,
472 PCI_REGION_IO);
473
474 hose->region_count = r - hose->regions;
475 hose->first_busno = busno;
476
477 fsl_pci_init(hose, pci_info);
478
479 if (fsl_is_pci_agent(hose)) {
480 fsl_pci_config_unlock(hose);
481 hose->last_busno = hose->first_busno;
482 }
483
484 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
485 printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ?
486 "e" : "", pci_info->pci_num,
487 hose->first_busno, hose->last_busno);
488
489 return(hose->last_busno + 1);
490 }
491
492 /* Enable inbound PCI config cycles for agent/endpoint interface */
493 void fsl_pci_config_unlock(struct pci_controller *hose)
494 {
495 pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
496 u8 agent;
497 u8 pcie_cap;
498 u16 pbfr;
499
500 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &agent);
501 if (!agent)
502 return;
503
504 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
505 if (pcie_cap != 0x0) {
506 /* PCIe - set CFG_READY bit of Configuration Ready Register */
507 pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1);
508 } else {
509 /* PCI - clear ACL bit of PBFR */
510 pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
511 pbfr &= ~0x20;
512 pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr);
513 }
514 }
515
516 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || \
517 defined(CONFIG_PCIE3) || defined(CONFIG_PCIE4)
518 int fsl_configure_pcie(struct fsl_pci_info *info,
519 struct pci_controller *hose,
520 const char *connected, int busno)
521 {
522 int is_endpoint;
523
524 set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
525 set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
526
527 is_endpoint = fsl_setup_hose(hose, info->regs);
528 printf("PCIe%u: %s", info->pci_num,
529 is_endpoint ? "Endpoint" : "Root Complex");
530 if (connected)
531 printf(" of %s", connected);
532 puts(", ");
533
534 return fsl_pci_init_port(info, hose, busno);
535 }
536
537 #if defined(CONFIG_FSL_CORENET)
538 #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1
539 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2
540 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3
541 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4
542 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
543 #elif defined(CONFIG_MPC85xx)
544 #define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE
545 #define _DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2
546 #define _DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3
547 #define _DEVDISR_PCIE4 0
548 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
549 #elif defined(CONFIG_MPC86xx)
550 #define _DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIE1
551 #define _DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIE2
552 #define _DEVDISR_PCIE3 0
553 #define _DEVDISR_PCIE4 0
554 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \
555 (&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
556 #else
557 #error "No defines for DEVDISR_PCIE"
558 #endif
559
560 /* Implement a dummy function for those platforms w/o SERDES */
561 static const char *__board_serdes_name(enum srds_prtcl device)
562 {
563 switch (device) {
564 #ifdef CONFIG_SYS_PCIE1_NAME
565 case PCIE1:
566 return CONFIG_SYS_PCIE1_NAME;
567 #endif
568 #ifdef CONFIG_SYS_PCIE2_NAME
569 case PCIE2:
570 return CONFIG_SYS_PCIE2_NAME;
571 #endif
572 #ifdef CONFIG_SYS_PCIE3_NAME
573 case PCIE3:
574 return CONFIG_SYS_PCIE3_NAME;
575 #endif
576 #ifdef CONFIG_SYS_PCIE4_NAME
577 case PCIE4:
578 return CONFIG_SYS_PCIE4_NAME;
579 #endif
580 default:
581 return NULL;
582 }
583
584 return NULL;
585 }
586
587 __attribute__((weak, alias("__board_serdes_name"))) const char *
588 board_serdes_name(enum srds_prtcl device);
589
590 static u32 devdisr_mask[] = {
591 _DEVDISR_PCIE1,
592 _DEVDISR_PCIE2,
593 _DEVDISR_PCIE3,
594 _DEVDISR_PCIE4,
595 };
596
597 int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
598 struct fsl_pci_info *pci_info)
599 {
600 struct pci_controller *hose;
601 int num = dev - PCIE1;
602
603 hose = calloc(1, sizeof(struct pci_controller));
604 if (!hose)
605 return busno;
606
607 if (is_serdes_configured(dev) && !(devdisr & devdisr_mask[num])) {
608 busno = fsl_configure_pcie(pci_info, hose,
609 board_serdes_name(dev), busno);
610 } else {
611 printf("PCIe%d: disabled\n", num + 1);
612 }
613
614 return busno;
615 }
616
617 int fsl_pcie_init_board(int busno)
618 {
619 struct fsl_pci_info pci_info;
620 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
621 u32 devdisr = in_be32(&gur->devdisr);
622
623 #ifdef CONFIG_PCIE1
624 SET_STD_PCIE_INFO(pci_info, 1);
625 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info);
626 #else
627 setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */
628 #endif
629
630 #ifdef CONFIG_PCIE2
631 SET_STD_PCIE_INFO(pci_info, 2);
632 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE2, &pci_info);
633 #else
634 setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */
635 #endif
636
637 #ifdef CONFIG_PCIE3
638 SET_STD_PCIE_INFO(pci_info, 3);
639 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE3, &pci_info);
640 #else
641 setbits_be32(&gur->devdisr, _DEVDISR_PCIE3); /* disable */
642 #endif
643
644 #ifdef CONFIG_PCIE4
645 SET_STD_PCIE_INFO(pci_info, 4);
646 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE4, &pci_info);
647 #else
648 setbits_be32(&gur->devdisr, _DEVDISR_PCIE4); /* disable */
649 #endif
650
651 return busno;
652 }
653 #else
654 int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
655 struct fsl_pci_info *pci_info)
656 {
657 return busno;
658 }
659
660 int fsl_pcie_init_board(int busno)
661 {
662 return busno;
663 }
664 #endif
665
666 #ifdef CONFIG_OF_BOARD_SETUP
667 #include <libfdt.h>
668 #include <fdt_support.h>
669
670 void ft_fsl_pci_setup(void *blob, const char *pci_compat,
671 unsigned long ctrl_addr)
672 {
673 int off;
674 u32 bus_range[2];
675 phys_addr_t p_ctrl_addr = (phys_addr_t)ctrl_addr;
676 struct pci_controller *hose;
677
678 hose = find_hose_by_cfg_addr((void *)(ctrl_addr));
679
680 /* convert ctrl_addr to true physical address */
681 p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR;
682 p_ctrl_addr += CONFIG_SYS_CCSRBAR_PHYS;
683
684 off = fdt_node_offset_by_compat_reg(blob, pci_compat, p_ctrl_addr);
685
686 if (off < 0)
687 return;
688
689 /* We assume a cfg_addr not being set means we didn't setup the controller */
690 if ((hose == NULL) || (hose->cfg_addr == NULL)) {
691 fdt_del_node(blob, off);
692 } else {
693 bus_range[0] = 0;
694 bus_range[1] = hose->last_busno - hose->first_busno;
695 fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
696 fdt_pci_dma_ranges(blob, off, hose);
697 }
698 }
699 #endif
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